Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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| Tool Version      : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date              : Sat Sep  7 17:35:05 2024
| Host              : linux-139028 running 64-bit Debian GNU/Linux 12 (bookworm)
| Command           : report_timing_summary -max_paths 10 -report_unconstrained -file d_1_wrapper_timing_summary_routed.rpt -pb d_1_wrapper_timing_summary_routed.pb -rpx d_1_wrapper_timing_summary_routed.rpx
| Design            : d_1_wrapper
| Device            : xczu49dr-ffvf1760
| Speed File        : -2  PRODUCTION 1.32 01-31-2021
| Temperature Grade : E
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

Rule       Severity  Description                                                                                            Violations  
---------  --------  -----------------------------------------------------------------------------------------------------  ----------  
LUTAR-1    Warning   LUT drives async reset alert                                                                           72          
TIMING-9   Warning   Unknown CDC Logic                                                                                      1           
TIMING-10  Warning   Missing property on synchronizer                                                                       1           
TIMING-18  Warning   Missing input or output delay                                                                          42          
TIMING-24  Warning   Overridden Max delay datapath only                                                                     8           
TIMING-47  Warning   False path, asynchronous clock group or max delay datapath only constraint between synchronous clocks  2           
CLKC-40    Advisory  Substitute PLLE4 for MMCME4 check                                                                      1           
CLKC-56    Advisory  MMCME4 with global clock driver has no LOC                                                             1           
XDCB-6     Advisory  Timing constraint pointing to hierarchical pins                                                        1           

Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (2)
6. checking no_output_delay (41)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (2)
------------------------------
 There are 2 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (41)
--------------------------------
 There are 41 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.019        0.000                      0               670456        0.009        0.000                      0               669922        0.000        0.000                       0                239160  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                                                                                                Waveform(ns)           Period(ns)      Frequency(MHz)
-----                                                                                                ------------           ----------      --------------
RFADC0_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFADC1_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFADC2_CLK                                                                                           {0.000 1.628}          3.255           307.220         
RFADC3_CLK                                                                                           {0.000 5.000}          10.000          100.000         
RFDAC0_CLK                                                                                           {0.000 1.018}          2.035           491.400         
RFDAC1_CLK                                                                                           {0.000 1.018}          2.035           491.400         
RFDAC2_CLK                                                                                           {0.000 1.018}          2.035           491.400         
RFDAC3_CLK                                                                                           {0.000 5.000}          10.000          100.000         
clk_pl_0                                                                                             {0.000 5.000}          10.000          100.000         
  clk_out1_d_1_clk_core_0                                                                            {0.000 2.500}          5.000           200.000         
clk_pl_1                                                                                             {0.000 250.000}        500.000         2.000           
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {0.000 25.000}         50.000          20.000          
default_sysclk_c0_300mhz_clk_p                                                                       {0.000 1.667}          3.334           299.940         
  mmcm_clkout0                                                                                       {0.000 1.500}          3.001           333.267         
    pll_clk[0]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[0]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
    pll_clk[1]                                                                                       {0.000 0.188}          0.375           2666.133        
      pll_clk[1]_DIV                                                                                 {0.000 1.500}          3.001           333.267         
  mmcm_clkout5                                                                                       {0.000 6.001}          12.002          83.317          
  mmcm_clkout6                                                                                       {0.000 3.001}          6.001           166.633         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                                                                                                    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                                                                                                    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
RFADC2_CLK                                                                                                 0.331        0.000                      0               123525        0.009        0.000                      0               123525        0.977        0.000                       0                 40416  
RFDAC2_CLK                                                                                                 0.019        0.000                      0               224814        0.010        0.000                      0               224814        0.377        0.000                       0                 84488  
clk_pl_0                                                                                                   1.952        0.000                      0               229789        0.009        0.000                      0               229789        1.000        0.000                       0                 81110  
  clk_out1_d_1_clk_core_0                                                                                  0.752        0.000                      0                10229        0.016        0.000                      0                10229        1.958        0.000                       0                  3283  
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       14.972        0.000                      0                  992        0.016        0.000                      0                  992       24.468        0.000                       0                   479  
default_sysclk_c0_300mhz_clk_p                                                                             1.983        0.000                      0                   23        0.052        0.000                      0                   23        0.500        0.000                       0                    19  
  mmcm_clkout0                                                                                             0.106        0.000                      0                69978        0.012        0.000                      0                69978        0.000        0.000                       0                 27068  
    pll_clk[0]                                                                                                                                                                                                                                         0.000        0.000                       0                     9  
      pll_clk[0]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    40  
    pll_clk[1]                                                                                                                                                                                                                                         0.000        0.000                       0                     8  
      pll_clk[1]_DIV                                                                                                                                                                                                                                   0.300        0.000                       0                    27  
  mmcm_clkout5                                                                                             9.414        0.000                      0                  827        0.030        0.000                      0                  827        5.469        0.000                       0                   570  
  mmcm_clkout6                                                                                             1.605        0.000                      0                 5376        0.021        0.000                      0                 5046        1.018        0.000                       0                  1643  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock                                                                                           To Clock                                                                                                 WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                           --------                                                                                                 -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
mmcm_clkout5                                                                                         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       11.414        0.000                      0                    8                                                                        
mmcm_clkout5                                                                                         mmcm_clkout0                                                                                               2.056        0.000                      0                   28                                                                        
mmcm_clkout6                                                                                         mmcm_clkout0                                                                                               1.557        0.000                      0                  115                                                                        
mmcm_clkout0                                                                                         pll_clk[0]_DIV                                                                                             0.754        0.000                      0                  352        0.505        0.000                      0                  352  
mmcm_clkout0                                                                                         pll_clk[1]_DIV                                                                                             0.475        0.000                      0                  236        0.588        0.000                      0                  236  
dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  mmcm_clkout5                                                                                              49.565        0.000                      0                    8                                                                        
mmcm_clkout0                                                                                         mmcm_clkout5                                                                                              10.503        0.000                      0                   10                                                                        
mmcm_clkout0                                                                                         mmcm_clkout6                                                                                               1.259        0.000                      0                   36        0.316        0.000                      0                    1  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                                 WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------                                                                                           ----------                                                                                           --------                                                                                                 -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
**async_default**                                                                                    clk_out1_d_1_clk_core_0                                                                              clk_out1_d_1_clk_core_0                                                                                    1.755        0.000                      0                 1675        1.423        0.000                      0                 1675  
**async_default**                                                                                    clk_pl_0                                                                                             clk_pl_0                                                                                                   6.960        0.000                      0                 2230        0.153        0.000                      0                 2230  
**async_default**                                                                                    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK       48.923        0.000                      0                  100        0.113        0.000                      0                  100  
**async_default**                                                                                    mmcm_clkout5                                                                                         mmcm_clkout5                                                                                              10.805        0.000                      0                  105        0.105        0.000                      0                  105  


------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                           
----------                                                                                           ----------                                                                                           --------                                                                                           
(none)                                                                                               RFDAC2_CLK                                                                                                                                                                                                
(none)                                                                                                                                                                                                    RFADC2_CLK                                                                                           
(none)                                                                                               RFADC2_CLK                                                                                           RFADC2_CLK                                                                                           
(none)                                                                                               RFDAC2_CLK                                                                                           RFADC2_CLK                                                                                           
(none)                                                                                               clk_pl_0                                                                                             RFADC2_CLK                                                                                           
(none)                                                                                               mmcm_clkout0                                                                                         RFADC2_CLK                                                                                           
(none)                                                                                                                                                                                                    RFDAC2_CLK                                                                                           
(none)                                                                                               RFADC2_CLK                                                                                           RFDAC2_CLK                                                                                           
(none)                                                                                               RFDAC2_CLK                                                                                           RFDAC2_CLK                                                                                           
(none)                                                                                               clk_out1_d_1_clk_core_0                                                                              RFDAC2_CLK                                                                                           
(none)                                                                                               clk_pl_0                                                                                             RFDAC2_CLK                                                                                           
(none)                                                                                               RFDAC2_CLK                                                                                           clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                               clk_pl_0                                                                                             clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                                                                                                                                    clk_pl_0                                                                                             
(none)                                                                                               RFADC0_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC1_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC2_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFADC3_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC0_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC1_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC2_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               RFDAC3_CLK                                                                                           clk_pl_0                                                                                             
(none)                                                                                               clk_out1_d_1_clk_core_0                                                                              clk_pl_0                                                                                             
(none)                                                                                               clk_pl_0                                                                                             clk_pl_0                                                                                             
(none)                                                                                               mmcm_clkout5                                                                                         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  
(none)                                                                                               clk_pl_0                                                                                             default_sysclk_c0_300mhz_clk_p                                                                       
(none)                                                                                               RFADC2_CLK                                                                                           mmcm_clkout0                                                                                         
(none)                                                                                               RFDAC2_CLK                                                                                           mmcm_clkout0                                                                                         
(none)                                                                                               clk_pl_0                                                                                             mmcm_clkout0                                                                                         
(none)                                                                                               default_sysclk_c0_300mhz_clk_p                                                                       mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout5                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               mmcm_clkout6                                                                                         mmcm_clkout0                                                                                         
(none)                                                                                               dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  mmcm_clkout5                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout5                                                                                         
(none)                                                                                               default_sysclk_c0_300mhz_clk_p                                                                       mmcm_clkout6                                                                                         
(none)                                                                                               mmcm_clkout0                                                                                         mmcm_clkout6                                                                                         
(none)                                                                                               mmcm_clkout6                                                                                         mmcm_clkout6                                                                                         


------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------

Path Group                                                                                           From Clock                                                                                           To Clock                                                                                           
----------                                                                                           ----------                                                                                           --------                                                                                           
(none)                                                                                               clk_pl_0                                                                                                                                                                                                  
(none)                                                                                               clk_pl_1                                                                                                                                                                                                  
(none)                                                                                               mmcm_clkout0                                                                                                                                                                                              
(none)                                                                                                                                                                                                    clk_out1_d_1_clk_core_0                                                                              
(none)                                                                                                                                                                                                    clk_pl_0                                                                                             
(none)                                                                                                                                                                                                    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  
(none)                                                                                                                                                                                                    default_sysclk_c0_300mhz_clk_p                                                                       


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  RFADC2_CLK
  To Clock:  RFADC2_CLK

Setup :            0  Failing Endpoints,  Worst Slack        0.331ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.009ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.977ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.331ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_27/ADDRARDADDR[6]
                            (rising edge-triggered cell RAMB36E2 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.255ns  (RFADC2_CLK rise@3.255ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        2.583ns  (logic 0.079ns (3.058%)  route 2.504ns (96.942%))
  Logic Levels:           0  
  Clock Path Skew:        -0.020ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.356ns = ( 5.611 - 3.255 ) 
    Source Clock Delay      (SCD):    2.607ns
    Clock Pessimism Removal (CPR):    0.231ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.081ns (routing 0.888ns, distribution 1.193ns)
  Clock Net Delay (Destination): 1.970ns (routing 0.801ns, distribution 1.169ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.081     2.607    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X64Y121        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y121        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.686 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]/Q
                         net (fo=33, routed)          2.504     5.190    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_28_0[3]
    RAMB36_X4Y23         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_27/ADDRARDADDR[6]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      3.255     3.255 r  
    RFADC_X0Y2           RFADC                        0.000     3.255 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     3.377 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     3.527    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.641 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.970     5.611    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X4Y23         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_27/CLKARDCLK
                         clock pessimism              0.231     5.842    
                         clock uncertainty           -0.035     5.807    
    RAMB36_X4Y23         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[6])
                                                     -0.285     5.522    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_27
  -------------------------------------------------------------------
                         required time                          5.522    
                         arrival time                          -5.190    
  -------------------------------------------------------------------
                         slack                                  0.331    

Slack (MET) :             0.342ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_16/ADDRARDADDR[8]
                            (rising edge-triggered cell RAMB36E2 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.255ns  (RFADC2_CLK rise@3.255ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        2.511ns  (logic 0.079ns (3.146%)  route 2.432ns (96.854%))
  Logic Levels:           0  
  Clock Path Skew:        -0.083ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.254ns = ( 5.509 - 3.255 ) 
    Source Clock Delay      (SCD):    2.568ns
    Clock Pessimism Removal (CPR):    0.231ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.042ns (routing 0.888ns, distribution 1.154ns)
  Clock Net Delay (Destination): 1.868ns (routing 0.801ns, distribution 1.067ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.042     2.568    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X64Y120        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y120        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.647 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[4]/Q
                         net (fo=32, routed)          2.432     5.079    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_28_0[4]
    RAMB36_X6Y12         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_16/ADDRARDADDR[8]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      3.255     3.255 r  
    RFADC_X0Y2           RFADC                        0.000     3.255 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     3.377 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     3.527    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.641 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.868     5.509    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X6Y12         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_16/CLKARDCLK
                         clock pessimism              0.231     5.740    
                         clock uncertainty           -0.035     5.705    
    RAMB36_X6Y12         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[8])
                                                     -0.283     5.422    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_16
  -------------------------------------------------------------------
                         required time                          5.422    
                         arrival time                          -5.079    
  -------------------------------------------------------------------
                         slack                                  0.342    

Slack (MET) :             0.368ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_26/ADDRARDADDR[6]
                            (rising edge-triggered cell RAMB36E2 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.255ns  (RFADC2_CLK rise@3.255ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        2.545ns  (logic 0.079ns (3.104%)  route 2.466ns (96.896%))
  Logic Levels:           0  
  Clock Path Skew:        -0.021ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.355ns = ( 5.610 - 3.255 ) 
    Source Clock Delay      (SCD):    2.607ns
    Clock Pessimism Removal (CPR):    0.231ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.081ns (routing 0.888ns, distribution 1.193ns)
  Clock Net Delay (Destination): 1.969ns (routing 0.801ns, distribution 1.168ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.081     2.607    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X64Y121        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y121        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.686 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[3]/Q
                         net (fo=33, routed)          2.466     5.152    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_28_0[3]
    RAMB36_X4Y22         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_26/ADDRARDADDR[6]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      3.255     3.255 r  
    RFADC_X0Y2           RFADC                        0.000     3.255 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     3.377 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     3.527    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.641 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.969     5.610    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X4Y22         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_26/CLKARDCLK
                         clock pessimism              0.231     5.841    
                         clock uncertainty           -0.035     5.806    
    RAMB36_X4Y22         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[6])
                                                     -0.285     5.521    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_26
  -------------------------------------------------------------------
                         required time                          5.521    
                         arrival time                          -5.152    
  -------------------------------------------------------------------
                         slack                                  0.368    

Slack (MET) :             0.373ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/out_q_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15/DINPADINP[0]
                            (rising edge-triggered cell RAMB36E2 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.255ns  (RFADC2_CLK rise@3.255ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        2.634ns  (logic 0.079ns (2.999%)  route 2.555ns (97.001%))
  Logic Levels:           0  
  Clock Path Skew:        0.015ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.450ns = ( 5.705 - 3.255 ) 
    Source Clock Delay      (SCD):    2.662ns
    Clock Pessimism Removal (CPR):    0.227ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.136ns (routing 0.888ns, distribution 1.248ns)
  Clock Net Delay (Destination): 2.064ns (routing 0.801ns, distribution 1.263ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.136     2.662    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X52Y171        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/out_q_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y171        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.741 r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/avg_i/out_q_r_reg[0]/Q
                         net (fo=17, routed)          2.555     5.296    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/dia[32]
    RAMB36_X3Y38         RAMB36E2                                     r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15/DINPADINP[0]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      3.255     3.255 r  
    RFADC_X0Y2           RFADC                        0.000     3.255 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     3.377 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     3.527    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.641 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.064     5.705    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X3Y38         RAMB36E2                                     r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15/CLKARDCLK
                         clock pessimism              0.227     5.932    
                         clock uncertainty           -0.035     5.897    
    RAMB36_X3Y38         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_DINPADINP[0])
                                                     -0.228     5.669    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15
  -------------------------------------------------------------------
                         required time                          5.669    
                         arrival time                          -5.296    
  -------------------------------------------------------------------
                         slack                                  0.373    

Slack (MET) :             0.384ns  (required time - arrival time)
  Source:                 d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_17/ADDRARDADDR[8]
                            (rising edge-triggered cell RAMB36E2 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.255ns  (RFADC2_CLK rise@3.255ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        2.469ns  (logic 0.079ns (3.200%)  route 2.390ns (96.800%))
  Logic Levels:           0  
  Clock Path Skew:        -0.084ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.253ns = ( 5.508 - 3.255 ) 
    Source Clock Delay      (SCD):    2.568ns
    Clock Pessimism Removal (CPR):    0.231ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.042ns (routing 0.888ns, distribution 1.154ns)
  Clock Net Delay (Destination): 1.867ns (routing 0.801ns, distribution 1.066ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.042     2.568    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X64Y120        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y120        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.647 r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/addr_r_reg[4]/Q
                         net (fo=32, routed)          2.390     5.037    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_28_0[4]
    RAMB36_X6Y13         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_17/ADDRARDADDR[8]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      3.255     3.255 r  
    RFADC_X0Y2           RFADC                        0.000     3.255 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     3.377 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     3.527    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.641 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.867     5.508    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/s_axis_aclk
    RAMB36_X6Y13         RAMB36E2                                     r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_17/CLKARDCLK
                         clock pessimism              0.231     5.739    
                         clock uncertainty           -0.035     5.704    
    RAMB36_X6Y13         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[8])
                                                     -0.283     5.421    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_17
  -------------------------------------------------------------------
                         required time                          5.421    
                         arrival time                          -5.037    
  -------------------------------------------------------------------
                         slack                                  0.384    

Slack (MET) :             0.416ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[524]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[20]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.255ns  (RFADC2_CLK rise@3.255ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        2.761ns  (logic 0.819ns (29.663%)  route 1.942ns (70.337%))
  Logic Levels:           3  (DSP_ALU=1 DSP_C_DATA=1 LUT3=1)
  Clock Path Skew:        -0.058ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.264ns = ( 5.519 - 3.255 ) 
    Source Clock Delay      (SCD):    2.612ns
    Clock Pessimism Removal (CPR):    0.290ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.086ns (routing 0.888ns, distribution 1.198ns)
  Clock Net Delay (Destination): 1.878ns (routing 0.801ns, distribution 1.077ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.086     2.612    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X74Y172        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[524]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y172        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.691 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[524]/Q
                         net (fo=16, routed)          1.569     4.260    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/s_axis_phase_tdata[17]
    SLICE_X80Y142        LUT3 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     4.310 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP_i_12/O
                         net (fo=1, routed)           0.373     4.683    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/C[20]
    DSP48E2_X14Y54       DSP_C_DATA (Prop_DSP_C_DATA_DSP48E2_C[20]_C_DATA[20])
                                                      0.105     4.788 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA_INST/C_DATA[20]
                         net (fo=2, routed)           0.000     4.788    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA.C_DATA<20>
    DSP48E2_X14Y54       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[20]_ALU_OUT[20])
                                                      0.585     5.373 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU_INST/ALU_OUT[20]
                         net (fo=1, routed)           0.000     5.373    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU.ALU_OUT<20>
    DSP48E2_X14Y54       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[20]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      3.255     3.255 r  
    RFADC_X0Y2           RFADC                        0.000     3.255 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     3.377 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     3.527    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.641 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.878     5.519    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/CLK
    DSP48E2_X14Y54       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.290     5.809    
                         clock uncertainty           -0.035     5.774    
    DSP48E2_X14Y54       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[20])
                                                      0.015     5.789    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.789    
                         arrival time                          -5.373    
  -------------------------------------------------------------------
                         slack                                  0.416    

Slack (MET) :             0.416ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[524]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[21]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.255ns  (RFADC2_CLK rise@3.255ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        2.761ns  (logic 0.819ns (29.663%)  route 1.942ns (70.337%))
  Logic Levels:           3  (DSP_ALU=1 DSP_C_DATA=1 LUT3=1)
  Clock Path Skew:        -0.058ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.264ns = ( 5.519 - 3.255 ) 
    Source Clock Delay      (SCD):    2.612ns
    Clock Pessimism Removal (CPR):    0.290ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.086ns (routing 0.888ns, distribution 1.198ns)
  Clock Net Delay (Destination): 1.878ns (routing 0.801ns, distribution 1.077ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.086     2.612    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X74Y172        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[524]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y172        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.691 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[524]/Q
                         net (fo=16, routed)          1.569     4.260    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/s_axis_phase_tdata[17]
    SLICE_X80Y142        LUT3 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     4.310 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP_i_12/O
                         net (fo=1, routed)           0.373     4.683    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/C[20]
    DSP48E2_X14Y54       DSP_C_DATA (Prop_DSP_C_DATA_DSP48E2_C[20]_C_DATA[20])
                                                      0.105     4.788 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA_INST/C_DATA[20]
                         net (fo=2, routed)           0.000     4.788    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA.C_DATA<20>
    DSP48E2_X14Y54       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[20]_ALU_OUT[21])
                                                      0.585     5.373 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU_INST/ALU_OUT[21]
                         net (fo=1, routed)           0.000     5.373    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU.ALU_OUT<21>
    DSP48E2_X14Y54       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[21]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      3.255     3.255 r  
    RFADC_X0Y2           RFADC                        0.000     3.255 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     3.377 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     3.527    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.641 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.878     5.519    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/CLK
    DSP48E2_X14Y54       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.290     5.809    
                         clock uncertainty           -0.035     5.774    
    DSP48E2_X14Y54       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[21])
                                                      0.015     5.789    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.789    
                         arrival time                          -5.373    
  -------------------------------------------------------------------
                         slack                                  0.416    

Slack (MET) :             0.416ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[524]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[22]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.255ns  (RFADC2_CLK rise@3.255ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        2.761ns  (logic 0.819ns (29.663%)  route 1.942ns (70.337%))
  Logic Levels:           3  (DSP_ALU=1 DSP_C_DATA=1 LUT3=1)
  Clock Path Skew:        -0.058ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.264ns = ( 5.519 - 3.255 ) 
    Source Clock Delay      (SCD):    2.612ns
    Clock Pessimism Removal (CPR):    0.290ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.086ns (routing 0.888ns, distribution 1.198ns)
  Clock Net Delay (Destination): 1.878ns (routing 0.801ns, distribution 1.077ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.086     2.612    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X74Y172        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[524]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y172        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.691 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[524]/Q
                         net (fo=16, routed)          1.569     4.260    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/s_axis_phase_tdata[17]
    SLICE_X80Y142        LUT3 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     4.310 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP_i_12/O
                         net (fo=1, routed)           0.373     4.683    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/C[20]
    DSP48E2_X14Y54       DSP_C_DATA (Prop_DSP_C_DATA_DSP48E2_C[20]_C_DATA[20])
                                                      0.105     4.788 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA_INST/C_DATA[20]
                         net (fo=2, routed)           0.000     4.788    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA.C_DATA<20>
    DSP48E2_X14Y54       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[20]_ALU_OUT[22])
                                                      0.585     5.373 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU_INST/ALU_OUT[22]
                         net (fo=1, routed)           0.000     5.373    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU.ALU_OUT<22>
    DSP48E2_X14Y54       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[22]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      3.255     3.255 r  
    RFADC_X0Y2           RFADC                        0.000     3.255 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     3.377 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     3.527    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.641 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.878     5.519    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/CLK
    DSP48E2_X14Y54       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.290     5.809    
                         clock uncertainty           -0.035     5.774    
    DSP48E2_X14Y54       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[22])
                                                      0.015     5.789    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.789    
                         arrival time                          -5.373    
  -------------------------------------------------------------------
                         slack                                  0.416    

Slack (MET) :             0.416ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[524]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[23]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.255ns  (RFADC2_CLK rise@3.255ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        2.761ns  (logic 0.819ns (29.663%)  route 1.942ns (70.337%))
  Logic Levels:           3  (DSP_ALU=1 DSP_C_DATA=1 LUT3=1)
  Clock Path Skew:        -0.058ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.264ns = ( 5.519 - 3.255 ) 
    Source Clock Delay      (SCD):    2.612ns
    Clock Pessimism Removal (CPR):    0.290ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.086ns (routing 0.888ns, distribution 1.198ns)
  Clock Net Delay (Destination): 1.878ns (routing 0.801ns, distribution 1.077ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.086     2.612    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X74Y172        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[524]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y172        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.691 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[524]/Q
                         net (fo=16, routed)          1.569     4.260    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/s_axis_phase_tdata[17]
    SLICE_X80Y142        LUT3 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     4.310 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP_i_12/O
                         net (fo=1, routed)           0.373     4.683    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/C[20]
    DSP48E2_X14Y54       DSP_C_DATA (Prop_DSP_C_DATA_DSP48E2_C[20]_C_DATA[20])
                                                      0.105     4.788 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA_INST/C_DATA[20]
                         net (fo=2, routed)           0.000     4.788    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA.C_DATA<20>
    DSP48E2_X14Y54       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[20]_ALU_OUT[23])
                                                      0.585     5.373 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU_INST/ALU_OUT[23]
                         net (fo=1, routed)           0.000     5.373    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU.ALU_OUT<23>
    DSP48E2_X14Y54       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[23]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      3.255     3.255 r  
    RFADC_X0Y2           RFADC                        0.000     3.255 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     3.377 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     3.527    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.641 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.878     5.519    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/CLK
    DSP48E2_X14Y54       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.290     5.809    
                         clock uncertainty           -0.035     5.774    
    DSP48E2_X14Y54       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[23])
                                                      0.015     5.789    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.789    
                         arrival time                          -5.373    
  -------------------------------------------------------------------
                         slack                                  0.416    

Slack (MET) :             0.416ns  (required time - arrival time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[524]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[24]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.255ns  (RFADC2_CLK rise@3.255ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        2.761ns  (logic 0.819ns (29.663%)  route 1.942ns (70.337%))
  Logic Levels:           3  (DSP_ALU=1 DSP_C_DATA=1 LUT3=1)
  Clock Path Skew:        -0.058ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.264ns = ( 5.519 - 3.255 ) 
    Source Clock Delay      (SCD):    2.612ns
    Clock Pessimism Removal (CPR):    0.290ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.086ns (routing 0.888ns, distribution 1.198ns)
  Clock Net Delay (Destination): 1.878ns (routing 0.801ns, distribution 1.077ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.086     2.612    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aclk
    SLICE_X74Y172        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[524]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X74Y172        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.691 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/dds_ctrl_int_r_reg[524]/Q
                         net (fo=16, routed)          1.569     4.260    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/s_axis_phase_tdata[17]
    SLICE_X80Y142        LUT3 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     4.310 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP_i_12/O
                         net (fo=1, routed)           0.373     4.683    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/C[20]
    DSP48E2_X14Y54       DSP_C_DATA (Prop_DSP_C_DATA_DSP48E2_C[20]_C_DATA[20])
                                                      0.105     4.788 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA_INST/C_DATA[20]
                         net (fo=2, routed)           0.000     4.788    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_C_DATA.C_DATA<20>
    DSP48E2_X14Y54       DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[20]_ALU_OUT[24])
                                                      0.585     5.373 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU_INST/ALU_OUT[24]
                         net (fo=1, routed)           0.000     5.373    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_ALU.ALU_OUT<24>
    DSP48E2_X14Y54       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/ALU_OUT[24]
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      3.255     3.255 r  
    RFADC_X0Y2           RFADC                        0.000     3.255 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     3.377 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     3.527    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     3.641 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.878     5.519    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/CLK
    DSP48E2_X14Y54       DSP_OUTPUT                                   r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.290     5.809    
                         clock uncertainty           -0.035     5.774    
    DSP48E2_X14Y54       DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[24])
                                                      0.015     5.789    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/GEN_dds[0].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_dsp48.i_struct.i_single_channel.I_DSP/I_VX5_6.I_DSP/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.789    
                         arrival time                          -5.373    
  -------------------------------------------------------------------
                         slack                                  0.416    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.009ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[16].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][13]_srl1/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.335ns  (logic 0.060ns (17.933%)  route 0.275ns (82.067%))
  Logic Levels:           0  
  Clock Path Skew:        0.269ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.855ns
    Source Clock Delay      (SCD):    2.359ns
    Clock Pessimism Removal (CPR):    0.227ns
  Clock Net Delay (Source):      1.973ns (routing 0.801ns, distribution 1.172ns)
  Clock Net Delay (Destination): 2.329ns (routing 0.888ns, distribution 1.441ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.973     2.359    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[16].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X89Y175        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[16].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y175        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.060     2.419 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[16].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[13]/Q
                         net (fo=2, routed)           0.275     2.693    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/A[13]
    SLICE_X89Y188        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][13]_srl1/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.329     2.855    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X89Y188        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][13]_srl1/CLK
                         clock pessimism             -0.227     2.628    
    SLICE_X89Y188        SRL16E (Hold_F5LUT_SLICEM_CLK_D)
                                                      0.056     2.684    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][13]_srl1
  -------------------------------------------------------------------
                         required time                         -2.684    
                         arrival time                           2.693    
  -------------------------------------------------------------------
                         slack                                  0.009    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[43].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.088ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.820ns
    Source Clock Delay      (SCD):    2.375ns
    Clock Pessimism Removal (CPR):    0.357ns
  Clock Net Delay (Source):      1.989ns (routing 0.801ns, distribution 1.188ns)
  Clock Net Delay (Destination): 2.294ns (routing 0.888ns, distribution 1.406ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.989     2.375    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X93Y97         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y97         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     2.433 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[49].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.072     2.505    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[43].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X93Y98         SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[43].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.294     2.820    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[43].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X93Y98         SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[43].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism             -0.357     2.463    
    SLICE_X93Y98         SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     2.495    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[4].g_symmetric.g_data_sym_array.g_data_sym[43].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -2.495    
                         arrival time                           2.505    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[50].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[44].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.088ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.814ns
    Source Clock Delay      (SCD):    2.369ns
    Clock Pessimism Removal (CPR):    0.357ns
  Clock Net Delay (Source):      1.983ns (routing 0.801ns, distribution 1.182ns)
  Clock Net Delay (Destination): 2.288ns (routing 0.888ns, distribution 1.400ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.983     2.369    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[50].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X93Y92         FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[50].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y92         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     2.427 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[50].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.072     2.499    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[44].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X93Y93         SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[44].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.288     2.814    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[44].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X93Y93         SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[44].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism             -0.357     2.457    
    SLICE_X93Y93         SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     2.489    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[6].g_symmetric.g_data_sym_array.g_data_sym[44].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -2.489    
                         arrival time                           2.499    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[52].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][5]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[46].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[5]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.217ns  (logic 0.057ns (26.267%)  route 0.160ns (73.733%))
  Logic Levels:           0  
  Clock Path Skew:        0.177ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.941ns
    Source Clock Delay      (SCD):    2.516ns
    Clock Pessimism Removal (CPR):    0.248ns
  Clock Net Delay (Source):      2.130ns (routing 0.801ns, distribution 1.329ns)
  Clock Net Delay (Destination): 2.415ns (routing 0.888ns, distribution 1.527ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.130     2.516    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[52].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X113Y54        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[52].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X113Y54        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     2.573 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[52].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][5]/Q
                         net (fo=1, routed)           0.160     2.733    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[46].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[5]
    SLICE_X113Y61        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[46].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[5]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.415     2.941    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[46].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X113Y61        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[46].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[5]_srl6/CLK
                         clock pessimism             -0.248     2.693    
    SLICE_X113Y61        SRL16E (Hold_F6LUT_SLICEM_CLK_D)
                                                      0.029     2.722    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[10].g_symmetric.g_data_sym_array.g_data_sym[46].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[5]_srl6
  -------------------------------------------------------------------
                         required time                         -2.722    
                         arrival time                           2.733    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[2].g_symmetric.g_data_sym_array.g_data_sym[40].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[2].g_symmetric.g_data_sym_array.g_data_sym[34].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.087ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.816ns
    Source Clock Delay      (SCD):    2.376ns
    Clock Pessimism Removal (CPR):    0.354ns
  Clock Net Delay (Source):      1.990ns (routing 0.801ns, distribution 1.189ns)
  Clock Net Delay (Destination): 2.290ns (routing 0.888ns, distribution 1.402ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.990     2.376    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[2].g_symmetric.g_data_sym_array.g_data_sym[40].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X93Y120        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[2].g_symmetric.g_data_sym_array.g_data_sym[40].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y120        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     2.434 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[2].g_symmetric.g_data_sym_array.g_data_sym[40].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.072     2.506    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[2].g_symmetric.g_data_sym_array.g_data_sym[34].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X93Y121        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[2].g_symmetric.g_data_sym_array.g_data_sym[34].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.290     2.816    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[2].g_symmetric.g_data_sym_array.g_data_sym[34].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X93Y121        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[2].g_symmetric.g_data_sym_array.g_data_sym[34].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism             -0.354     2.462    
    SLICE_X93Y121        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     2.494    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[2].g_symmetric.g_data_sym_array.g_data_sym[34].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -2.494    
                         arrival time                           2.506    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[33].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.087ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.946ns
    Source Clock Delay      (SCD):    2.492ns
    Clock Pessimism Removal (CPR):    0.368ns
  Clock Net Delay (Source):      2.106ns (routing 0.801ns, distribution 1.305ns)
  Clock Net Delay (Destination): 2.420ns (routing 0.888ns, distribution 1.532ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.106     2.492    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X109Y65        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y65        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     2.550 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[39].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.072     2.622    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[33].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X109Y66        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[33].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.420     2.946    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[33].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X109Y66        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[33].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism             -0.368     2.578    
    SLICE_X109Y66        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     2.610    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[1].g_symmetric.g_data_sym_array.g_data_sym[33].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -2.610    
                         arrival time                           2.622    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[13].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[7].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.087ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.862ns
    Source Clock Delay      (SCD):    2.418ns
    Clock Pessimism Removal (CPR):    0.358ns
  Clock Net Delay (Source):      2.032ns (routing 0.801ns, distribution 1.231ns)
  Clock Net Delay (Destination): 2.336ns (routing 0.888ns, distribution 1.448ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.032     2.418    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[13].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X93Y185        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[13].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y185        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     2.476 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[13].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.072     2.548    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[7].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X93Y186        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[7].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.336     2.862    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[7].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X93Y186        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[7].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism             -0.358     2.504    
    SLICE_X93Y186        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     2.536    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[12].g_symmetric.g_data_sym_array.g_data_sym[7].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -2.536    
                         arrival time                           2.548    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][9]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[9]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.334ns  (logic 0.060ns (17.964%)  route 0.274ns (82.036%))
  Logic Levels:           0  
  Clock Path Skew:        0.267ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.857ns
    Source Clock Delay      (SCD):    2.363ns
    Clock Pessimism Removal (CPR):    0.227ns
  Clock Net Delay (Source):      1.977ns (routing 0.801ns, distribution 1.176ns)
  Clock Net Delay (Destination): 2.331ns (routing 0.888ns, distribution 1.443ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.977     2.363    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X89Y173        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y173        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.060     2.423 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[21].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][9]/Q
                         net (fo=1, routed)           0.274     2.697    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[9]
    SLICE_X89Y183        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[9]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.331     2.857    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X89Y183        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[9]_srl6/CLK
                         clock pessimism             -0.227     2.630    
    SLICE_X89Y183        SRL16E (Hold_B5LUT_SLICEM_CLK_D)
                                                      0.055     2.685    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[15].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[9]_srl6
  -------------------------------------------------------------------
                         required time                         -2.685    
                         arrival time                           2.697    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[37].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[31].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.615%)  route 0.072ns (55.385%))
  Logic Levels:           0  
  Clock Path Skew:        0.086ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.945ns
    Source Clock Delay      (SCD):    2.492ns
    Clock Pessimism Removal (CPR):    0.368ns
  Clock Net Delay (Source):      2.106ns (routing 0.801ns, distribution 1.305ns)
  Clock Net Delay (Destination): 2.419ns (routing 0.888ns, distribution 1.531ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.106     2.492    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[37].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X109Y67        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[37].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y67        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.058     2.550 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[37].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[1][7]/Q
                         net (fo=1, routed)           0.072     2.622    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[31].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]
    SLICE_X109Y68        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[31].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.419     2.945    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[31].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X109Y68        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[31].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6/CLK
                         clock pessimism             -0.368     2.577    
    SLICE_X109Y68        SRL16E (Hold_H6LUT_SLICEM_CLK_D)
                                                      0.032     2.609    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[13].g_symmetric.g_data_sym_array.g_data_sym[31].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[7]_srl6
  -------------------------------------------------------------------
                         required time                         -2.609    
                         arrival time                           2.622    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[56].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0]_srl1/D
                            (rising edge-triggered cell SRL16E clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             RFADC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFADC2_CLK rise@0.000ns - RFADC2_CLK rise@0.000ns)
  Data Path Delay:        0.249ns  (logic 0.061ns (24.459%)  route 0.188ns (75.541%))
  Logic Levels:           0  
  Clock Path Skew:        0.208ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.815ns
    Source Clock Delay      (SCD):    2.376ns
    Clock Pessimism Removal (CPR):    0.231ns
  Clock Net Delay (Source):      1.990ns (routing 0.801ns, distribution 1.189ns)
  Clock Net Delay (Destination): 2.289ns (routing 0.888ns, distribution 1.401ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.990     2.376    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/aclk
    SLICE_X91Y121        FDRE                                         r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y121        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     2.437 r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[57].g_data_sym_casc_dly.i_data_sym_casc_dly/gen_reg.d_reg_reg[0]/Q
                         net (fo=2, routed)           0.188     2.626    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[56].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/A[0]
    SLICE_X90Y108        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[56].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0]_srl1/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.289     2.815    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[56].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/aclk
    SLICE_X90Y108        SRL16E                                       r  d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[56].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0]_srl1/CLK
                         clock pessimism             -0.231     2.584    
    SLICE_X90Y108        SRL16E (Hold_A6LUT_SLICEM_CLK_D)
                                                      0.029     2.613    d_1_i/axis_dyn_readout_v1_0/inst/readout_top_i/down_conversion_fir_i/fir_i/U0/i_synth/g_single_rate.i_single_rate/g_parallel.g_paths[3].g_symmetric.g_data_sym_array.g_data_sym[56].g_data_sym_casc_buff.i_data_sym_casc_buff/g_buff.i_buff/gen_dly.gen_shiftreg.gen_rtl_delay.delay_bus_reg[0][0]_srl1
  -------------------------------------------------------------------
                         required time                         -2.613    
                         arrival time                           2.626    
  -------------------------------------------------------------------
                         slack                                  0.013    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFADC2_CLK
Waveform(ns):       { 0.000 1.628 }
Period(ns):         3.255
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     RFADC/FABRIC_CLK    n/a            1.626         3.255       1.629      RFADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         3.255       1.900      RAMB36_X2Y31  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         3.255       1.900      RAMB36_X2Y32  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         3.255       1.900      RAMB36_X3Y33  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         3.255       1.900      RAMB36_X3Y34  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         3.255       1.900      RAMB36_X3Y35  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_12/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         3.255       1.900      RAMB36_X3Y36  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_13/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         3.255       1.900      RAMB36_X3Y37  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_14/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         3.255       1.900      RAMB36_X3Y38  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_15/CLKARDCLK
Min Period        n/a     RAMB36E2/CLKARDCLK  n/a            1.355         3.255       1.900      RAMB36_X5Y28  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_16/CLKARDCLK
Low Pulse Width   Slow    RFADC/FABRIC_CLK    n/a            0.650         1.628       0.978      RFADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
Low Pulse Width   Fast    RFADC/FABRIC_CLK    n/a            0.650         1.628       0.978      RFADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.627       1.085      RAMB36_X2Y31  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.628       1.086      RAMB36_X2Y31  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.627       1.085      RAMB36_X2Y32  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.628       1.086      RAMB36_X2Y32  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.628       1.086      RAMB36_X3Y33  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.628       1.086      RAMB36_X3Y33  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
Low Pulse Width   Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.628       1.086      RAMB36_X3Y34  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
Low Pulse Width   Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.628       1.086      RAMB36_X3Y34  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
High Pulse Width  Slow    RFADC/FABRIC_CLK    n/a            0.650         1.627       0.977      RFADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
High Pulse Width  Fast    RFADC/FABRIC_CLK    n/a            0.650         1.628       0.978      RFADC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.627       1.085      RAMB36_X2Y31  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.628       1.086      RAMB36_X2Y31  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_0/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.628       1.086      RAMB36_X2Y32  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.627       1.085      RAMB36_X2Y32  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_1/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.627       1.085      RAMB36_X3Y33  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.628       1.086      RAMB36_X3Y33  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_10/CLKARDCLK
High Pulse Width  Slow    RAMB36E2/CLKARDCLK  n/a            0.542         1.627       1.085      RAMB36_X3Y34  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK
High Pulse Width  Fast    RAMB36E2/CLKARDCLK  n/a            0.542         1.628       1.086      RAMB36_X3Y34  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/bram_i/RAM_reg_bram_11/CLKARDCLK



---------------------------------------------------------------------------------------------------
From Clock:  RFDAC2_CLK
  To Clock:  RFDAC2_CLK

Setup :            0  Failing Endpoints,  Worst Slack        0.019ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.010ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.377ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.019ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.805ns  (logic 0.537ns (29.743%)  route 1.268ns (70.257%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT4=1)
  Clock Path Skew:        -0.100ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.180ns = ( 5.215 - 2.035 ) 
    Source Clock Delay      (SCD):    3.593ns
    Clock Pessimism Removal (CPR):    0.313ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.882ns (routing 1.474ns, distribution 1.408ns)
  Clock Net Delay (Destination): 2.636ns (routing 1.336ns, distribution 1.300ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.882     3.593    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X67Y351        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y351        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.669 f  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[16]/Q
                         net (fo=43, routed)          0.508     4.178    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N[20]
    SLICE_X68Y375        LUT3 (Prop_A5LUT_SLICEL_I2_O)
                                                      0.138     4.316 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__1_i_7/O
                         net (fo=2, routed)           0.250     4.566    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__1_i_7_n_0
    SLICE_X68Y375        LUT4 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.051     4.617 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__1_i_15/O
                         net (fo=1, routed)           0.009     4.626    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__1_i_15_n_0
    SLICE_X68Y375        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[7])
                                                      0.186     4.812 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__1/CO[7]
                         net (fo=1, routed)           0.026     4.838    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__1_n_0
    SLICE_X68Y376        CARRY8 (Prop_CARRY8_SLICEL_CI_O[4])
                                                      0.086     4.924 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__2/O[4]
                         net (fo=1, routed)           0.475     5.399    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_88[28]
    SLICE_X72Y375        SRL16E                                       r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.636     5.215    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X72Y375        SRL16E                                       r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/CLK
                         clock pessimism              0.313     5.528    
                         clock uncertainty           -0.035     5.493    
    SLICE_X72Y375        SRL16E (Setup_D5LUT_SLICEM_CLK_D)
                                                     -0.075     5.418    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r
  -------------------------------------------------------------------
                         required time                          5.418    
                         arrival time                          -5.399    
  -------------------------------------------------------------------
                         slack                                  0.019    

Slack (MET) :             0.032ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/ENARDEN
                            (rising edge-triggered cell RAMB36E2 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.430ns  (logic 0.080ns (5.594%)  route 1.350ns (94.406%))
  Logic Levels:           0  
  Clock Path Skew:        -0.195ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.104ns = ( 5.139 - 2.035 ) 
    Source Clock Delay      (SCD):    3.604ns
    Clock Pessimism Removal (CPR):    0.305ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.893ns (routing 1.474ns, distribution 1.419ns)
  Clock Net Delay (Destination): 2.560ns (routing 1.336ns, distribution 1.224ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.893     3.604    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X72Y357        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y357        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     3.684 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg/Q
                         net (fo=4352, routed)        1.350     5.034    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/s_axis_phase_tvalid
    RAMB36_X7Y55         RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/ENARDEN
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.560     5.139    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/aclk
    RAMB36_X7Y55         RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKARDCLK
                         clock pessimism              0.305     5.444    
                         clock uncertainty           -0.035     5.408    
    RAMB36_X7Y55         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ENARDEN)
                                                     -0.342     5.066    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0
  -------------------------------------------------------------------
                         required time                          5.066    
                         arrival time                          -5.034    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.046ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.881ns  (logic 0.497ns (26.424%)  route 1.384ns (73.576%))
  Logic Levels:           5  (CARRY8=3 LUT3=1 LUT4=1)
  Clock Path Skew:        0.003ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.195ns = ( 5.230 - 2.035 ) 
    Source Clock Delay      (SCD):    3.587ns
    Clock Pessimism Removal (CPR):    0.395ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.876ns (routing 1.474ns, distribution 1.402ns)
  Clock Net Delay (Destination): 2.651ns (routing 1.336ns, distribution 1.315ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.876     3.587    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X68Y142        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y142        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     3.668 f  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[9]/Q
                         net (fo=43, routed)          0.610     4.278    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N[13]
    SLICE_X60Y133        LUT3 (Prop_B5LUT_SLICEM_I2_O)
                                                      0.103     4.381 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__0_i_6/O
                         net (fo=2, routed)           0.237     4.618    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__0_i_6_n_0
    SLICE_X60Y133        LUT4 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.051     4.669 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__0_i_14/O
                         net (fo=1, routed)           0.021     4.690    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__0_i_14_n_0
    SLICE_X60Y133        CARRY8 (Prop_CARRY8_SLICEM_S[2]_CO[7])
                                                      0.161     4.851 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__0/CO[7]
                         net (fo=1, routed)           0.026     4.877    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__0_n_0
    SLICE_X60Y134        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     4.892 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__1/CO[7]
                         net (fo=1, routed)           0.026     4.918    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__1_n_0
    SLICE_X60Y135        CARRY8 (Prop_CARRY8_SLICEM_CI_O[4])
                                                      0.086     5.004 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__2/O[4]
                         net (fo=1, routed)           0.464     5.468    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_88[28]
    SLICE_X56Y135        SRL16E                                       r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.651     5.230    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X56Y135        SRL16E                                       r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/CLK
                         clock pessimism              0.395     5.625    
                         clock uncertainty           -0.035     5.589    
    SLICE_X56Y135        SRL16E (Setup_D5LUT_SLICEM_CLK_D)
                                                     -0.075     5.514    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r
  -------------------------------------------------------------------
                         required time                          5.514    
                         arrival time                          -5.468    
  -------------------------------------------------------------------
                         slack                                  0.046    

Slack (MET) :             0.050ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/ENARDEN
                            (rising edge-triggered cell RAMB36E2 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.478ns  (logic 0.079ns (5.346%)  route 1.399ns (94.654%))
  Logic Levels:           0  
  Clock Path Skew:        -0.130ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.250ns = ( 5.285 - 2.035 ) 
    Source Clock Delay      (SCD):    3.688ns
    Clock Pessimism Removal (CPR):    0.309ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.977ns (routing 1.474ns, distribution 1.503ns)
  Clock Net Delay (Destination): 2.706ns (routing 1.336ns, distribution 1.370ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.977     3.688    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X87Y256        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y256        FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     3.767 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_tvalid_r_reg/Q
                         net (fo=4352, routed)        1.399     5.166    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/s_axis_phase_tvalid
    RAMB36_X8Y31         RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/ENARDEN
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.706     5.285    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/aclk
    RAMB36_X8Y31         RAMB36E2                                     r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0/CLKARDCLK
                         clock pessimism              0.309     5.594    
                         clock uncertainty           -0.035     5.558    
    RAMB36_X8Y31         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ENARDEN)
                                                     -0.342     5.216    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_rtl.i_quarter_table.i_block_rom.i_pipe_1.pre_asyn_sin_RAM_op_reg_0
  -------------------------------------------------------------------
                         required time                          5.216    
                         arrival time                          -5.166    
  -------------------------------------------------------------------
                         slack                                  0.050    

Slack (MET) :             0.059ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.814ns  (logic 0.545ns (30.038%)  route 1.269ns (69.962%))
  Logic Levels:           6  (CARRY8=4 LUT3=1 LUT4=1)
  Clock Path Skew:        -0.051ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.250ns = ( 5.285 - 2.035 ) 
    Source Clock Delay      (SCD):    3.691ns
    Clock Pessimism Removal (CPR):    0.390ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.980ns (routing 1.474ns, distribution 1.506ns)
  Clock Net Delay (Destination): 2.706ns (routing 1.336ns, distribution 1.370ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.980     3.691    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X85Y261        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y261        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     3.771 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[1]/Q
                         net (fo=34, routed)          0.481     4.252    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N[5]
    SLICE_X89Y242        LUT3 (Prop_F5LUT_SLICEM_I1_O)
                                                      0.142     4.394 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry_i_2/O
                         net (fo=2, routed)           0.233     4.627    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry_i_2_n_0
    SLICE_X89Y242        LUT4 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.090     4.717 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry_i_7/O
                         net (fo=1, routed)           0.016     4.733    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry_i_7_n_0
    SLICE_X89Y242        CARRY8 (Prop_CARRY8_SLICEM_S[6]_CO[7])
                                                      0.117     4.850 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry/CO[7]
                         net (fo=1, routed)           0.026     4.876    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry_n_0
    SLICE_X89Y243        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     4.891 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__0/CO[7]
                         net (fo=1, routed)           0.026     4.917    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__0_n_0
    SLICE_X89Y244        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     4.932 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__1/CO[7]
                         net (fo=1, routed)           0.026     4.958    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__1_n_0
    SLICE_X89Y245        CARRY8 (Prop_CARRY8_SLICEM_CI_O[4])
                                                      0.086     5.044 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__2/O[4]
                         net (fo=1, routed)           0.461     5.505    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_88[28]
    SLICE_X89Y246        SRL16E                                       r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.706     5.285    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X89Y246        SRL16E                                       r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/CLK
                         clock pessimism              0.390     5.675    
                         clock uncertainty           -0.035     5.639    
    SLICE_X89Y246        SRL16E (Setup_D5LUT_SLICEM_CLK_D)
                                                     -0.075     5.564    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r
  -------------------------------------------------------------------
                         required time                          5.564    
                         arrival time                          -5.505    
  -------------------------------------------------------------------
                         slack                                  0.059    

Slack (MET) :             0.062ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.748ns  (logic 0.544ns (31.117%)  route 1.204ns (68.883%))
  Logic Levels:           6  (CARRY8=4 LUT3=1 LUT4=1)
  Clock Path Skew:        -0.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.243ns = ( 5.278 - 2.035 ) 
    Source Clock Delay      (SCD):    3.689ns
    Clock Pessimism Removal (CPR):    0.332ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.978ns (routing 1.474ns, distribution 1.504ns)
  Clock Net Delay (Destination): 2.699ns (routing 1.336ns, distribution 1.363ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.978     3.689    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X57Y403        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y403        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     3.768 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_r2_reg[1]/Q
                         net (fo=34, routed)          0.428     4.196    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_N[5]
    SLICE_X60Y418        LUT3 (Prop_F5LUT_SLICEM_I1_O)
                                                      0.142     4.338 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry_i_2/O
                         net (fo=2, routed)           0.233     4.571    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry_i_2_n_0
    SLICE_X60Y418        LUT4 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.090     4.661 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry_i_7/O
                         net (fo=1, routed)           0.016     4.677    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry_i_7_n_0
    SLICE_X60Y418        CARRY8 (Prop_CARRY8_SLICEM_S[6]_CO[7])
                                                      0.117     4.794 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry/CO[7]
                         net (fo=1, routed)           0.026     4.820    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry_n_0
    SLICE_X60Y419        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     4.835 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__0/CO[7]
                         net (fo=1, routed)           0.026     4.861    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__0_n_0
    SLICE_X60Y420        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     4.876 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__1/CO[7]
                         net (fo=1, routed)           0.026     4.902    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__1_n_0
    SLICE_X60Y421        CARRY8 (Prop_CARRY8_SLICEM_CI_O[4])
                                                      0.086     4.988 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_carry__2/O[4]
                         net (fo=1, routed)           0.449     5.437    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v0[11]_88[28]
    SLICE_X60Y422        SRL16E                                       r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.699     5.278    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X60Y422        SRL16E                                       r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r/CLK
                         clock pessimism              0.332     5.610    
                         clock uncertainty           -0.035     5.574    
    SLICE_X60Y422        SRL16E (Setup_D5LUT_SLICEM_CLK_D)
                                                     -0.075     5.499    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v0_r2_reg[11][28]_srl2___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r2_reg_r
  -------------------------------------------------------------------
                         required time                          5.499    
                         arrival time                          -5.437    
  -------------------------------------------------------------------
                         slack                                  0.062    

Slack (MET) :             0.066ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[1].phase_v1_r1_reg[1][31]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.900ns  (logic 0.477ns (25.110%)  route 1.423ns (74.889%))
  Logic Levels:           5  (CARRY8=4 LUT2=1)
  Clock Path Skew:        -0.059ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.256ns = ( 5.291 - 2.035 ) 
    Source Clock Delay      (SCD):    3.628ns
    Clock Pessimism Removal (CPR):    0.313ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.917ns (routing 1.474ns, distribution 1.443ns)
  Clock Net Delay (Destination): 2.712ns (routing 1.336ns, distribution 1.376ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.917     3.628    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X77Y351        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y351        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     3.707 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[5]/Q
                         net (fo=16, routed)          1.282     4.989    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1[5]
    SLICE_X88Y388        LUT2 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.097     5.086 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry_i_3/O
                         net (fo=1, routed)           0.011     5.097    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry_i_3_n_0
    SLICE_X88Y388        CARRY8 (Prop_CARRY8_SLICEL_S[5]_CO[7])
                                                      0.155     5.252 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry/CO[7]
                         net (fo=1, routed)           0.026     5.278    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry_n_0
    SLICE_X88Y389        CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
                                                      0.015     5.293 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry__0/CO[7]
                         net (fo=1, routed)           0.052     5.345    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry__0_n_0
    SLICE_X88Y390        CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
                                                      0.015     5.360 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry__1/CO[7]
                         net (fo=1, routed)           0.026     5.386    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry__1_n_0
    SLICE_X88Y391        CARRY8 (Prop_CARRY8_SLICEL_CI_O[7])
                                                      0.116     5.502 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry__2/O[7]
                         net (fo=1, routed)           0.026     5.528    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_67[31]
    SLICE_X88Y391        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[1].phase_v1_r1_reg[1][31]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.712     5.291    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X88Y391        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[1].phase_v1_r1_reg[1][31]/C
                         clock pessimism              0.313     5.604    
                         clock uncertainty           -0.035     5.569    
    SLICE_X88Y391        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.025     5.594    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[1].phase_v1_r1_reg[1][31]
  -------------------------------------------------------------------
                         required time                          5.594    
                         arrival time                          -5.528    
  -------------------------------------------------------------------
                         slack                                  0.066    

Slack (MET) :             0.067ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[1].phase_v1_r1_reg[1][29]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.899ns  (logic 0.477ns (25.124%)  route 1.422ns (74.876%))
  Logic Levels:           5  (CARRY8=4 LUT2=1)
  Clock Path Skew:        -0.059ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.256ns = ( 5.291 - 2.035 ) 
    Source Clock Delay      (SCD):    3.628ns
    Clock Pessimism Removal (CPR):    0.313ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.917ns (routing 1.474ns, distribution 1.443ns)
  Clock Net Delay (Destination): 2.712ns (routing 1.336ns, distribution 1.376ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.917     3.628    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X77Y351        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y351        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     3.707 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1_reg[5]/Q
                         net (fo=16, routed)          1.282     4.989    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_0_r1[5]
    SLICE_X88Y388        LUT2 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.097     5.086 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry_i_3/O
                         net (fo=1, routed)           0.011     5.097    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry_i_3_n_0
    SLICE_X88Y388        CARRY8 (Prop_CARRY8_SLICEL_S[5]_CO[7])
                                                      0.155     5.252 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry/CO[7]
                         net (fo=1, routed)           0.026     5.278    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry_n_0
    SLICE_X88Y389        CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
                                                      0.015     5.293 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry__0/CO[7]
                         net (fo=1, routed)           0.052     5.345    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry__0_n_0
    SLICE_X88Y390        CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
                                                      0.015     5.360 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry__1/CO[7]
                         net (fo=1, routed)           0.026     5.386    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry__1_n_0
    SLICE_X88Y391        CARRY8 (Prop_CARRY8_SLICEL_CI_O[5])
                                                      0.116     5.502 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_carry__2/O[5]
                         net (fo=1, routed)           0.025     5.527    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/phase_v1[1]_67[29]
    SLICE_X88Y391        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[1].phase_v1_r1_reg[1][29]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.712     5.291    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X88Y391        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[1].phase_v1_r1_reg[1][29]/C
                         clock pessimism              0.313     5.604    
                         clock uncertainty           -0.035     5.569    
    SLICE_X88Y391        FDRE (Setup_FFF_SLICEL_C_D)
                                                      0.025     5.594    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[1].phase_v1_r1_reg[1][29]
  -------------------------------------------------------------------
                         required time                          5.594    
                         arrival time                          -5.527    
  -------------------------------------------------------------------
                         slack                                  0.067    

Slack (MET) :             0.074ns  (required time - arrival time)
  Source:                 d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].prodg_y_full_real_r_reg[7]/DSP_OUTPUT_INST/CLK
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/DATA_DAC0[117]
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.577ns  (logic 0.270ns (17.121%)  route 1.307ns (82.879%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        -0.262ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.361ns = ( 5.396 - 2.035 ) 
    Source Clock Delay      (SCD):    3.936ns
    Clock Pessimism Removal (CPR):    0.313ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.225ns (routing 1.474ns, distribution 1.751ns)
  Clock Net Delay (Destination): 2.817ns (routing 1.336ns, distribution 1.481ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       3.225     3.936    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].prodg_y_full_real_r_reg[7]/CLK
    DSP48E2_X21Y151      DSP_OUTPUT                                   r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].prodg_y_full_real_r_reg[7]/DSP_OUTPUT_INST/CLK
  -------------------------------------------------------------------    -------------------
    DSP48E2_X21Y151      DSP_OUTPUT (Prop_DSP_OUTPUT_DSP48E2_CLK_P[20])
                                                      0.220     4.156 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].prodg_y_full_real_r_reg[7]/DSP_OUTPUT_INST/P[20]
                         net (fo=1, routed)           0.638     4.794    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[127][5]
    SLICE_X111Y332       LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     4.844 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/stdy_latency_reg_i/m_axis_tdata[117]_INST_0/O
                         net (fo=1, routed)           0.669     5.513    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s10_axis_tdata[117]
    RFDAC_X0Y1           RFDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/DATA_DAC0[117]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.817     5.396    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s1_axis_aclk
    RFDAC_X0Y1           RFDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
                         clock pessimism              0.313     5.709    
                         clock uncertainty           -0.035     5.674    
    RFDAC_X0Y1           RFDAC (Setup_RFDAC_FABRIC_CLK_DATA_DAC0[117])
                                                     -0.087     5.587    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac
  -------------------------------------------------------------------
                         required time                          5.587    
                         arrival time                          -5.513    
  -------------------------------------------------------------------
                         slack                                  0.074    

Slack (MET) :             0.074ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/TRIG_FIFO[2].trig_fifo_inst/fifo_mem/RAM_reg/CLKARDCLK
                            (rising edge-triggered cell RAMB36E2 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[26]
                            (rising edge-triggered cell DSP_OUTPUT clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            2.035ns  (RFDAC2_CLK rise@2.035ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        1.709ns  (logic 0.904ns (52.896%)  route 0.805ns (47.104%))
  Logic Levels:           2  (DSP_ALU=1 DSP_C_DATA=1)
  Clock Path Skew:        -0.231ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.218ns = ( 5.253 - 2.035 ) 
    Source Clock Delay      (SCD):    3.845ns
    Clock Pessimism Removal (CPR):    0.396ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      3.134ns (routing 1.474ns, distribution 1.660ns)
  Clock Net Delay (Destination): 2.674ns (routing 1.336ns, distribution 1.338ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       3.134     3.845    d_1_i/qick_processor_0/t_clk_i
    RAMB36_X3Y43         RAMB36E2                                     r  d_1_i/qick_processor_0/TRIG_FIFO[2].trig_fifo_inst/fifo_mem/RAM_reg/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X3Y43         RAMB36E2 (Prop_RAMB36E2_RAMB36_CLKARDCLK_DOUTADOUT[26])
                                                      0.214     4.059 r  d_1_i/qick_processor_0/TRIG_FIFO[2].trig_fifo_inst/fifo_mem/RAM_reg/DOUTADOUT[26]
                         net (fo=1, routed)           0.805     4.864    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/C[26]
    DSP48E2_X7Y87        DSP_C_DATA (Prop_DSP_C_DATA_DSP48E2_C[26]_C_DATA[26])
                                                      0.105     4.969 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_C_DATA_INST/C_DATA[26]
                         net (fo=2, routed)           0.000     4.969    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_C_DATA.C_DATA<26>
    DSP48E2_X7Y87        DSP_ALU (Prop_DSP_ALU_DSP48E2_C_DATA[26]_ALU_OUT[26])
                                                      0.585     5.554 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU_INST/ALU_OUT[26]
                         net (fo=1, routed)           0.000     5.554    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_ALU.ALU_OUT<26>
    DSP48E2_X7Y87        DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/ALU_OUT[26]
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      2.035     2.035 r  
    RFDAC_X0Y2           RFDAC                        0.000     2.035 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     2.316 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     2.465    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     2.579 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.674     5.253    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/CLK
    DSP48E2_X7Y87        DSP_OUTPUT                                   r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST/CLK
                         clock pessimism              0.396     5.649    
                         clock uncertainty           -0.035     5.613    
    DSP48E2_X7Y87        DSP_OUTPUT (Setup_DSP_OUTPUT_DSP48E2_CLK_ALU_OUT[26])
                                                      0.015     5.628    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/dsp_bl.DSP48E_BL/DSP_OUTPUT_INST
  -------------------------------------------------------------------
                         required time                          5.628    
                         arrival time                          -5.554    
  -------------------------------------------------------------------
                         slack                                  0.074    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1062]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.131ns  (logic 0.060ns (45.801%)  route 0.071ns (54.198%))
  Logic Levels:           0  
  Clock Path Skew:        0.059ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.662ns
    Source Clock Delay      (SCD):    3.164ns
    Clock Pessimism Removal (CPR):    0.439ns
  Clock Net Delay (Source):      2.620ns (routing 1.336ns, distribution 1.284ns)
  Clock Net Delay (Destination): 2.951ns (routing 1.474ns, distribution 1.477ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.620     3.164    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X77Y370        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1062]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X77Y370        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.060     3.224 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1062]/Q
                         net (fo=1, routed)           0.071     3.295    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/s_axis_phase_tdata[22]
    SLICE_X77Y371        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.951     3.662    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/aclk
    SLICE_X77Y371        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[22]/C
                         clock pessimism             -0.439     3.224    
    SLICE_X77Y371        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     3.286    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[14].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[22]
  -------------------------------------------------------------------
                         required time                         -3.286    
                         arrival time                           3.295    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.170ns  (logic 0.059ns (34.706%)  route 0.111ns (65.294%))
  Logic Levels:           0  
  Clock Path Skew:        0.131ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.827ns
    Source Clock Delay      (SCD):    3.291ns
    Clock Pessimism Removal (CPR):    0.405ns
  Clock Net Delay (Source):      2.747ns (routing 1.336ns, distribution 1.411ns)
  Clock Net Delay (Destination): 3.116ns (routing 1.474ns, distribution 1.642ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.747     3.291    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/aclk
    SLICE_X92Y433        FDRE                                         r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y433        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     3.350 r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/Q
                         net (fo=1, routed)           0.111     3.461    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q[0]
    SLICE_X93Y433        SRL16E                                       r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       3.116     3.827    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/aclk
    SLICE_X93Y433        SRL16E                                       r  d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2/CLK
                         clock pessimism             -0.405     3.422    
    SLICE_X93Y433        SRL16E (Hold_A6LUT_SLICEM_CLK_D)
                                                      0.029     3.451    d_1_i/axis_signal_gen_v6_3/inst/signal_gen_top_i/signal_gen_i/GEN_dds[4].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2
  -------------------------------------------------------------------
                         required time                         -3.451    
                         arrival time                           3.461    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[5].phase_v1_r1_reg[5][12]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[404]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.275ns  (logic 0.058ns (21.091%)  route 0.217ns (78.909%))
  Logic Levels:           0  
  Clock Path Skew:        0.203ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.772ns
    Source Clock Delay      (SCD):    3.256ns
    Clock Pessimism Removal (CPR):    0.313ns
  Clock Net Delay (Source):      2.712ns (routing 1.336ns, distribution 1.376ns)
  Clock Net Delay (Destination): 3.061ns (routing 1.474ns, distribution 1.587ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.712     3.256    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X87Y344        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[5].phase_v1_r1_reg[5][12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y344        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.058     3.314 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[5].phase_v1_r1_reg[5][12]/Q
                         net (fo=1, routed)           0.217     3.531    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int[404]
    SLICE_X88Y363        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[404]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       3.061     3.772    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X88Y363        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[404]/C
                         clock pessimism             -0.313     3.459    
    SLICE_X88Y363        FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.062     3.521    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[404]
  -------------------------------------------------------------------
                         required time                         -3.521    
                         arrival time                           3.531    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_real_latency_reg_i/GEN_reg[7].shift_r_reg[7][2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/shift_r_reg[0][2]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.339ns  (logic 0.058ns (17.131%)  route 0.281ns (82.869%))
  Logic Levels:           0  
  Clock Path Skew:        0.301ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.934ns
    Source Clock Delay      (SCD):    3.329ns
    Clock Pessimism Removal (CPR):    0.305ns
  Clock Net Delay (Source):      2.785ns (routing 1.336ns, distribution 1.449ns)
  Clock Net Delay (Destination): 3.223ns (routing 1.474ns, distribution 1.749ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.785     3.329    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_real_latency_reg_i/aclk
    SLICE_X112Y293       FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_real_latency_reg_i/GEN_reg[7].shift_r_reg[7][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y293       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     3.387 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_real_latency_reg_i/GEN_reg[7].shift_r_reg[7][2]/Q
                         net (fo=2, routed)           0.281     3.667    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/B[2]
    SLICE_X110Y304       SRL16E                                       r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/shift_r_reg[0][2]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       3.223     3.934    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/aclk
    SLICE_X110Y304       SRL16E                                       r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/shift_r_reg[0][2]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r/CLK
                         clock pessimism             -0.305     3.629    
    SLICE_X110Y304       SRL16E (Hold_C6LUT_SLICEM_CLK_D)
                                                      0.028     3.657    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/GEN_dds[7].mem_mux_latency_reg_i/shift_r_reg[0][2]_srl3___inst_signal_gen_top_i_signal_gen_i_ctrl_i_en_reg_r3_reg_r
  -------------------------------------------------------------------
                         required time                         -3.657    
                         arrival time                           3.667    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[265]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[3].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.184ns  (logic 0.059ns (32.065%)  route 0.125ns (67.935%))
  Logic Levels:           0  
  Clock Path Skew:        0.112ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.721ns
    Source Clock Delay      (SCD):    3.220ns
    Clock Pessimism Removal (CPR):    0.390ns
  Clock Net Delay (Source):      2.676ns (routing 1.336ns, distribution 1.340ns)
  Clock Net Delay (Destination): 3.010ns (routing 1.474ns, distribution 1.536ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.676     3.220    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X92Y247        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[265]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y247        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     3.279 r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[265]/Q
                         net (fo=1, routed)           0.125     3.404    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[3].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/s_axis_phase_tdata[17]
    SLICE_X91Y248        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[3].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       3.010     3.721    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[3].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/aclk
    SLICE_X91Y248        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[3].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[17]/C
                         clock pessimism             -0.390     3.331    
    SLICE_X91Y248        FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.062     3.393    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/GEN_dds[3].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[17]
  -------------------------------------------------------------------
                         required time                         -3.393    
                         arrival time                           3.404    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[7].phase_v1_r1_reg[7][28]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[564]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.169ns  (logic 0.059ns (34.911%)  route 0.110ns (65.089%))
  Logic Levels:           0  
  Clock Path Skew:        0.097ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.679ns
    Source Clock Delay      (SCD):    3.182ns
    Clock Pessimism Removal (CPR):    0.400ns
  Clock Net Delay (Source):      2.638ns (routing 1.336ns, distribution 1.302ns)
  Clock Net Delay (Destination): 2.968ns (routing 1.474ns, distribution 1.494ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.638     3.182    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X57Y128        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[7].phase_v1_r1_reg[7][28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y128        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     3.241 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[7].phase_v1_r1_reg[7][28]/Q
                         net (fo=1, routed)           0.110     3.351    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int[564]
    SLICE_X55Y129        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[564]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.968     3.679    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X55Y129        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[564]/C
                         clock pessimism             -0.400     3.279    
    SLICE_X55Y129        FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.062     3.341    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[564]
  -------------------------------------------------------------------
                         required time                         -3.341    
                         arrival time                           3.351    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[627]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.127ns  (logic 0.058ns (45.669%)  route 0.069ns (54.331%))
  Logic Levels:           0  
  Clock Path Skew:        0.055ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.706ns
    Source Clock Delay      (SCD):    3.212ns
    Clock Pessimism Removal (CPR):    0.440ns
  Clock Net Delay (Source):      2.668ns (routing 1.336ns, distribution 1.332ns)
  Clock Net Delay (Destination): 2.995ns (routing 1.474ns, distribution 1.521ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.668     3.212    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X84Y250        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[627]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y250        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     3.270 r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[627]/Q
                         net (fo=1, routed)           0.069     3.339    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/s_axis_phase_tdata[19]
    SLICE_X84Y251        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.995     3.706    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/aclk
    SLICE_X84Y251        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[19]/C
                         clock pessimism             -0.440     3.267    
    SLICE_X84Y251        FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     3.329    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[19]
  -------------------------------------------------------------------
                         required time                         -3.329    
                         arrival time                           3.339    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[623]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.164ns  (logic 0.061ns (37.195%)  route 0.103ns (62.805%))
  Logic Levels:           0  
  Clock Path Skew:        0.093ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.636ns
    Source Clock Delay      (SCD):    3.153ns
    Clock Pessimism Removal (CPR):    0.389ns
  Clock Net Delay (Source):      2.609ns (routing 1.336ns, distribution 1.273ns)
  Clock Net Delay (Destination): 2.925ns (routing 1.474ns, distribution 1.451ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.609     3.153    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X72Y370        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[623]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X72Y370        FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.061     3.214 r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[623]/Q
                         net (fo=1, routed)           0.103     3.317    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/s_axis_phase_tdata[15]
    SLICE_X70Y371        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.925     3.636    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/aclk
    SLICE_X70Y371        FDRE                                         r  d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[15]/C
                         clock pessimism             -0.389     3.247    
    SLICE_X70Y371        FDRE (Hold_CFF_SLICEM_C_D)
                                                      0.060     3.307    d_1_i/axis_signal_gen_v6_2/inst/signal_gen_top_i/signal_gen_i/GEN_dds[8].dds_i/U0/i_synth/i_dds/I_PHASEGEN.i_conventional_accum.i_accum/i_common.i_stream_poff_gen.poff_channel_in/opt_has_pipe.first_q_reg[15]
  -------------------------------------------------------------------
                         required time                         -3.307    
                         arrival time                           3.317    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v1_r1_reg[11][14]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[838]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.291ns  (logic 0.058ns (19.931%)  route 0.233ns (80.069%))
  Logic Levels:           0  
  Clock Path Skew:        0.220ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.777ns
    Source Clock Delay      (SCD):    3.244ns
    Clock Pessimism Removal (CPR):    0.313ns
  Clock Net Delay (Source):      2.700ns (routing 1.336ns, distribution 1.364ns)
  Clock Net Delay (Destination): 3.066ns (routing 1.474ns, distribution 1.592ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.700     3.244    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X86Y343        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v1_r1_reg[11][14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y343        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.058     3.302 r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/ctrl_i/GEN_phase[11].phase_v1_r1_reg[11][14]/Q
                         net (fo=1, routed)           0.233     3.535    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int[838]
    SLICE_X88Y361        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[838]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       3.066     3.777    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X88Y361        FDRE                                         r  d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[838]/C
                         clock pessimism             -0.313     3.464    
    SLICE_X88Y361        FDRE (Hold_GFF_SLICEL_C_D)
                                                      0.060     3.524    d_1_i/axis_signal_gen_v6_1/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[838]
  -------------------------------------------------------------------
                         required time                         -3.524    
                         arrival time                           3.535    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2/D
                            (rising edge-triggered cell SRL16E clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             RFDAC2_CLK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (RFDAC2_CLK rise@0.000ns - RFDAC2_CLK rise@0.000ns)
  Data Path Delay:        0.167ns  (logic 0.058ns (34.731%)  route 0.109ns (65.269%))
  Logic Levels:           0  
  Clock Path Skew:        0.127ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    3.752ns
    Source Clock Delay      (SCD):    3.220ns
    Clock Pessimism Removal (CPR):    0.404ns
  Clock Net Delay (Source):      2.676ns (routing 1.336ns, distribution 1.340ns)
  Clock Net Delay (Destination): 3.041ns (routing 1.474ns, distribution 1.567ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.676     3.220    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/aclk
    SLICE_X55Y440        FDRE                                         r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y440        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     3.278 r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q_reg[0]/Q
                         net (fo=1, routed)           0.109     3.387    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.first_q[0]
    SLICE_X56Y440        SRL16E                                       r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       3.041     3.752    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/aclk
    SLICE_X56Y440        SRL16E                                       r  d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2/CLK
                         clock pessimism             -0.404     3.348    
    SLICE_X56Y440        SRL16E (Hold_A6LUT_SLICEM_CLK_D)
                                                      0.029     3.377    d_1_i/axis_signal_gen_v6_4/inst/signal_gen_top_i/signal_gen_i/GEN_dds[6].dds_i/U0/i_synth/i_dds/I_SINCOS.i_std_rom.i_rom/i_rtl.i_quarter_table.i_addr_reg_c/opt_has_pipe.i_pipe[3].pipe_reg[3][0]_srl2
  -------------------------------------------------------------------
                         required time                         -3.377    
                         arrival time                           3.387    
  -------------------------------------------------------------------
                         slack                                  0.011    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         RFDAC2_CLK
Waveform(ns):       { 0.000 1.018 }
Period(ns):         2.035
Sources:            { d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     RFDAC/FABRIC_CLK    n/a            1.600         2.035       0.435      RFDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Min Period        n/a     RFDAC/FABRIC_CLK    n/a            1.600         2.035       0.435      RFDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Min Period        n/a     RFDAC/CLK_DAC       n/a            1.600         2.035       0.435      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
Min Period        n/a     RFDAC/FABRIC_CLK    n/a            1.600         2.035       0.435      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/FABRIC_CLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.355         2.035       0.680      RAMB18_X9Y49  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.355         2.035       0.680      RAMB18_X9Y48  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.355         2.035       0.680      RAMB18_X6Y69  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[10].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.355         2.035       0.680      RAMB18_X7Y73  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[10].mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.355         2.035       0.680      RAMB18_X7Y70  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[11].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB18E2/CLKBWRCLK  n/a            1.355         2.035       0.680      RAMB18_X7Y74  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[11].mem_real_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Slow    RFDAC/FABRIC_CLK    n/a            0.640         1.018       0.378      RFDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Low Pulse Width   Fast    RFDAC/FABRIC_CLK    n/a            0.640         1.017       0.377      RFDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
Low Pulse Width   Slow    RFDAC/FABRIC_CLK    n/a            0.640         1.018       0.378      RFDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Low Pulse Width   Fast    RFDAC/FABRIC_CLK    n/a            0.640         1.018       0.378      RFDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
Low Pulse Width   Slow    RFDAC/CLK_DAC       n/a            0.640         1.018       0.378      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
Low Pulse Width   Fast    RFDAC/CLK_DAC       n/a            0.640         1.017       0.377      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
Low Pulse Width   Slow    RFDAC/FABRIC_CLK    n/a            0.640         1.017       0.377      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/FABRIC_CLK
Low Pulse Width   Fast    RFDAC/FABRIC_CLK    n/a            0.640         1.018       0.378      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/FABRIC_CLK
Low Pulse Width   Slow    RAMB18E2/CLKBWRCLK  n/a            0.542         1.017       0.475      RAMB18_X9Y49  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
Low Pulse Width   Fast    RAMB18E2/CLKBWRCLK  n/a            0.542         1.018       0.476      RAMB18_X9Y49  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Slow    RFDAC/FABRIC_CLK    n/a            0.640         1.017       0.377      RFDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
High Pulse Width  Fast    RFDAC/FABRIC_CLK    n/a            0.640         1.018       0.378      RFDAC_X0Y0    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/FABRIC_CLK
High Pulse Width  Slow    RFDAC/FABRIC_CLK    n/a            0.640         1.017       0.377      RFDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
High Pulse Width  Fast    RFDAC/FABRIC_CLK    n/a            0.640         1.018       0.378      RFDAC_X0Y1    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/FABRIC_CLK
High Pulse Width  Slow    RFDAC/CLK_DAC       n/a            0.640         1.018       0.378      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
High Pulse Width  Fast    RFDAC/CLK_DAC       n/a            0.640         1.018       0.378      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
High Pulse Width  Slow    RFDAC/FABRIC_CLK    n/a            0.640         1.018       0.378      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/FABRIC_CLK
High Pulse Width  Fast    RFDAC/FABRIC_CLK    n/a            0.640         1.018       0.378      RFDAC_X0Y2    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/FABRIC_CLK
High Pulse Width  Slow    RAMB18E2/CLKBWRCLK  n/a            0.542         1.018       0.476      RAMB18_X9Y49  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK
High Pulse Width  Fast    RAMB18E2/CLKBWRCLK  n/a            0.542         1.018       0.476      RAMB18_X9Y49  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/GEN_mem[0].mem_imag_i/RAM_reg_bram_0/CLKBWRCLK



---------------------------------------------------------------------------------------------------
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        1.952ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.009ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.952ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/dac1_sample_rate_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.979ns  (logic 0.618ns (7.745%)  route 7.361ns (92.255%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.285ns = ( 12.285 - 10.000 ) 
    Source Clock Delay      (SCD):    2.361ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.135ns (routing 0.670ns, distribution 1.465ns)
  Clock Net Delay (Destination): 2.103ns (routing 0.606ns, distribution 1.497ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.135     2.361    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[0])
                                                      0.579     2.940 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[0]
                         net (fo=22, routed)          3.898     6.838    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[0]
    SLICE_X69Y162        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     6.877 r  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[0]_INST_0/O
                         net (fo=157, routed)         3.463    10.340    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[0]
    SLICE_X99Y217        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac1_sample_rate_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.103    12.285    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X99Y217        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac1_sample_rate_reg[0]/C
                         clock pessimism              0.112    12.397    
                         clock uncertainty           -0.130    12.268    
    SLICE_X99Y217        FDRE (Setup_DFF_SLICEM_C_D)
                                                      0.025    12.293    d_1_i/usp_rf_data_converter_0/inst/dac1_sample_rate_reg[0]
  -------------------------------------------------------------------
                         required time                         12.293    
                         arrival time                         -10.340    
  -------------------------------------------------------------------
                         slack                                  1.952    

Slack (MET) :             2.070ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/dac1_ref_clk_freq_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.861ns  (logic 0.618ns (7.861%)  route 7.243ns (92.139%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.036ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.285ns = ( 12.285 - 10.000 ) 
    Source Clock Delay      (SCD):    2.361ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.135ns (routing 0.670ns, distribution 1.465ns)
  Clock Net Delay (Destination): 2.103ns (routing 0.606ns, distribution 1.497ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.135     2.361    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[0])
                                                      0.579     2.940 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[0]
                         net (fo=22, routed)          3.898     6.838    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[0]
    SLICE_X69Y162        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     6.877 r  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[0]_INST_0/O
                         net (fo=157, routed)         3.345    10.222    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[0]
    SLICE_X99Y217        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac1_ref_clk_freq_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.103    12.285    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X99Y217        FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac1_ref_clk_freq_reg[0]/C
                         clock pessimism              0.112    12.397    
                         clock uncertainty           -0.130    12.268    
    SLICE_X99Y217        FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    12.293    d_1_i/usp_rf_data_converter_0/inst/dac1_ref_clk_freq_reg[0]
  -------------------------------------------------------------------
                         required time                         12.293    
                         arrival time                         -10.222    
  -------------------------------------------------------------------
                         slack                                  2.070    

Slack (MET) :             2.229ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/dac3_end_stage_reg[0]/D
                            (rising edge-triggered cell FDSE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.700ns  (logic 0.618ns (8.026%)  route 7.082ns (91.974%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.034ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.283ns = ( 12.283 - 10.000 ) 
    Source Clock Delay      (SCD):    2.361ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.135ns (routing 0.670ns, distribution 1.465ns)
  Clock Net Delay (Destination): 2.101ns (routing 0.606ns, distribution 1.495ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.135     2.361    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[0])
                                                      0.579     2.940 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[0]
                         net (fo=22, routed)          3.898     6.838    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[0]
    SLICE_X69Y162        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     6.877 r  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[0]_INST_0/O
                         net (fo=157, routed)         3.184    10.061    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[0]
    SLICE_X105Y221       FDSE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac3_end_stage_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.101    12.283    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y221       FDSE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac3_end_stage_reg[0]/C
                         clock pessimism              0.112    12.395    
                         clock uncertainty           -0.130    12.265    
    SLICE_X105Y221       FDSE (Setup_AFF_SLICEL_C_D)
                                                      0.025    12.290    d_1_i/usp_rf_data_converter_0/inst/dac3_end_stage_reg[0]
  -------------------------------------------------------------------
                         required time                         12.290    
                         arrival time                         -10.061    
  -------------------------------------------------------------------
                         slack                                  2.229    

Slack (MET) :             2.247ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_wren_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.652ns  (logic 0.939ns (12.271%)  route 6.713ns (87.729%))
  Logic Levels:           5  (LUT2=1 LUT5=1 LUT6=3)
  Clock Path Skew:        0.004ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.163ns = ( 12.163 - 10.000 ) 
    Source Clock Delay      (SCD):    2.361ns
    Clock Pessimism Removal (CPR):    0.202ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.135ns (routing 0.670ns, distribution 1.465ns)
  Clock Net Delay (Destination): 1.981ns (routing 0.606ns, distribution 1.375ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.135     2.361    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[54])
                                                      0.537     2.898 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[54]
                         net (fo=18, routed)          3.114     6.012    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[54]
    SLICE_X64Y150        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.124     6.136 r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[22]_INST_0/O
                         net (fo=78, routed)          3.064     9.201    d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/s_axi_lite_wdata[22]
    SLICE_X68Y14         LUT5 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.036     9.237 r  d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/dmacr_i[23]_i_2/O
                         net (fo=3, routed)           0.260     9.496    d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/s_axi_lite_wdata_23_sn_1
    SLICE_X70Y11         LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.090     9.586 r  d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_wren_i_4/O
                         net (fo=1, routed)           0.047     9.633    d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_wren_i_4_n_0
    SLICE_X70Y11         LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.101     9.734 r  d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_wren_i_2/O
                         net (fo=2, routed)           0.162     9.896    d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/buffer_length_wren1
    SLICE_X70Y9          LUT2 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.051     9.947 r  d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_REG_FOR_SMPL.buffer_length_wren_i_1__0/O
                         net (fo=1, routed)           0.066    10.013    d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/buffer_length_wren0
    SLICE_X70Y9          FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_wren_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.981    12.163    d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/s_axi_lite_aclk
    SLICE_X70Y9          FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_wren_reg/C
                         clock pessimism              0.202    12.365    
                         clock uncertainty           -0.130    12.236    
    SLICE_X70Y9          FDRE (Setup_CFF_SLICEM_C_D)
                                                      0.025    12.261    d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_wren_reg
  -------------------------------------------------------------------
                         required time                         12.261    
                         arrival time                         -10.013    
  -------------------------------------------------------------------
                         slack                                  2.247    

Slack (MET) :             2.250ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/dac0_reset_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.683ns  (logic 0.706ns (9.190%)  route 6.977ns (90.810%))
  Logic Levels:           2  (LUT6=2)
  Clock Path Skew:        0.038ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.287ns = ( 12.287 - 10.000 ) 
    Source Clock Delay      (SCD):    2.361ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.135ns (routing 0.670ns, distribution 1.465ns)
  Clock Net Delay (Destination): 2.105ns (routing 0.606ns, distribution 1.499ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.135     2.361    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[0])
                                                      0.579     2.940 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[0]
                         net (fo=22, routed)          3.898     6.838    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[0]
    SLICE_X69Y162        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     6.877 r  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[0]_INST_0/O
                         net (fo=157, routed)         3.013     9.890    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/s_axi_wdata[0]
    SLICE_X104Y208       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.088     9.978 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/dac0_reset_i_1/O
                         net (fo=1, routed)           0.066    10.044    d_1_i/usp_rf_data_converter_0/inst/dac0_reset
    SLICE_X104Y208       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac0_reset_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.105    12.287    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y208       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac0_reset_reg/C
                         clock pessimism              0.112    12.399    
                         clock uncertainty           -0.130    12.269    
    SLICE_X104Y208       FDRE (Setup_CFF_SLICEM_C_D)
                                                      0.025    12.294    d_1_i/usp_rf_data_converter_0/inst/dac0_reset_reg
  -------------------------------------------------------------------
                         required time                         12.294    
                         arrival time                         -10.044    
  -------------------------------------------------------------------
                         slack                                  2.250    

Slack (MET) :             2.264ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/dac1_cmn_irq_en_reg/D
                            (rising edge-triggered cell FDSE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.668ns  (logic 0.721ns (9.403%)  route 6.947ns (90.597%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.286ns = ( 12.286 - 10.000 ) 
    Source Clock Delay      (SCD):    2.361ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.135ns (routing 0.670ns, distribution 1.465ns)
  Clock Net Delay (Destination): 2.104ns (routing 0.606ns, distribution 1.498ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.135     2.361    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[4])
                                                      0.596     2.957 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[4]
                         net (fo=20, routed)          3.632     6.589    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[4]
    SLICE_X69Y165        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.125     6.714 r  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[4]_INST_0/O
                         net (fo=69, routed)          3.314    10.029    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[4]
    SLICE_X103Y222       FDSE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac1_cmn_irq_en_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.104    12.286    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y222       FDSE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac1_cmn_irq_en_reg/C
                         clock pessimism              0.112    12.398    
                         clock uncertainty           -0.130    12.268    
    SLICE_X103Y222       FDSE (Setup_HFF_SLICEM_C_D)
                                                      0.025    12.293    d_1_i/usp_rf_data_converter_0/inst/dac1_cmn_irq_en_reg
  -------------------------------------------------------------------
                         required time                         12.293    
                         arrival time                         -10.029    
  -------------------------------------------------------------------
                         slack                                  2.264    

Slack (MET) :             2.264ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc30_irq_en_reg/D
                            (rising edge-triggered cell FDSE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.663ns  (logic 0.618ns (8.065%)  route 7.045ns (91.935%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.032ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.281ns = ( 12.281 - 10.000 ) 
    Source Clock Delay      (SCD):    2.361ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.135ns (routing 0.670ns, distribution 1.465ns)
  Clock Net Delay (Destination): 2.099ns (routing 0.606ns, distribution 1.493ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.135     2.361    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[0])
                                                      0.579     2.940 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[0]
                         net (fo=22, routed)          3.898     6.838    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[0]
    SLICE_X69Y162        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     6.877 r  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[0]_INST_0/O
                         net (fo=157, routed)         3.147    10.024    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[0]
    SLICE_X103Y205       FDSE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc30_irq_en_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.099    12.281    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y205       FDSE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc30_irq_en_reg/C
                         clock pessimism              0.112    12.393    
                         clock uncertainty           -0.130    12.263    
    SLICE_X103Y205       FDSE (Setup_HFF_SLICEM_C_D)
                                                      0.025    12.288    d_1_i/usp_rf_data_converter_0/inst/adc30_irq_en_reg
  -------------------------------------------------------------------
                         required time                         12.288    
                         arrival time                         -10.024    
  -------------------------------------------------------------------
                         slack                                  2.264    

Slack (MET) :             2.269ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_wren_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.630ns  (logic 0.956ns (12.529%)  route 6.674ns (87.471%))
  Logic Levels:           5  (LUT2=1 LUT5=1 LUT6=3)
  Clock Path Skew:        0.004ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.163ns = ( 12.163 - 10.000 ) 
    Source Clock Delay      (SCD):    2.361ns
    Clock Pessimism Removal (CPR):    0.202ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.135ns (routing 0.670ns, distribution 1.465ns)
  Clock Net Delay (Destination): 1.981ns (routing 0.606ns, distribution 1.375ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.135     2.361    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[54])
                                                      0.537     2.898 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[54]
                         net (fo=18, routed)          3.114     6.012    d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[54]
    SLICE_X64Y150        LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.124     6.136 r  d_1_i/ps8_0_axi_periph/i00_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[22]_INST_0/O
                         net (fo=78, routed)          3.064     9.201    d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/s_axi_lite_wdata[22]
    SLICE_X68Y14         LUT5 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.036     9.237 r  d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/dmacr_i[23]_i_2/O
                         net (fo=3, routed)           0.260     9.496    d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/s_axi_lite_wdata_23_sn_1
    SLICE_X70Y11         LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.090     9.586 r  d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_wren_i_4/O
                         net (fo=1, routed)           0.047     9.633    d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_wren_i_4_n_0
    SLICE_X70Y11         LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.101     9.734 r  d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_MM2S_REGISTERS.I_MM2S_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_wren_i_2/O
                         net (fo=2, routed)           0.162     9.896    d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/buffer_length_wren1
    SLICE_X70Y9          LUT2 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.068     9.964 r  d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_REG_FOR_SMPL.buffer_length_wren_i_1/O
                         net (fo=1, routed)           0.027     9.991    d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/buffer_length_wren0
    SLICE_X70Y9          FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_wren_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.981    12.163    d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/s_axi_lite_aclk
    SLICE_X70Y9          FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_wren_reg/C
                         clock pessimism              0.202    12.365    
                         clock uncertainty           -0.130    12.236    
    SLICE_X70Y9          FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    12.261    d_1_i/axi_dma_tproc/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/GEN_REG_FOR_SMPL.buffer_length_wren_reg
  -------------------------------------------------------------------
                         required time                         12.261    
                         arrival time                          -9.991    
  -------------------------------------------------------------------
                         slack                                  2.269    

Slack (MET) :             2.292ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/dac1_sim_level_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.640ns  (logic 0.618ns (8.089%)  route 7.022ns (91.911%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.037ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.286ns = ( 12.286 - 10.000 ) 
    Source Clock Delay      (SCD):    2.361ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.135ns (routing 0.670ns, distribution 1.465ns)
  Clock Net Delay (Destination): 2.104ns (routing 0.606ns, distribution 1.498ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.135     2.361    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[0])
                                                      0.579     2.940 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[0]
                         net (fo=22, routed)          3.898     6.838    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[0]
    SLICE_X69Y162        LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     6.877 r  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[0]_INST_0/O
                         net (fo=157, routed)         3.124    10.001    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[0]
    SLICE_X105Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac1_sim_level_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.104    12.286    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/dac1_sim_level_reg[0]/C
                         clock pessimism              0.112    12.398    
                         clock uncertainty           -0.130    12.268    
    SLICE_X105Y222       FDRE (Setup_EFF_SLICEL_C_D)
                                                      0.025    12.293    d_1_i/usp_rf_data_converter_0/inst/dac1_sim_level_reg[0]
  -------------------------------------------------------------------
                         required time                         12.293    
                         arrival time                         -10.001    
  -------------------------------------------------------------------
                         slack                                  2.292    

Slack (MET) :             2.300ns  (required time - arrival time)
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
                            (rising edge-triggered cell PS8 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/adc02_tdd_obs_reg_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        7.664ns  (logic 0.681ns (8.885%)  route 6.983ns (91.115%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.069ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.318ns = ( 12.318 - 10.000 ) 
    Source Clock Delay      (SCD):    2.361ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.135ns (routing 0.670ns, distribution 1.465ns)
  Clock Net Delay (Destination): 2.136ns (routing 0.606ns, distribution 1.530ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.135     2.361    d_1_i/zynq_ultra_ps_e_0/inst/maxihpm0_fpd_aclk
    PS8_X0Y0             PS8                                          r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0ACLK
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8 (Prop_PS8_MAXIGP0ACLK_MAXIGP0WDATA[3])
                                                      0.582     2.943 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP0WDATA[3]
                         net (fo=21, routed)          3.713     6.656    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/s_axi_wdata[3]
    SLICE_X65Y163        LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.099     6.755 r  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/m_axi_wdata[3]_INST_0/O
                         net (fo=93, routed)          3.271    10.025    d_1_i/usp_rf_data_converter_0/inst/s_axi_wdata[3]
    SLICE_X107Y184       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc02_tdd_obs_reg_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.136    12.318    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X107Y184       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/adc02_tdd_obs_reg_reg/C
                         clock pessimism              0.112    12.430    
                         clock uncertainty           -0.130    12.300    
    SLICE_X107Y184       FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    12.325    d_1_i/usp_rf_data_converter_0/inst/adc02_tdd_obs_reg_reg
  -------------------------------------------------------------------
                         required time                         12.325    
                         arrival time                         -10.025    
  -------------------------------------------------------------------
                         slack                                  2.300    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.009ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][108]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMF/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.238ns  (logic 0.059ns (24.831%)  route 0.179ns (75.169%))
  Logic Levels:           0  
  Clock Path Skew:        0.150ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.386ns
    Source Clock Delay      (SCD):    2.039ns
    Clock Pessimism Removal (CPR):    0.197ns
  Clock Net Delay (Source):      1.857ns (routing 0.606ns, distribution 1.251ns)
  Clock Net Delay (Destination): 2.160ns (routing 0.670ns, distribution 1.490ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.857     2.039    d_1_i/axi_smc/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
    SLICE_X38Y19         FDRE                                         r  d_1_i/axi_smc/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][108]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y19         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     2.098 r  d_1_i/axi_smc/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][108]/Q
                         net (fo=2, routed)           0.179     2.276    d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/DIF0
    SLICE_X39Y24         RAMD32                                       r  d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMF/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.160     2.386    d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/WCLK
    SLICE_X39Y24         RAMD32                                       r  d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMF/CLK
                         clock pessimism             -0.197     2.189    
    SLICE_X39Y24         RAMD32 (Hold_F5LUT_SLICEM_CLK_I)
                                                      0.078     2.267    d_1_i/axi_smc/inst/s02_nodes/s02_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMF
  -------------------------------------------------------------------
                         required time                         -2.267    
                         arrival time                           2.276    
  -------------------------------------------------------------------
                         slack                                  0.009    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_rd.fifo_empty_r_reg/C
                            (rising edge-triggered cell FDSE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_rd.empty_r_reg/D
                            (rising edge-triggered cell FDSE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.201ns  (logic 0.081ns (40.380%)  route 0.120ns (59.620%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.131ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.437ns
    Source Clock Delay      (SCD):    2.160ns
    Clock Pessimism Removal (CPR):    0.146ns
  Clock Net Delay (Source):      1.978ns (routing 0.606ns, distribution 1.372ns)
  Clock Net Delay (Destination): 2.211ns (routing 0.670ns, distribution 1.541ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.978     2.160    d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/s_sc_aclk
    SLICE_X73Y59         FDSE                                         r  d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_rd.fifo_empty_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y59         FDSE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     2.218 r  d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_rd.fifo_empty_r_reg/Q
                         net (fo=4, routed)           0.096     2.313    d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_rd.fifo_empty_r
    SLICE_X73Y61         LUT4 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.023     2.336 r  d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_rd.empty_r_i_1__0/O
                         net (fo=1, routed)           0.024     2.360    d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_rd.empty_r_i_1__0_n_0
    SLICE_X73Y61         FDSE                                         r  d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_rd.empty_r_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.211     2.437    d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/s_sc_aclk
    SLICE_X73Y61         FDSE                                         r  d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_rd.empty_r_reg/C
                         clock pessimism             -0.146     2.291    
    SLICE_X73Y61         FDSE (Hold_HFF_SLICEL_C_D)
                                                      0.060     2.351    d_1_i/axi_smc/inst/s04_nodes/s04_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_rd.empty_r_reg
  -------------------------------------------------------------------
                         required time                         -2.351    
                         arrival time                           2.360    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.valid_payld_o_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.payld_o_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.217ns  (logic 0.093ns (42.871%)  route 0.124ns (57.129%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.147ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.440ns
    Source Clock Delay      (SCD):    2.147ns
    Clock Pessimism Removal (CPR):    0.146ns
  Clock Net Delay (Source):      1.965ns (routing 0.606ns, distribution 1.359ns)
  Clock Net Delay (Destination): 2.214ns (routing 0.670ns, distribution 1.544ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.965     2.147    d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/s_sc_aclk
    SLICE_X67Y58         FDRE                                         r  d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.valid_payld_o_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y58         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.058     2.205 r  d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.valid_payld_o_reg/Q
                         net (fo=4, routed)           0.095     2.300    d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.valid_payld_o_reg_n_0
    SLICE_X67Y61         LUT4 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.035     2.335 r  d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.payld_o[0]_i_1/O
                         net (fo=1, routed)           0.029     2.364    d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.payld_o[0]_i_1_n_0
    SLICE_X67Y61         FDRE                                         r  d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.payld_o_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.214     2.440    d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/s_sc_aclk
    SLICE_X67Y61         FDRE                                         r  d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.payld_o_reg[0]/C
                         clock pessimism             -0.146     2.294    
    SLICE_X67Y61         FDRE (Hold_BFF_SLICEM_C_D)
                                                      0.060     2.354    d_1_i/axi_smc/inst/s05_nodes/s05_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.payld_o_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.354    
                         arrival time                           2.364    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/m_vector_i_reg[2059]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAME/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.224ns  (logic 0.060ns (26.786%)  route 0.164ns (73.214%))
  Logic Levels:           0  
  Clock Path Skew:        0.137ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.469ns
    Source Clock Delay      (SCD):    2.130ns
    Clock Pessimism Removal (CPR):    0.202ns
  Clock Net Delay (Source):      1.948ns (routing 0.606ns, distribution 1.342ns)
  Clock Net Delay (Destination): 2.243ns (routing 0.670ns, distribution 1.573ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.948     2.130    d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/aclk
    SLICE_X73Y87         FDRE                                         r  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/m_vector_i_reg[2059]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X73Y87         FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     2.190 r  d_1_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/m_vector_i_reg[2059]/Q
                         net (fo=1, routed)           0.164     2.354    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/DIE0
    SLICE_X70Y89         RAMD32                                       r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAME/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.243     2.469    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/WCLK
    SLICE_X70Y89         RAMD32                                       r  d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAME/CLK
                         clock pessimism             -0.202     2.267    
    SLICE_X70Y89         RAMD32 (Hold_E5LUT_SLICEM_CLK_I)
                                                      0.077     2.344    d_1_i/axi_smc/inst/s01_nodes/s01_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAME
  -------------------------------------------------------------------
                         required time                         -2.344    
                         arrival time                           2.354    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m17_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/m_payload_i_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m17_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[0].S_AXI_RDATA_II_reg[26]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.231ns  (logic 0.060ns (26.009%)  route 0.171ns (73.991%))
  Logic Levels:           0  
  Clock Path Skew:        0.159ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.356ns
    Source Clock Delay      (SCD):    2.051ns
    Clock Pessimism Removal (CPR):    0.146ns
  Clock Net Delay (Source):      1.869ns (routing 0.606ns, distribution 1.263ns)
  Clock Net Delay (Destination): 2.130ns (routing 0.670ns, distribution 1.460ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.869     2.051    d_1_i/ps8_0_axi_periph/m17_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/aclk
    SLICE_X56Y60         FDRE                                         r  d_1_i/ps8_0_axi_periph/m17_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/m_payload_i_reg[26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y60         FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.060     2.111 r  d_1_i/ps8_0_axi_periph/m17_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/m_payload_i_reg[26]/Q
                         net (fo=8, routed)           0.171     2.282    d_1_i/ps8_0_axi_periph/m17_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/m_axi_rdata[26]
    SLICE_X57Y56         FDRE                                         r  d_1_i/ps8_0_axi_periph/m17_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[0].S_AXI_RDATA_II_reg[26]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.130     2.356    d_1_i/ps8_0_axi_periph/m17_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/CLK
    SLICE_X57Y56         FDRE                                         r  d_1_i/ps8_0_axi_periph/m17_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[0].S_AXI_RDATA_II_reg[26]/C
                         clock pessimism             -0.146     2.210    
    SLICE_X57Y56         FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.062     2.272    d_1_i/ps8_0_axi_periph/m17_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_READ.read_data_inst/WORD_LANE[0].S_AXI_RDATA_II_reg[26]
  -------------------------------------------------------------------
                         required time                         -2.272    
                         arrival time                           2.282    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][27][userdata][2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMG/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.252ns  (logic 0.060ns (23.810%)  route 0.192ns (76.190%))
  Logic Levels:           0  
  Clock Path Skew:        0.164ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.486ns
    Source Clock Delay      (SCD):    2.120ns
    Clock Pessimism Removal (CPR):    0.202ns
  Clock Net Delay (Source):      1.938ns (routing 0.606ns, distribution 1.332ns)
  Clock Net Delay (Destination): 2.260ns (routing 0.670ns, distribution 1.590ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.938     2.120    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/s_sc_aclk
    SLICE_X68Y80         FDRE                                         r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][27][userdata][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y80         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.060     2.180 r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][27][userdata][2]/Q
                         net (fo=1, routed)           0.192     2.372    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/DIG0
    SLICE_X72Y79         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMG/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.260     2.486    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/WCLK
    SLICE_X72Y79         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMG/CLK
                         clock pessimism             -0.202     2.284    
    SLICE_X72Y79         RAMD32 (Hold_G5LUT_SLICEM_CLK_I)
                                                      0.078     2.362    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[1].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMG
  -------------------------------------------------------------------
                         required time                         -2.362    
                         arrival time                           2.372    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][4][userdata][3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.236ns  (logic 0.058ns (24.576%)  route 0.178ns (75.424%))
  Logic Levels:           0  
  Clock Path Skew:        0.151ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.477ns
    Source Clock Delay      (SCD):    2.124ns
    Clock Pessimism Removal (CPR):    0.202ns
  Clock Net Delay (Source):      1.942ns (routing 0.606ns, distribution 1.336ns)
  Clock Net Delay (Destination): 2.251ns (routing 0.670ns, distribution 1.581ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.942     2.124    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/s_sc_aclk
    SLICE_X71Y85         FDRE                                         r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][4][userdata][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X71Y85         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     2.182 r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][4][userdata][3]/Q
                         net (fo=1, routed)           0.178     2.360    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/DIA0
    SLICE_X72Y86         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.251     2.477    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/WCLK
    SLICE_X72Y86         RAMD32                                       r  d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMA/CLK
                         clock pessimism             -0.202     2.275    
    SLICE_X72Y86         RAMD32 (Hold_A5LUT_SLICEM_CLK_I)
                                                      0.075     2.350    d_1_i/axi_smc/inst/s03_nodes/s03_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMA
  -------------------------------------------------------------------
                         required time                         -2.350    
                         arrival time                           2.360    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc/inst/switchboards/ar_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][112]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.234ns  (logic 0.061ns (26.068%)  route 0.173ns (73.932%))
  Logic Levels:           0  
  Clock Path Skew:        0.149ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.408ns
    Source Clock Delay      (SCD):    2.062ns
    Clock Pessimism Removal (CPR):    0.197ns
  Clock Net Delay (Source):      1.880ns (routing 0.606ns, distribution 1.274ns)
  Clock Net Delay (Destination): 2.182ns (routing 0.670ns, distribution 1.512ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.880     2.062    d_1_i/axi_smc/inst/switchboards/ar_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
    SLICE_X58Y7          FDRE                                         r  d_1_i/axi_smc/inst/switchboards/ar_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][112]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X58Y7          FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     2.123 r  d_1_i/axi_smc/inst/switchboards/ar_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][112]/Q
                         net (fo=1, routed)           0.173     2.296    d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/DIA0
    SLICE_X54Y5          RAMD32                                       r  d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.182     2.408    d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/WCLK
    SLICE_X54Y5          RAMD32                                       r  d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMA/CLK
                         clock pessimism             -0.197     2.211    
    SLICE_X54Y5          RAMD32 (Hold_A5LUT_SLICEM_CLK_I)
                                                      0.075     2.286    d_1_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMA
  -------------------------------------------------------------------
                         required time                         -2.286    
                         arrival time                           2.296    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_cc.fifo_wr_rst_cc_reg[2]/C
                            (rising edge-triggered cell FDSE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/RSTREGARSTREG
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.212ns  (logic 0.057ns (26.950%)  route 0.155ns (73.050%))
  Logic Levels:           0  
  Clock Path Skew:        0.213ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.414ns
    Source Clock Delay      (SCD):    2.004ns
    Clock Pessimism Removal (CPR):    0.197ns
  Clock Net Delay (Source):      1.822ns (routing 0.606ns, distribution 1.216ns)
  Clock Net Delay (Destination): 2.188ns (routing 0.670ns, distribution 1.518ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.822     2.004    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X45Y93         FDSE                                         r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_cc.fifo_wr_rst_cc_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y93         FDSE (Prop_FFF_SLICEM_C_Q)
                                                      0.057     2.061 r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_cc.fifo_wr_rst_cc_reg[2]/Q
                         net (fo=40, routed)          0.155     2.215    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/rstb
    RAMB36_X4Y18         RAMB36E2                                     r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/RSTREGARSTREG
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.188     2.414    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clka
    RAMB36_X4Y18         RAMB36E2                                     r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0/CLKARDCLK
                         clock pessimism             -0.197     2.217    
    RAMB36_X4Y18         RAMB36E2 (Hold_RAMB36E2_RAMB36_CLKARDCLK_RSTREGARSTREG)
                                                     -0.012     2.205    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0
  -------------------------------------------------------------------
                         required time                         -2.205    
                         arrival time                           2.215    
  -------------------------------------------------------------------
                         slack                                  0.010    

Slack (MET) :             0.010ns  (arrival time - required time)
  Source:                 d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1025]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk_pl_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.241ns  (logic 0.061ns (25.311%)  route 0.180ns (74.689%))
  Logic Levels:           0  
  Clock Path Skew:        0.169ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.404ns
    Source Clock Delay      (SCD):    2.038ns
    Clock Pessimism Removal (CPR):    0.197ns
  Clock Net Delay (Source):      1.856ns (routing 0.606ns, distribution 1.250ns)
  Clock Net Delay (Destination): 2.178ns (routing 0.670ns, distribution 1.508ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.856     2.038    d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/m_axi_s2mm_aclk
    SLICE_X59Y77         FDRE                                         r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y77         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     2.099 r  d_1_i/axi_dma_avg/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_reg[0]/Q
                         net (fo=2, routed)           0.180     2.279    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/D[1]
    SLICE_X62Y64         FDRE                                         r  d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1025]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.178     2.404    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/aclk
    SLICE_X62Y64         FDRE                                         r  d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1025]/C
                         clock pessimism             -0.197     2.207    
    SLICE_X62Y64         FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     2.269    d_1_i/axi_smc/inst/s03_entry_pipeline/s03_mmu/inst/w_sreg/skid_buffer_reg[1025]
  -------------------------------------------------------------------
                         required time                         -2.269    
                         arrival time                           2.279    
  -------------------------------------------------------------------
                         slack                                  0.010    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_pl_0
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0] }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location           Pin
Min Period        n/a     FDRE/C             n/a            8.000         10.000      2.000      HDIOLOGIC_S_X0Y6   d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Min Period        n/a     FDRE/C             n/a            8.000         10.000      2.000      HDIOLOGIC_S_X0Y22  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
Min Period        n/a     FDRE/C             n/a            8.000         10.000      2.000      HDIOLOGIC_S_X0Y23  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Min Period        n/a     FDRE/C             n/a            8.000         10.000      2.000      HDIOLOGIC_S_X0Y10  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
Min Period        n/a     FDRE/C             n/a            8.000         10.000      2.000      HDIOLOGIC_S_X0Y11  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Min Period        n/a     RFADC/DCLK         n/a            4.000         10.000      6.000      RFADC_X0Y0         d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/DCLK
Min Period        n/a     RFADC/DCLK         n/a            4.000         10.000      6.000      RFADC_X0Y1         d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/DCLK
Min Period        n/a     RFADC/DCLK         n/a            4.000         10.000      6.000      RFADC_X0Y2         d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/DCLK
Min Period        n/a     RFADC/DCLK         n/a            4.000         10.000      6.000      RFADC_X0Y3         d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/DCLK
Min Period        n/a     RFDAC/DCLK         n/a            4.000         10.000      6.000      RFDAC_X0Y0         d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/DCLK
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       10.000      90.000     MMCM_X0Y2          d_1_i/clk_core/inst/mmcme4_adv_inst/CLKIN1
Low Pulse Width   Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y6   d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Low Pulse Width   Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y6   d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Low Pulse Width   Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y22  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
Low Pulse Width   Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y22  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
Low Pulse Width   Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y23  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Low Pulse Width   Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y23  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Low Pulse Width   Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y10  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
Low Pulse Width   Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y10  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
Low Pulse Width   Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y11  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
Low Pulse Width   Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y11  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
High Pulse Width  Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y6   d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
High Pulse Width  Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y6   d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
High Pulse Width  Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y22  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
High Pulse Width  Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y22  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
High Pulse Width  Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y23  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
High Pulse Width  Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y23  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
High Pulse Width  Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y10  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
High Pulse Width  Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y10  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C
High Pulse Width  Slow    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y11  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
High Pulse Width  Fast    FDRE/C             n/a            4.000         5.000       1.000      HDIOLOGIC_S_X0Y11  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C



---------------------------------------------------------------------------------------------------
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_out1_d_1_clk_core_0

Setup :            0  Failing Endpoints,  Worst Slack        0.752ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.016ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.958ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.752ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[47]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.058ns  (logic 1.177ns (29.001%)  route 2.881ns (70.999%))
  Logic Levels:           14  (CARRY8=6 LUT3=1 LUT4=2 LUT5=2 LUT6=3)
  Clock Path Skew:        -0.152ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.494ns = ( 9.494 - 5.000 ) 
    Source Clock Delay      (SCD):    4.301ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.836ns (routing 0.947ns, distribution 0.889ns)
  Clock Net Delay (Destination): 1.559ns (routing 0.863ns, distribution 0.696ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.836     4.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y212        FDCE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     4.380 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/Q
                         net (fo=10, routed)          0.223     4.603    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[1]
    SLICE_X35Y212        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     4.701 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1/O
                         net (fo=3, routed)           0.600     5.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1_n_0
    SLICE_X39Y215        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.401 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/AXI_DB.xreg_TPROC_DEBUG[4]_i_6/O
                         net (fo=2, routed)           0.295     5.696    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4
    SLICE_X45Y216        LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.796 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_11/O
                         net (fo=2, routed)           0.342     6.138    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_0
    SLICE_X53Y217        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.052     6.190 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=5, routed)           0.149     6.339    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/some_fifo_full
    SLICE_X53Y221        LUT4 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.100     6.439 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=540, routed)         0.346     6.785    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/D[0]
    SLICE_X51Y221        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     6.875 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.179     7.055    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][6]_1
    SLICE_X52Y220        LUT3 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.065     7.120 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_time_ref_dt[47]_i_11/O
                         net (fo=48, routed)          0.552     7.672    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_0
    SLICE_X54Y207        LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.797 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17/O
                         net (fo=1, routed)           0.013     7.810    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17_n_0
    SLICE_X54Y207        CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7])
                                                      0.192     8.002 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.028    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1_n_0
    SLICE_X54Y208        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.043 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.069    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1_n_0
    SLICE_X54Y209        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.084 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1/CO[7]
                         net (fo=1, routed)           0.052     8.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1_n_0
    SLICE_X54Y210        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.151 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.177    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1_n_0
    SLICE_X54Y211        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.192 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.218    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1_n_0
    SLICE_X54Y212        CARRY8 (Prop_CARRY8_SLICEM_CI_O[7])
                                                      0.116     8.334 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[47]_i_2/O[7]
                         net (fo=1, routed)           0.026     8.360    d_1_i/qick_processor_0/inst/QPROC/CORE_0_n_481
    SLICE_X54Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[47]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.559     9.494    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X54Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[47]/C
                         clock pessimism             -0.345     9.149    
                         clock uncertainty           -0.062     9.086    
    SLICE_X54Y212        FDCE (Setup_HFF_SLICEM_C_D)
                                                      0.025     9.111    d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[47]
  -------------------------------------------------------------------
                         required time                          9.111    
                         arrival time                          -8.360    
  -------------------------------------------------------------------
                         slack                                  0.752    

Slack (MET) :             0.753ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[45]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.057ns  (logic 1.177ns (29.008%)  route 2.880ns (70.992%))
  Logic Levels:           14  (CARRY8=6 LUT3=1 LUT4=2 LUT5=2 LUT6=3)
  Clock Path Skew:        -0.152ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.494ns = ( 9.494 - 5.000 ) 
    Source Clock Delay      (SCD):    4.301ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.836ns (routing 0.947ns, distribution 0.889ns)
  Clock Net Delay (Destination): 1.559ns (routing 0.863ns, distribution 0.696ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.836     4.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y212        FDCE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     4.380 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/Q
                         net (fo=10, routed)          0.223     4.603    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[1]
    SLICE_X35Y212        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     4.701 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1/O
                         net (fo=3, routed)           0.600     5.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1_n_0
    SLICE_X39Y215        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.401 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/AXI_DB.xreg_TPROC_DEBUG[4]_i_6/O
                         net (fo=2, routed)           0.295     5.696    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4
    SLICE_X45Y216        LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.796 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_11/O
                         net (fo=2, routed)           0.342     6.138    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_0
    SLICE_X53Y217        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.052     6.190 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=5, routed)           0.149     6.339    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/some_fifo_full
    SLICE_X53Y221        LUT4 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.100     6.439 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=540, routed)         0.346     6.785    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/D[0]
    SLICE_X51Y221        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     6.875 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.179     7.055    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][6]_1
    SLICE_X52Y220        LUT3 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.065     7.120 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_time_ref_dt[47]_i_11/O
                         net (fo=48, routed)          0.552     7.672    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_0
    SLICE_X54Y207        LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.797 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17/O
                         net (fo=1, routed)           0.013     7.810    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17_n_0
    SLICE_X54Y207        CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7])
                                                      0.192     8.002 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.028    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1_n_0
    SLICE_X54Y208        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.043 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.069    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1_n_0
    SLICE_X54Y209        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.084 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1/CO[7]
                         net (fo=1, routed)           0.052     8.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1_n_0
    SLICE_X54Y210        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.151 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.177    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1_n_0
    SLICE_X54Y211        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.192 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.218    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1_n_0
    SLICE_X54Y212        CARRY8 (Prop_CARRY8_SLICEM_CI_O[5])
                                                      0.116     8.334 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[47]_i_2/O[5]
                         net (fo=1, routed)           0.025     8.359    d_1_i/qick_processor_0/inst/QPROC/CORE_0_n_483
    SLICE_X54Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[45]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.559     9.494    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X54Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[45]/C
                         clock pessimism             -0.345     9.149    
                         clock uncertainty           -0.062     9.086    
    SLICE_X54Y212        FDCE (Setup_FFF_SLICEM_C_D)
                                                      0.025     9.111    d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[45]
  -------------------------------------------------------------------
                         required time                          9.111    
                         arrival time                          -8.359    
  -------------------------------------------------------------------
                         slack                                  0.753    

Slack (MET) :             0.765ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[46]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.045ns  (logic 1.164ns (28.773%)  route 2.881ns (71.227%))
  Logic Levels:           14  (CARRY8=6 LUT3=1 LUT4=2 LUT5=2 LUT6=3)
  Clock Path Skew:        -0.152ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.494ns = ( 9.494 - 5.000 ) 
    Source Clock Delay      (SCD):    4.301ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.836ns (routing 0.947ns, distribution 0.889ns)
  Clock Net Delay (Destination): 1.559ns (routing 0.863ns, distribution 0.696ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.836     4.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y212        FDCE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     4.380 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/Q
                         net (fo=10, routed)          0.223     4.603    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[1]
    SLICE_X35Y212        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     4.701 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1/O
                         net (fo=3, routed)           0.600     5.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1_n_0
    SLICE_X39Y215        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.401 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/AXI_DB.xreg_TPROC_DEBUG[4]_i_6/O
                         net (fo=2, routed)           0.295     5.696    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4
    SLICE_X45Y216        LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.796 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_11/O
                         net (fo=2, routed)           0.342     6.138    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_0
    SLICE_X53Y217        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.052     6.190 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=5, routed)           0.149     6.339    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/some_fifo_full
    SLICE_X53Y221        LUT4 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.100     6.439 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=540, routed)         0.346     6.785    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/D[0]
    SLICE_X51Y221        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     6.875 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.179     7.055    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][6]_1
    SLICE_X52Y220        LUT3 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.065     7.120 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_time_ref_dt[47]_i_11/O
                         net (fo=48, routed)          0.552     7.672    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_0
    SLICE_X54Y207        LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.797 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17/O
                         net (fo=1, routed)           0.013     7.810    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17_n_0
    SLICE_X54Y207        CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7])
                                                      0.192     8.002 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.028    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1_n_0
    SLICE_X54Y208        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.043 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.069    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1_n_0
    SLICE_X54Y209        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.084 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1/CO[7]
                         net (fo=1, routed)           0.052     8.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1_n_0
    SLICE_X54Y210        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.151 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.177    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1_n_0
    SLICE_X54Y211        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.192 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.218    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1_n_0
    SLICE_X54Y212        CARRY8 (Prop_CARRY8_SLICEM_CI_O[6])
                                                      0.103     8.321 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[47]_i_2/O[6]
                         net (fo=1, routed)           0.026     8.347    d_1_i/qick_processor_0/inst/QPROC/CORE_0_n_482
    SLICE_X54Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[46]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.559     9.494    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X54Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[46]/C
                         clock pessimism             -0.345     9.149    
                         clock uncertainty           -0.062     9.086    
    SLICE_X54Y212        FDCE (Setup_GFF_SLICEM_C_D)
                                                      0.025     9.111    d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[46]
  -------------------------------------------------------------------
                         required time                          9.111    
                         arrival time                          -8.347    
  -------------------------------------------------------------------
                         slack                                  0.765    

Slack (MET) :             0.783ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[44]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.027ns  (logic 1.147ns (28.479%)  route 2.880ns (71.521%))
  Logic Levels:           14  (CARRY8=6 LUT3=1 LUT4=2 LUT5=2 LUT6=3)
  Clock Path Skew:        -0.152ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.494ns = ( 9.494 - 5.000 ) 
    Source Clock Delay      (SCD):    4.301ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.836ns (routing 0.947ns, distribution 0.889ns)
  Clock Net Delay (Destination): 1.559ns (routing 0.863ns, distribution 0.696ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.836     4.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y212        FDCE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     4.380 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/Q
                         net (fo=10, routed)          0.223     4.603    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[1]
    SLICE_X35Y212        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     4.701 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1/O
                         net (fo=3, routed)           0.600     5.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1_n_0
    SLICE_X39Y215        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.401 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/AXI_DB.xreg_TPROC_DEBUG[4]_i_6/O
                         net (fo=2, routed)           0.295     5.696    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4
    SLICE_X45Y216        LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.796 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_11/O
                         net (fo=2, routed)           0.342     6.138    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_0
    SLICE_X53Y217        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.052     6.190 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=5, routed)           0.149     6.339    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/some_fifo_full
    SLICE_X53Y221        LUT4 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.100     6.439 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=540, routed)         0.346     6.785    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/D[0]
    SLICE_X51Y221        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     6.875 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.179     7.055    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][6]_1
    SLICE_X52Y220        LUT3 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.065     7.120 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_time_ref_dt[47]_i_11/O
                         net (fo=48, routed)          0.552     7.672    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_0
    SLICE_X54Y207        LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.797 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17/O
                         net (fo=1, routed)           0.013     7.810    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17_n_0
    SLICE_X54Y207        CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7])
                                                      0.192     8.002 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.028    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1_n_0
    SLICE_X54Y208        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.043 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.069    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1_n_0
    SLICE_X54Y209        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.084 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1/CO[7]
                         net (fo=1, routed)           0.052     8.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1_n_0
    SLICE_X54Y210        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.151 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.177    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1_n_0
    SLICE_X54Y211        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.192 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.218    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1_n_0
    SLICE_X54Y212        CARRY8 (Prop_CARRY8_SLICEM_CI_O[4])
                                                      0.086     8.304 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[47]_i_2/O[4]
                         net (fo=1, routed)           0.025     8.329    d_1_i/qick_processor_0/inst/QPROC/CORE_0_n_484
    SLICE_X54Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[44]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.559     9.494    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X54Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[44]/C
                         clock pessimism             -0.345     9.149    
                         clock uncertainty           -0.062     9.086    
    SLICE_X54Y212        FDCE (Setup_EFF_SLICEM_C_D)
                                                      0.025     9.111    d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[44]
  -------------------------------------------------------------------
                         required time                          9.111    
                         arrival time                          -8.329    
  -------------------------------------------------------------------
                         slack                                  0.783    

Slack (MET) :             0.787ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[43]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.024ns  (logic 1.143ns (28.401%)  route 2.881ns (71.599%))
  Logic Levels:           14  (CARRY8=6 LUT3=1 LUT4=2 LUT5=2 LUT6=3)
  Clock Path Skew:        -0.151ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.495ns = ( 9.495 - 5.000 ) 
    Source Clock Delay      (SCD):    4.301ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.836ns (routing 0.947ns, distribution 0.889ns)
  Clock Net Delay (Destination): 1.560ns (routing 0.863ns, distribution 0.697ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.836     4.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y212        FDCE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     4.380 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/Q
                         net (fo=10, routed)          0.223     4.603    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[1]
    SLICE_X35Y212        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     4.701 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1/O
                         net (fo=3, routed)           0.600     5.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1_n_0
    SLICE_X39Y215        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.401 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/AXI_DB.xreg_TPROC_DEBUG[4]_i_6/O
                         net (fo=2, routed)           0.295     5.696    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4
    SLICE_X45Y216        LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.796 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_11/O
                         net (fo=2, routed)           0.342     6.138    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_0
    SLICE_X53Y217        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.052     6.190 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=5, routed)           0.149     6.339    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/some_fifo_full
    SLICE_X53Y221        LUT4 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.100     6.439 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=540, routed)         0.346     6.785    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/D[0]
    SLICE_X51Y221        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     6.875 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.179     7.055    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][6]_1
    SLICE_X52Y220        LUT3 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.065     7.120 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_time_ref_dt[47]_i_11/O
                         net (fo=48, routed)          0.552     7.672    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_0
    SLICE_X54Y207        LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.797 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17/O
                         net (fo=1, routed)           0.013     7.810    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17_n_0
    SLICE_X54Y207        CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7])
                                                      0.192     8.002 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.028    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1_n_0
    SLICE_X54Y208        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.043 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.069    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1_n_0
    SLICE_X54Y209        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.084 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1/CO[7]
                         net (fo=1, routed)           0.052     8.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1_n_0
    SLICE_X54Y210        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.151 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.177    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1_n_0
    SLICE_X54Y211        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.192 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.218    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1_n_0
    SLICE_X54Y212        CARRY8 (Prop_CARRY8_SLICEM_CI_O[3])
                                                      0.082     8.300 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[47]_i_2/O[3]
                         net (fo=1, routed)           0.026     8.326    d_1_i/qick_processor_0/inst/QPROC/CORE_0_n_485
    SLICE_X54Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[43]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.560     9.495    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X54Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[43]/C
                         clock pessimism             -0.345     9.150    
                         clock uncertainty           -0.062     9.087    
    SLICE_X54Y212        FDCE (Setup_DFF_SLICEM_C_D)
                                                      0.025     9.112    d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[43]
  -------------------------------------------------------------------
                         required time                          9.112    
                         arrival time                          -8.326    
  -------------------------------------------------------------------
                         slack                                  0.787    

Slack (MET) :             0.794ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[41]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.017ns  (logic 1.137ns (28.301%)  route 2.880ns (71.699%))
  Logic Levels:           14  (CARRY8=6 LUT3=1 LUT4=2 LUT5=2 LUT6=3)
  Clock Path Skew:        -0.151ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.495ns = ( 9.495 - 5.000 ) 
    Source Clock Delay      (SCD):    4.301ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.836ns (routing 0.947ns, distribution 0.889ns)
  Clock Net Delay (Destination): 1.560ns (routing 0.863ns, distribution 0.697ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.836     4.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y212        FDCE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     4.380 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/Q
                         net (fo=10, routed)          0.223     4.603    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[1]
    SLICE_X35Y212        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     4.701 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1/O
                         net (fo=3, routed)           0.600     5.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1_n_0
    SLICE_X39Y215        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.401 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/AXI_DB.xreg_TPROC_DEBUG[4]_i_6/O
                         net (fo=2, routed)           0.295     5.696    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4
    SLICE_X45Y216        LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.796 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_11/O
                         net (fo=2, routed)           0.342     6.138    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_0
    SLICE_X53Y217        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.052     6.190 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=5, routed)           0.149     6.339    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/some_fifo_full
    SLICE_X53Y221        LUT4 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.100     6.439 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=540, routed)         0.346     6.785    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/D[0]
    SLICE_X51Y221        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     6.875 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.179     7.055    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][6]_1
    SLICE_X52Y220        LUT3 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.065     7.120 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_time_ref_dt[47]_i_11/O
                         net (fo=48, routed)          0.552     7.672    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_0
    SLICE_X54Y207        LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.797 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17/O
                         net (fo=1, routed)           0.013     7.810    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17_n_0
    SLICE_X54Y207        CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7])
                                                      0.192     8.002 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.028    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1_n_0
    SLICE_X54Y208        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.043 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.069    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1_n_0
    SLICE_X54Y209        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.084 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1/CO[7]
                         net (fo=1, routed)           0.052     8.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1_n_0
    SLICE_X54Y210        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.151 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.177    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1_n_0
    SLICE_X54Y211        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.192 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.218    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1_n_0
    SLICE_X54Y212        CARRY8 (Prop_CARRY8_SLICEM_CI_O[1])
                                                      0.076     8.294 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[47]_i_2/O[1]
                         net (fo=1, routed)           0.025     8.319    d_1_i/qick_processor_0/inst/QPROC/CORE_0_n_487
    SLICE_X54Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[41]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.560     9.495    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X54Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[41]/C
                         clock pessimism             -0.345     9.150    
                         clock uncertainty           -0.062     9.087    
    SLICE_X54Y212        FDCE (Setup_BFF_SLICEM_C_D)
                                                      0.025     9.112    d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[41]
  -------------------------------------------------------------------
                         required time                          9.112    
                         arrival time                          -8.319    
  -------------------------------------------------------------------
                         slack                                  0.794    

Slack (MET) :             0.797ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[39]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.017ns  (logic 1.162ns (28.924%)  route 2.855ns (71.076%))
  Logic Levels:           13  (CARRY8=5 LUT3=1 LUT4=2 LUT5=2 LUT6=3)
  Clock Path Skew:        -0.149ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.497ns = ( 9.497 - 5.000 ) 
    Source Clock Delay      (SCD):    4.301ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.836ns (routing 0.947ns, distribution 0.889ns)
  Clock Net Delay (Destination): 1.562ns (routing 0.863ns, distribution 0.699ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.836     4.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y212        FDCE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     4.380 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/Q
                         net (fo=10, routed)          0.223     4.603    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[1]
    SLICE_X35Y212        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     4.701 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1/O
                         net (fo=3, routed)           0.600     5.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1_n_0
    SLICE_X39Y215        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.401 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/AXI_DB.xreg_TPROC_DEBUG[4]_i_6/O
                         net (fo=2, routed)           0.295     5.696    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4
    SLICE_X45Y216        LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.796 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_11/O
                         net (fo=2, routed)           0.342     6.138    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_0
    SLICE_X53Y217        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.052     6.190 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=5, routed)           0.149     6.339    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/some_fifo_full
    SLICE_X53Y221        LUT4 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.100     6.439 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=540, routed)         0.346     6.785    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/D[0]
    SLICE_X51Y221        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     6.875 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.179     7.055    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][6]_1
    SLICE_X52Y220        LUT3 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.065     7.120 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_time_ref_dt[47]_i_11/O
                         net (fo=48, routed)          0.552     7.672    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_0
    SLICE_X54Y207        LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.797 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17/O
                         net (fo=1, routed)           0.013     7.810    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17_n_0
    SLICE_X54Y207        CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7])
                                                      0.192     8.002 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.028    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1_n_0
    SLICE_X54Y208        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.043 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.069    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1_n_0
    SLICE_X54Y209        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.084 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1/CO[7]
                         net (fo=1, routed)           0.052     8.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1_n_0
    SLICE_X54Y210        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.151 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.177    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1_n_0
    SLICE_X54Y211        CARRY8 (Prop_CARRY8_SLICEM_CI_O[7])
                                                      0.116     8.293 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1/O[7]
                         net (fo=1, routed)           0.026     8.319    d_1_i/qick_processor_0/inst/QPROC/CORE_0_n_489
    SLICE_X54Y211        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[39]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.562     9.497    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X54Y211        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[39]/C
                         clock pessimism             -0.345     9.152    
                         clock uncertainty           -0.062     9.090    
    SLICE_X54Y211        FDCE (Setup_HFF_SLICEM_C_D)
                                                      0.025     9.115    d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[39]
  -------------------------------------------------------------------
                         required time                          9.115    
                         arrival time                          -8.319    
  -------------------------------------------------------------------
                         slack                                  0.797    

Slack (MET) :             0.798ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[37]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.016ns  (logic 1.162ns (28.931%)  route 2.854ns (71.069%))
  Logic Levels:           13  (CARRY8=5 LUT3=1 LUT4=2 LUT5=2 LUT6=3)
  Clock Path Skew:        -0.149ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.497ns = ( 9.497 - 5.000 ) 
    Source Clock Delay      (SCD):    4.301ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.836ns (routing 0.947ns, distribution 0.889ns)
  Clock Net Delay (Destination): 1.562ns (routing 0.863ns, distribution 0.699ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.836     4.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y212        FDCE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     4.380 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/Q
                         net (fo=10, routed)          0.223     4.603    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[1]
    SLICE_X35Y212        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     4.701 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1/O
                         net (fo=3, routed)           0.600     5.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1_n_0
    SLICE_X39Y215        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.401 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/AXI_DB.xreg_TPROC_DEBUG[4]_i_6/O
                         net (fo=2, routed)           0.295     5.696    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4
    SLICE_X45Y216        LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.796 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_11/O
                         net (fo=2, routed)           0.342     6.138    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_0
    SLICE_X53Y217        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.052     6.190 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=5, routed)           0.149     6.339    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/some_fifo_full
    SLICE_X53Y221        LUT4 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.100     6.439 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=540, routed)         0.346     6.785    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/D[0]
    SLICE_X51Y221        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     6.875 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.179     7.055    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][6]_1
    SLICE_X52Y220        LUT3 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.065     7.120 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_time_ref_dt[47]_i_11/O
                         net (fo=48, routed)          0.552     7.672    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_0
    SLICE_X54Y207        LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.797 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17/O
                         net (fo=1, routed)           0.013     7.810    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17_n_0
    SLICE_X54Y207        CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7])
                                                      0.192     8.002 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.028    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1_n_0
    SLICE_X54Y208        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.043 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.069    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1_n_0
    SLICE_X54Y209        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.084 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1/CO[7]
                         net (fo=1, routed)           0.052     8.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1_n_0
    SLICE_X54Y210        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.151 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.177    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1_n_0
    SLICE_X54Y211        CARRY8 (Prop_CARRY8_SLICEM_CI_O[5])
                                                      0.116     8.293 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1/O[5]
                         net (fo=1, routed)           0.025     8.318    d_1_i/qick_processor_0/inst/QPROC/CORE_0_n_491
    SLICE_X54Y211        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[37]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.562     9.497    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X54Y211        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[37]/C
                         clock pessimism             -0.345     9.152    
                         clock uncertainty           -0.062     9.090    
    SLICE_X54Y211        FDCE (Setup_FFF_SLICEM_C_D)
                                                      0.025     9.115    d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[37]
  -------------------------------------------------------------------
                         required time                          9.115    
                         arrival time                          -8.318    
  -------------------------------------------------------------------
                         slack                                  0.798    

Slack (MET) :             0.802ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[42]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.009ns  (logic 1.128ns (28.133%)  route 2.881ns (71.867%))
  Logic Levels:           14  (CARRY8=6 LUT3=1 LUT4=2 LUT5=2 LUT6=3)
  Clock Path Skew:        -0.151ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.495ns = ( 9.495 - 5.000 ) 
    Source Clock Delay      (SCD):    4.301ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.836ns (routing 0.947ns, distribution 0.889ns)
  Clock Net Delay (Destination): 1.560ns (routing 0.863ns, distribution 0.697ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.836     4.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y212        FDCE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     4.380 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/Q
                         net (fo=10, routed)          0.223     4.603    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[1]
    SLICE_X35Y212        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     4.701 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1/O
                         net (fo=3, routed)           0.600     5.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1_n_0
    SLICE_X39Y215        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.401 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/AXI_DB.xreg_TPROC_DEBUG[4]_i_6/O
                         net (fo=2, routed)           0.295     5.696    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4
    SLICE_X45Y216        LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.796 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_11/O
                         net (fo=2, routed)           0.342     6.138    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_0
    SLICE_X53Y217        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.052     6.190 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=5, routed)           0.149     6.339    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/some_fifo_full
    SLICE_X53Y221        LUT4 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.100     6.439 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=540, routed)         0.346     6.785    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/D[0]
    SLICE_X51Y221        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     6.875 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.179     7.055    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][6]_1
    SLICE_X52Y220        LUT3 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.065     7.120 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_time_ref_dt[47]_i_11/O
                         net (fo=48, routed)          0.552     7.672    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_0
    SLICE_X54Y207        LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.797 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17/O
                         net (fo=1, routed)           0.013     7.810    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17_n_0
    SLICE_X54Y207        CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7])
                                                      0.192     8.002 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.028    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1_n_0
    SLICE_X54Y208        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.043 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.069    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1_n_0
    SLICE_X54Y209        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.084 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1/CO[7]
                         net (fo=1, routed)           0.052     8.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1_n_0
    SLICE_X54Y210        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.151 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.177    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1_n_0
    SLICE_X54Y211        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.192 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.218    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1_n_0
    SLICE_X54Y212        CARRY8 (Prop_CARRY8_SLICEM_CI_O[2])
                                                      0.067     8.285 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[47]_i_2/O[2]
                         net (fo=1, routed)           0.026     8.311    d_1_i/qick_processor_0/inst/QPROC/CORE_0_n_486
    SLICE_X54Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[42]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.560     9.495    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X54Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[42]/C
                         clock pessimism             -0.345     9.150    
                         clock uncertainty           -0.062     9.087    
    SLICE_X54Y212        FDCE (Setup_CFF_SLICEM_C_D)
                                                      0.025     9.112    d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[42]
  -------------------------------------------------------------------
                         required time                          9.112    
                         arrival time                          -8.311    
  -------------------------------------------------------------------
                         slack                                  0.802    

Slack (MET) :             0.810ns  (required time - arrival time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[38]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        4.004ns  (logic 1.149ns (28.693%)  route 2.855ns (71.307%))
  Logic Levels:           13  (CARRY8=5 LUT3=1 LUT4=2 LUT5=2 LUT6=3)
  Clock Path Skew:        -0.149ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.497ns = ( 9.497 - 5.000 ) 
    Source Clock Delay      (SCD):    4.301ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.836ns (routing 0.947ns, distribution 0.889ns)
  Clock Net Delay (Destination): 1.562ns (routing 0.863ns, distribution 0.699ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.836     4.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y212        FDCE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     4.380 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/Q
                         net (fo=10, routed)          0.223     4.603    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[1]
    SLICE_X35Y212        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     4.701 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1/O
                         net (fo=3, routed)           0.600     5.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1_n_0
    SLICE_X39Y215        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.401 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/AXI_DB.xreg_TPROC_DEBUG[4]_i_6/O
                         net (fo=2, routed)           0.295     5.696    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4
    SLICE_X45Y216        LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.796 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_11/O
                         net (fo=2, routed)           0.342     6.138    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_0
    SLICE_X53Y217        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.052     6.190 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=5, routed)           0.149     6.339    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/some_fifo_full
    SLICE_X53Y221        LUT4 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.100     6.439 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=540, routed)         0.346     6.785    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/D[0]
    SLICE_X51Y221        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     6.875 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.179     7.055    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][6]_1
    SLICE_X52Y220        LUT3 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.065     7.120 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_time_ref_dt[47]_i_11/O
                         net (fo=48, routed)          0.552     7.672    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_0
    SLICE_X54Y207        LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     7.797 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17/O
                         net (fo=1, routed)           0.013     7.810    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt[7]_i_17_n_0
    SLICE_X54Y207        CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[7])
                                                      0.192     8.002 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.028    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[7]_i_1_n_0
    SLICE_X54Y208        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.043 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.069    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[15]_i_1_n_0
    SLICE_X54Y209        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.084 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1/CO[7]
                         net (fo=1, routed)           0.052     8.136    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[23]_i_1_n_0
    SLICE_X54Y210        CARRY8 (Prop_CARRY8_SLICEM_CI_CO[7])
                                                      0.015     8.151 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1/CO[7]
                         net (fo=1, routed)           0.026     8.177    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[31]_i_1_n_0
    SLICE_X54Y211        CARRY8 (Prop_CARRY8_SLICEM_CI_O[6])
                                                      0.103     8.280 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/ctrl_hzrd/c_time_ref_dt_reg[39]_i_1/O[6]
                         net (fo=1, routed)           0.026     8.306    d_1_i/qick_processor_0/inst/QPROC/CORE_0_n_490
    SLICE_X54Y211        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[38]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.562     9.497    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X54Y211        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[38]/C
                         clock pessimism             -0.345     9.152    
                         clock uncertainty           -0.062     9.090    
    SLICE_X54Y211        FDCE (Setup_GFF_SLICEM_C_D)
                                                      0.025     9.115    d_1_i/qick_processor_0/inst/QPROC/c_time_ref_dt_reg[38]
  -------------------------------------------------------------------
                         required time                          9.115    
                         arrival time                          -8.306    
  -------------------------------------------------------------------
                         slack                                  0.810    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.016ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x2_reg_reg[addr][5]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/wr_reg_reg[addr][5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.186ns  (logic 0.058ns (31.100%)  route 0.128ns (68.900%))
  Logic Levels:           0  
  Clock Path Skew:        0.108ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.263ns
    Source Clock Delay      (SCD):    4.503ns
    Clock Pessimism Removal (CPR):    -0.348ns
  Clock Net Delay (Source):      1.568ns (routing 0.863ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.798ns (routing 0.947ns, distribution 0.851ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.568     4.503    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X60Y218        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x2_reg_reg[addr][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y218        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.058     4.561 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x2_reg_reg[addr][5]/Q
                         net (fo=14, routed)          0.128     4.689    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x2_reg_reg[addr_n_0_][5]
    SLICE_X58Y220        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/wr_reg_reg[addr][5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.798     4.263    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X58Y220        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/wr_reg_reg[addr][5]/C
                         clock pessimism              0.348     4.611    
    SLICE_X58Y220        FDRE (Hold_EFF2_SLICEL_C_D)
                                                      0.062     4.673    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/wr_reg_reg[addr][5]
  -------------------------------------------------------------------
                         required time                         -4.673    
                         arrival time                           4.689    
  -------------------------------------------------------------------
                         slack                                  0.016    

Slack (MET) :             0.024ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][23]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.134ns  (logic 0.060ns (44.776%)  route 0.074ns (55.224%))
  Logic Levels:           0  
  Clock Path Skew:        0.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.337ns
    Source Clock Delay      (SCD):    4.581ns
    Clock Pessimism Removal (CPR):    -0.292ns
  Clock Net Delay (Source):      1.646ns (routing 0.863ns, distribution 0.783ns)
  Clock Net Delay (Destination): 1.872ns (routing 0.947ns, distribution 0.925ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.646     4.581    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X64Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y183        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.060     4.641 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[23]/Q
                         net (fo=1, routed)           0.074     4.715    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg[23]
    SLICE_X64Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][23]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.872     4.337    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X64Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][23]/C
                         clock pessimism              0.292     4.629    
    SLICE_X64Y184        FDRE (Hold_AFF2_SLICEL_C_D)
                                                      0.062     4.691    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][23]
  -------------------------------------------------------------------
                         required time                         -4.691    
                         arrival time                           4.715    
  -------------------------------------------------------------------
                         slack                                  0.024    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.083ns  (logic 0.038ns (45.959%)  route 0.045ns (54.041%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.424ns
    Source Clock Delay      (SCD):    2.641ns
    Clock Pessimism Removal (CPR):    -0.223ns
  Clock Net Delay (Source):      0.981ns (routing 0.518ns, distribution 0.463ns)
  Clock Net Delay (Destination): 1.107ns (routing 0.574ns, distribution 0.533ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.981     2.641    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/c_clk_i
    SLICE_X56Y239        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y239        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.679 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.045     2.724    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clr_fifo_req
    SLICE_X56Y239        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.107     2.424    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X56Y239        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg/C
                         clock pessimism              0.223     2.647    
    SLICE_X56Y239        FDCE (Hold_GFF2_SLICEM_C_D)
                                                      0.047     2.694    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[6].wave_fifo_inst/gcc_wr_ptr/clear_cdc_reg
  -------------------------------------------------------------------
                         required time                         -2.694    
                         arrival time                           2.724    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_2r_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.083ns  (logic 0.039ns (46.988%)  route 0.044ns (53.012%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    2.640ns
    Clock Pessimism Removal (CPR):    -0.222ns
  Clock Net Delay (Source):      0.980ns (routing 0.518ns, distribution 0.462ns)
  Clock Net Delay (Destination): 1.106ns (routing 0.574ns, distribution 0.532ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.980     2.640    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X51Y198        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y198        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.679 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[4]/Q
                         net (fo=2, routed)           0.044     2.723    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r[4]
    SLICE_X51Y198        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_2r_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.106     2.423    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X51Y198        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_2r_reg[4]/C
                         clock pessimism              0.222     2.646    
    SLICE_X51Y198        FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.046     2.692    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_2r_reg[4]
  -------------------------------------------------------------------
                         required time                         -2.692    
                         arrival time                           2.723    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_2r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.176ns  (logic 0.058ns (32.958%)  route 0.118ns (67.042%))
  Logic Levels:           0  
  Clock Path Skew:        0.085ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.241ns
    Source Clock Delay      (SCD):    4.504ns
    Clock Pessimism Removal (CPR):    -0.348ns
  Clock Net Delay (Source):      1.569ns (routing 0.863ns, distribution 0.706ns)
  Clock Net Delay (Destination): 1.776ns (routing 0.947ns, distribution 0.829ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.569     4.504    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X50Y191        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y191        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     4.562 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r_reg[7]/Q
                         net (fo=3, routed)           0.118     4.680    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_r[7]
    SLICE_X49Y193        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_2r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.776     4.241    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X49Y193        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_2r_reg[7]/C
                         clock pessimism              0.348     4.589    
    SLICE_X49Y193        FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.060     4.649    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/tproc_ctrl_2r_reg[7]
  -------------------------------------------------------------------
                         required time                         -4.649    
                         arrival time                           4.680    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[1][4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/reg_out_i_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.179ns  (logic 0.098ns (54.770%)  route 0.081ns (45.230%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.086ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.354ns
    Source Clock Delay      (SCD):    4.608ns
    Clock Pessimism Removal (CPR):    -0.340ns
  Clock Net Delay (Source):      1.673ns (routing 0.863ns, distribution 0.810ns)
  Clock Net Delay (Destination): 1.889ns (routing 0.947ns, distribution 0.942ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.673     4.608    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X67Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[1][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y183        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.060     4.668 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[1][4]/Q
                         net (fo=5, routed)           0.068     4.736    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff[1][4]
    SLICE_X69Y183        LUT2 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.038     4.774 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_out_bin[3]_INST_0/O
                         net (fo=1, routed)           0.013     4.787    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/D[3]
    SLICE_X69Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/reg_out_i_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.889     4.354    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/rd_clk
    SLICE_X69Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/reg_out_i_reg[3]/C
                         clock pessimism              0.340     4.694    
    SLICE_X69Y183        FDRE (Hold_DFF2_SLICEM_C_D)
                                                      0.061     4.755    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wpr_gray_reg/reg_out_i_reg[3]
  -------------------------------------------------------------------
                         required time                         -4.755    
                         arrival time                           4.787    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][51]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r_reg[51]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.088ns  (logic 0.059ns (67.045%)  route 0.029ns (32.955%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.009ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.428ns
    Source Clock Delay      (SCD):    2.648ns
    Clock Pessimism Removal (CPR):    -0.228ns
  Clock Net Delay (Source):      0.988ns (routing 0.518ns, distribution 0.470ns)
  Clock Net Delay (Destination): 1.111ns (routing 0.574ns, distribution 0.537ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.988     2.648    d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/c_clk_i
    SLICE_X57Y183        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][51]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y183        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.687 r  d_1_i/qick_processor_0/inst/QPROC/IN_PORT_REG/genblk1[1].port_dt_r_reg[1][51]/Q
                         net (fo=1, routed)           0.023     2.710    d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r_reg[63]_1[51]
    SLICE_X57Y183        LUT3 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.020     2.730 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r[51]_i_1/O
                         net (fo=1, routed)           0.006     2.736    d_1_i/qick_processor_0/inst/QPROC/CORE_0/p_0_in_0[51]
    SLICE_X57Y183        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r_reg[51]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.111     2.428    d_1_i/qick_processor_0/inst/QPROC/CORE_0/c_clk_i
    SLICE_X57Y183        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r_reg[51]/C
                         clock pessimism              0.228     2.656    
    SLICE_X57Y183        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     2.703    d_1_i/qick_processor_0/inst/QPROC/CORE_0/in_port_dt_r_reg[51]
  -------------------------------------------------------------------
                         required time                         -2.703    
                         arrival time                           2.736    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.033ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[4][26]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[146]/D
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.179ns  (logic 0.095ns (52.973%)  route 0.084ns (47.026%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.087ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.319ns
    Source Clock Delay      (SCD):    4.572ns
    Clock Pessimism Removal (CPR):    -0.340ns
  Clock Net Delay (Source):      1.637ns (routing 0.863ns, distribution 0.774ns)
  Clock Net Delay (Destination): 1.854ns (routing 0.947ns, distribution 0.907ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.637     4.572    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_clk_i
    SLICE_X64Y202        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[4][26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y202        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     4.631 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[4][26]/Q
                         net (fo=5, routed)           0.062     4.693    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/wreg_32_dt_reg[4][31]_0[26]
    SLICE_X62Y202        LUT4 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.036     4.729 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/reg_bank/c_fifo_data_in_r[146]_i_1/O
                         net (fo=1, routed)           0.022     4.751    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[167]_0[146]
    SLICE_X62Y202        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[146]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.854     4.319    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X62Y202        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[146]/C
                         clock pessimism              0.340     4.659    
    SLICE_X62Y202        FDCE (Hold_BFF_SLICEL_C_D)
                                                      0.060     4.719    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_fifo_data_in_r_reg[146]
  -------------------------------------------------------------------
                         required time                         -4.719    
                         arrival time                           4.751    
  -------------------------------------------------------------------
                         slack                                  0.033    

Slack (MET) :             0.033ns  (arrival time - required time)
  Source:                 d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/rd_reg_reg[addr][4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_reg_reg[addr][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.135ns  (logic 0.058ns (42.982%)  route 0.077ns (57.018%))
  Logic Levels:           0  
  Clock Path Skew:        0.040ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.264ns
    Source Clock Delay      (SCD):    4.512ns
    Clock Pessimism Removal (CPR):    -0.288ns
  Clock Net Delay (Source):      1.577ns (routing 0.863ns, distribution 0.714ns)
  Clock Net Delay (Destination): 1.799ns (routing 0.947ns, distribution 0.852ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.577     4.512    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X59Y221        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/rd_reg_reg[addr][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X59Y221        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     4.570 r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/rd_reg_reg[addr][4]/Q
                         net (fo=4, routed)           0.077     4.647    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/rd_reg_reg[addr_n_0_][4]
    SLICE_X59Y221        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_reg_reg[addr][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.799     4.264    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/c_clk_i
    SLICE_X59Y221        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_reg_reg[addr][4]/C
                         clock pessimism              0.288     4.552    
    SLICE_X59Y221        FDRE (Hold_FFF2_SLICEL_C_D)
                                                      0.062     4.614    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_reg_reg[addr][4]
  -------------------------------------------------------------------
                         required time                         -4.614    
                         arrival time                           4.647    
  -------------------------------------------------------------------
                         slack                                  0.033    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[53]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][53]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             clk_out1_d_1_clk_core_0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        0.209ns  (logic 0.059ns (28.230%)  route 0.150ns (71.770%))
  Logic Levels:           0  
  Clock Path Skew:        0.113ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    4.276ns
    Source Clock Delay      (SCD):    4.511ns
    Clock Pessimism Removal (CPR):    -0.348ns
  Clock Net Delay (Source):      1.576ns (routing 0.863ns, distribution 0.713ns)
  Clock Net Delay (Destination): 1.811ns (routing 0.947ns, distribution 0.864ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.576     4.511    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X52Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[53]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y183        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.059     4.570 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[53]/Q
                         net (fo=1, routed)           0.150     4.720    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg[53]
    SLICE_X55Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][53]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.811     4.276    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X55Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][53]/C
                         clock pessimism              0.348     4.624    
    SLICE_X55Y183        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.062     4.686    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.gen_doutb_pipe.doutb_pipe_reg[0][53]
  -------------------------------------------------------------------
                         required time                         -4.686    
                         arrival time                           4.720    
  -------------------------------------------------------------------
                         slack                                  0.034    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk_out1_d_1_clk_core_0
Waveform(ns):       { 0.000 2.500 }
Period(ns):         5.000
Sources:            { d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y40  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y41  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y43  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_2/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y44  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/D_MEM/RAM_reg_bram_3/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y42  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_0/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X5Y41  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_1/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y39  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_2/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X6Y38  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_3/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.569         5.000       3.431      RAMB36_X7Y40  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4/CLKBWRCLK
Min Period        n/a     RAMB36E2/CLKBWRCLK  n/a            1.355         5.000       3.645      RAMB36_X3Y44  d_1_i/qick_processor_0/TRIG_FIFO[0].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X3Y44  d_1_i/qick_processor_0/TRIG_FIFO[0].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X3Y44  d_1_i/qick_processor_0/TRIG_FIFO[0].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X3Y42  d_1_i/qick_processor_0/TRIG_FIFO[1].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X3Y42  d_1_i/qick_processor_0/TRIG_FIFO[1].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X3Y43  d_1_i/qick_processor_0/TRIG_FIFO[2].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X3Y43  d_1_i/qick_processor_0/TRIG_FIFO[2].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X4Y43  d_1_i/qick_processor_0/TRIG_FIFO[3].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X4Y43  d_1_i/qick_processor_0/TRIG_FIFO[3].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
Low Pulse Width   Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X4Y46  d_1_i/qick_processor_0/TRIG_FIFO[4].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
Low Pulse Width   Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X4Y46  d_1_i/qick_processor_0/TRIG_FIFO[4].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X3Y44  d_1_i/qick_processor_0/TRIG_FIFO[0].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X3Y44  d_1_i/qick_processor_0/TRIG_FIFO[0].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X3Y42  d_1_i/qick_processor_0/TRIG_FIFO[1].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X3Y42  d_1_i/qick_processor_0/TRIG_FIFO[1].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X3Y43  d_1_i/qick_processor_0/TRIG_FIFO[2].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X3Y43  d_1_i/qick_processor_0/TRIG_FIFO[2].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X4Y43  d_1_i/qick_processor_0/TRIG_FIFO[3].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X4Y43  d_1_i/qick_processor_0/TRIG_FIFO[3].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
High Pulse Width  Slow    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X4Y46  d_1_i/qick_processor_0/TRIG_FIFO[4].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK
High Pulse Width  Fast    RAMB36E2/CLKBWRCLK  n/a            0.542         2.500       1.958      RAMB36_X4Y46  d_1_i/qick_processor_0/TRIG_FIFO[4].trig_fifo_inst/fifo_mem/RAM_reg/CLKBWRCLK



---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       14.972ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.016ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack       24.468ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             14.972ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDO
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        2.110ns  (logic 0.361ns (17.109%)  route 1.749ns (82.891%))
  Logic Levels:           3  (LUT3=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -7.682ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    0.000ns = ( 25.000 - 25.000 ) 
    Source Clock Delay      (SCD):    7.682ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Source):      1.932ns (routing 1.068ns, distribution 0.864ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.932     7.682    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X105Y79        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y79        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     7.761 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state_reg[0]/Q
                         net (fo=50, routed)          0.378     8.139    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/state[0]
    SLICE_X106Y81        LUT5 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.124     8.263 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_bscanid_en_INST_0/O
                         net (fo=35, routed)          0.394     8.657    dbg_hub/inst/BSCANID.u_xsdbm_id/bscanid_en_int
    SLICE_X105Y78        LUT3 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.123     8.780 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch_i_1/O
                         net (fo=2, routed)           0.443     9.223    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_tdo[0]
    SLICE_X106Y81        LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.035     9.258 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdo_INST_0/O
                         net (fo=1, routed)           0.534     9.792    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/TDO
    CONFIG_SITE_X0Y0     BSCANE2                                      r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDO
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                         clock pessimism              0.000    25.000    
                         clock uncertainty           -0.235    24.765    
    CONFIG_SITE_X0Y0     BSCANE2 (Setup_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TDO)
                                                      0.000    24.765    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst
  -------------------------------------------------------------------
                         required time                         24.765    
                         arrival time                          -9.792    
  -------------------------------------------------------------------
                         slack                                 14.972    

Slack (MET) :             20.383ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[25]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.628ns  (logic 5.147ns (77.651%)  route 1.481ns (22.349%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        2.291ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.291ns = ( 52.291 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.054ns (routing 0.587ns, distribution 0.467ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_RESET)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/RESET
                         net (fo=79, routed)          1.109    31.209    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_reset
    SLICE_X107Y83        LUT5 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.047    31.256 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1/O
                         net (fo=32, routed)          0.372    31.628    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0
    SLICE_X102Y82        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[25]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755    51.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    51.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.054    52.291    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X102Y82        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[25]/C
                         clock pessimism              0.000    52.291    
                         clock uncertainty           -0.235    52.056    
    SLICE_X102Y82        FDRE (Setup_DFF_SLICEL_C_R)
                                                     -0.044    52.012    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[25]
  -------------------------------------------------------------------
                         required time                         52.012    
                         arrival time                         -31.628    
  -------------------------------------------------------------------
                         slack                                 20.383    

Slack (MET) :             20.383ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[26]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.628ns  (logic 5.147ns (77.651%)  route 1.481ns (22.349%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        2.291ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.291ns = ( 52.291 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.054ns (routing 0.587ns, distribution 0.467ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_RESET)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/RESET
                         net (fo=79, routed)          1.109    31.209    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_reset
    SLICE_X107Y83        LUT5 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.047    31.256 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1/O
                         net (fo=32, routed)          0.372    31.628    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0
    SLICE_X102Y82        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[26]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755    51.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    51.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.054    52.291    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X102Y82        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[26]/C
                         clock pessimism              0.000    52.291    
                         clock uncertainty           -0.235    52.056    
    SLICE_X102Y82        FDRE (Setup_CFF_SLICEL_C_R)
                                                     -0.044    52.012    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[26]
  -------------------------------------------------------------------
                         required time                         52.012    
                         arrival time                         -31.628    
  -------------------------------------------------------------------
                         slack                                 20.383    

Slack (MET) :             20.383ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[27]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.628ns  (logic 5.147ns (77.651%)  route 1.481ns (22.349%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        2.291ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.291ns = ( 52.291 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.054ns (routing 0.587ns, distribution 0.467ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_RESET)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/RESET
                         net (fo=79, routed)          1.109    31.209    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_reset
    SLICE_X107Y83        LUT5 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.047    31.256 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1/O
                         net (fo=32, routed)          0.372    31.628    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0
    SLICE_X102Y82        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[27]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755    51.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    51.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.054    52.291    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X102Y82        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[27]/C
                         clock pessimism              0.000    52.291    
                         clock uncertainty           -0.235    52.056    
    SLICE_X102Y82        FDRE (Setup_BFF_SLICEL_C_R)
                                                     -0.044    52.012    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[27]
  -------------------------------------------------------------------
                         required time                         52.012    
                         arrival time                         -31.628    
  -------------------------------------------------------------------
                         slack                                 20.383    

Slack (MET) :             20.396ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[6]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.620ns  (logic 5.147ns (77.755%)  route 1.473ns (22.245%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        2.295ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.295ns = ( 52.295 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.058ns (routing 0.587ns, distribution 0.471ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_RESET)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/RESET
                         net (fo=79, routed)          1.109    31.209    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_reset
    SLICE_X107Y83        LUT5 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.047    31.256 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1/O
                         net (fo=32, routed)          0.364    31.620    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0
    SLICE_X105Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[6]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755    51.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    51.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.058    52.295    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X105Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[6]/C
                         clock pessimism              0.000    52.295    
                         clock uncertainty           -0.235    52.060    
    SLICE_X105Y80        FDRE (Setup_DFF_SLICEL_C_R)
                                                     -0.044    52.016    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[6]
  -------------------------------------------------------------------
                         required time                         52.016    
                         arrival time                         -31.620    
  -------------------------------------------------------------------
                         slack                                 20.396    

Slack (MET) :             20.396ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[7]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.620ns  (logic 5.147ns (77.755%)  route 1.473ns (22.245%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        2.295ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.295ns = ( 52.295 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.058ns (routing 0.587ns, distribution 0.471ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_RESET)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/RESET
                         net (fo=79, routed)          1.109    31.209    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_reset
    SLICE_X107Y83        LUT5 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.047    31.256 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1/O
                         net (fo=32, routed)          0.364    31.620    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0
    SLICE_X105Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[7]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755    51.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    51.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.058    52.295    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X105Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[7]/C
                         clock pessimism              0.000    52.295    
                         clock uncertainty           -0.235    52.060    
    SLICE_X105Y80        FDRE (Setup_CFF_SLICEL_C_R)
                                                     -0.044    52.016    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[7]
  -------------------------------------------------------------------
                         required time                         52.016    
                         arrival time                         -31.620    
  -------------------------------------------------------------------
                         slack                                 20.396    

Slack (MET) :             20.451ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[17]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.566ns  (logic 5.147ns (78.394%)  route 1.419ns (21.606%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        2.296ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.296ns = ( 52.296 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.059ns (routing 0.587ns, distribution 0.472ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_RESET)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/RESET
                         net (fo=79, routed)          1.109    31.209    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_reset
    SLICE_X107Y83        LUT5 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.047    31.256 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1/O
                         net (fo=32, routed)          0.310    31.566    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0
    SLICE_X105Y84        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[17]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755    51.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    51.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.059    52.296    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X105Y84        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[17]/C
                         clock pessimism              0.000    52.296    
                         clock uncertainty           -0.235    52.060    
    SLICE_X105Y84        FDRE (Setup_DFF_SLICEL_C_R)
                                                     -0.044    52.016    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[17]
  -------------------------------------------------------------------
                         required time                         52.016    
                         arrival time                         -31.566    
  -------------------------------------------------------------------
                         slack                                 20.451    

Slack (MET) :             20.451ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[22]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.566ns  (logic 5.147ns (78.394%)  route 1.419ns (21.606%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        2.296ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.296ns = ( 52.296 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.059ns (routing 0.587ns, distribution 0.472ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_RESET)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/RESET
                         net (fo=79, routed)          1.109    31.209    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_reset
    SLICE_X107Y83        LUT5 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.047    31.256 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1/O
                         net (fo=32, routed)          0.310    31.566    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0
    SLICE_X105Y84        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[22]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755    51.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    51.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.059    52.296    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X105Y84        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[22]/C
                         clock pessimism              0.000    52.296    
                         clock uncertainty           -0.235    52.060    
    SLICE_X105Y84        FDRE (Setup_CFF_SLICEL_C_R)
                                                     -0.044    52.016    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[22]
  -------------------------------------------------------------------
                         required time                         52.016    
                         arrival time                         -31.566    
  -------------------------------------------------------------------
                         slack                                 20.451    

Slack (MET) :             20.451ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[23]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.566ns  (logic 5.147ns (78.394%)  route 1.419ns (21.606%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        2.296ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.296ns = ( 52.296 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.059ns (routing 0.587ns, distribution 0.472ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_RESET)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/RESET
                         net (fo=79, routed)          1.109    31.209    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_reset
    SLICE_X107Y83        LUT5 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.047    31.256 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1/O
                         net (fo=32, routed)          0.310    31.566    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0
    SLICE_X105Y84        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[23]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755    51.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    51.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.059    52.296    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X105Y84        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[23]/C
                         clock pessimism              0.000    52.296    
                         clock uncertainty           -0.235    52.060    
    SLICE_X105Y84        FDRE (Setup_BFF_SLICEL_C_R)
                                                     -0.044    52.016    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[23]
  -------------------------------------------------------------------
                         required time                         52.016    
                         arrival time                         -31.566    
  -------------------------------------------------------------------
                         slack                                 20.451    

Slack (MET) :             20.451ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
                            (falling edge-triggered cell BSCANE2 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[24]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Fast Process Corner)
  Requirement:            25.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall@25.000ns)
  Data Path Delay:        6.566ns  (logic 5.147ns (78.394%)  route 1.419ns (21.606%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        2.296ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.296ns = ( 52.296 - 50.000 ) 
    Source Clock Delay      (SCD):    0.000ns = ( 25.000 - 25.000 ) 
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.235ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + DCD
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
    Duty Cycle Distortion   (DCD):    0.200ns
  Clock Net Delay (Destination): 1.059ns (routing 0.587ns, distribution 0.472ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK fall edge)
                                                     25.000    25.000 f  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    25.000 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_RESET)
                                                      5.100    30.100 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/RESET
                         net (fo=79, routed)          1.109    31.209    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_reset
    SLICE_X107Y83        LUT5 (Prop_C5LUT_SLICEM_I0_O)
                                                      0.047    31.256 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1/O
                         net (fo=32, routed)          0.310    31.566    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_1_n_0
    SLICE_X105Y84        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[24]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755    51.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017    51.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.059    52.296    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X105Y84        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[24]/C
                         clock pessimism              0.000    52.296    
                         clock uncertainty           -0.235    52.060    
    SLICE_X105Y84        FDRE (Setup_AFF_SLICEL_C_R)
                                                     -0.044    52.016    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[24]
  -------------------------------------------------------------------
                         required time                         52.016    
                         arrival time                         -31.566    
  -------------------------------------------------------------------
                         slack                                 20.451    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.016ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.157ns  (logic 0.058ns (36.848%)  route 0.099ns (63.152%))
  Logic Levels:           0  
  Clock Path Skew:        0.080ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    7.680ns
    Source Clock Delay      (SCD):    3.180ns
    Clock Pessimism Removal (CPR):    4.420ns
  Clock Net Delay (Source):      1.709ns (routing 0.968ns, distribution 0.741ns)
  Clock Net Delay (Destination): 1.930ns (routing 1.068ns, distribution 0.862ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.709     3.180    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X105Y74        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y74        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     3.238 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp_reg/Q
                         net (fo=5, routed)           0.099     3.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/icn_cmd_en_temp
    SLICE_X106Y74        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.930     7.680    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X106Y74        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en_reg/C
                         clock pessimism             -4.420     3.260    
    SLICE_X106Y74        FDRE (Hold_CFF2_SLICEL_C_D)
                                                      0.062     3.322    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/shift_en_reg
  -------------------------------------------------------------------
                         required time                         -3.322    
                         arrival time                           3.337    
  -------------------------------------------------------------------
                         slack                                  0.016    

Slack (MET) :             0.024ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.077ns  (logic 0.039ns (50.688%)  route 0.038ns (49.312%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.522ns
    Source Clock Delay      (SCD):    2.304ns
    Clock Pessimism Removal (CPR):    4.213ns
  Clock Net Delay (Source):      1.067ns (routing 0.587ns, distribution 0.480ns)
  Clock Net Delay (Destination): 1.211ns (routing 0.658ns, distribution 0.553ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.067     2.304    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X102Y61        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y61        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/Q
                         net (fo=4, routed)           0.038     2.380    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Q[2]
    SLICE_X102Y61        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.211     6.522    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X102Y61        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]/C
                         clock pessimism             -4.213     2.310    
    SLICE_X102Y61        FDCE (Hold_EFF2_SLICEL_C_D)
                                                      0.047     2.357    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.357    
                         arrival time                           2.380    
  -------------------------------------------------------------------
                         slack                                  0.024    

Slack (MET) :             0.029ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/icn_cmd_en_temp_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.138ns  (logic 0.060ns (43.351%)  route 0.078ns (56.649%))
  Logic Levels:           0  
  Clock Path Skew:        0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    7.700ns
    Source Clock Delay      (SCD):    3.182ns
    Clock Pessimism Removal (CPR):    4.470ns
  Clock Net Delay (Source):      1.711ns (routing 0.968ns, distribution 0.743ns)
  Clock Net Delay (Destination): 1.950ns (routing 1.068ns, distribution 0.882ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.711     3.182    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X105Y74        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y74        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.060     3.242 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[1]/Q
                         net (fo=4, routed)           0.078     3.320    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ICN_CMD_EN_I
    SLICE_X105Y72        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/icn_cmd_en_temp_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.950     7.700    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/m_bscan_tck[0]
    SLICE_X105Y72        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/icn_cmd_en_temp_reg/C
                         clock pessimism             -4.470     3.229    
    SLICE_X105Y72        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     3.291    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/icn_cmd_en_temp_reg
  -------------------------------------------------------------------
                         required time                         -3.291    
                         arrival time                           3.320    
  -------------------------------------------------------------------
                         slack                                  0.029    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.084ns  (logic 0.039ns (46.605%)  route 0.045ns (53.396%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.521ns
    Source Clock Delay      (SCD):    2.303ns
    Clock Pessimism Removal (CPR):    4.213ns
  Clock Net Delay (Source):      1.066ns (routing 0.587ns, distribution 0.479ns)
  Clock Net Delay (Destination): 1.210ns (routing 0.658ns, distribution 0.552ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.066     2.303    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y68        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y68        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.342 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[9]/Q
                         net (fo=2, routed)           0.045     2.386    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[9]
    SLICE_X105Y68        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.210     6.521    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y68        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[8]/C
                         clock pessimism             -4.213     2.309    
    SLICE_X105Y68        FDRE (Hold_CFF_SLICEL_C_D)
                                                      0.046     2.355    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[8]
  -------------------------------------------------------------------
                         required time                         -2.355    
                         arrival time                           2.386    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.035ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[0]/D
                            (rising edge-triggered cell FDSE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.088ns  (logic 0.059ns (67.045%)  route 0.029ns (32.955%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.534ns
    Source Clock Delay      (SCD):    2.315ns
    Clock Pessimism Removal (CPR):    4.214ns
  Clock Net Delay (Source):      1.078ns (routing 0.587ns, distribution 0.491ns)
  Clock Net Delay (Destination): 1.223ns (routing 0.658ns, distribution 0.565ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.078     2.315    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y88        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y88        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.354 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[1]/Q
                         net (fo=1, routed)           0.023     2.377    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid__0[1]
    SLICE_X108Y88        LUT2 (Prop_H5LUT_SLICEL_I0_O)
                                                      0.020     2.397 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[0]_i_1/O
                         net (fo=1, routed)           0.006     2.403    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[0]_i_1_n_0
    SLICE_X108Y88        FDSE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.223     6.534    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X108Y88        FDSE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[0]/C
                         clock pessimism             -4.214     2.321    
    SLICE_X108Y88        FDSE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     2.368    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.368    
                         arrival time                           2.403    
  -------------------------------------------------------------------
                         slack                                  0.035    

Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.193ns  (logic 0.059ns (30.506%)  route 0.134ns (69.494%))
  Logic Levels:           0  
  Clock Path Skew:        0.094ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    7.688ns
    Source Clock Delay      (SCD):    3.174ns
    Clock Pessimism Removal (CPR):    4.420ns
  Clock Net Delay (Source):      1.703ns (routing 0.968ns, distribution 0.735ns)
  Clock Net Delay (Destination): 1.938ns (routing 1.068ns, distribution 0.870ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.703     3.174    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X105Y83        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y83        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     3.233 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid_reg[10]/Q
                         net (fo=2, routed)           0.134     3.367    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid[10]
    SLICE_X106Y82        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.938     7.688    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y82        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid_reg[9]/C
                         clock pessimism             -4.420     3.268    
    SLICE_X106Y82        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     3.330    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/temp_curid_reg[9]
  -------------------------------------------------------------------
                         required time                         -3.330    
                         arrival time                           3.367    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.091ns  (logic 0.059ns (64.769%)  route 0.032ns (35.231%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.526ns
    Source Clock Delay      (SCD):    2.307ns
    Clock Pessimism Removal (CPR):    4.214ns
  Clock Net Delay (Source):      1.070ns (routing 0.587ns, distribution 0.483ns)
  Clock Net Delay (Destination): 1.215ns (routing 0.658ns, distribution 0.557ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.070     2.307    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/m_bscan_tck[0]
    SLICE_X105Y61        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y61        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.346 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[2]/Q
                         net (fo=3, routed)           0.026     2.372    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[2]
    SLICE_X105Y61        LUT4 (Prop_G5LUT_SLICEL_I3_O)
                                                      0.020     2.392 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count[3]_i_2/O
                         net (fo=1, routed)           0.006     2.398    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/p_0_in__0[3]
    SLICE_X105Y61        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.215     6.526    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/m_bscan_tck[0]
    SLICE_X105Y61        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[3]/C
                         clock pessimism             -4.214     2.313    
    SLICE_X105Y61        FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.047     2.360    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/shift_bit_count_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.360    
                         arrival time                           2.398    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/shift_en_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.090ns  (logic 0.039ns (43.158%)  route 0.051ns (56.842%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.530ns
    Source Clock Delay      (SCD):    2.312ns
    Clock Pessimism Removal (CPR):    4.213ns
  Clock Net Delay (Source):      1.075ns (routing 0.587ns, distribution 0.488ns)
  Clock Net Delay (Destination): 1.219ns (routing 0.658ns, distribution 0.561ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.075     2.312    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/m_bscan_tck[0]
    SLICE_X106Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y71        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.351 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/icn_cmd_en_temp_reg/Q
                         net (fo=5, routed)           0.051     2.402    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/icn_cmd_en_temp
    SLICE_X106Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/shift_en_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.219     6.530    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/m_bscan_tck[0]
    SLICE_X106Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/shift_en_reg/C
                         clock pessimism             -4.213     2.318    
    SLICE_X106Y71        FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.046     2.364    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD3/shift_en_reg
  -------------------------------------------------------------------
                         required time                         -2.364    
                         arrival time                           2.402    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.040ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.092ns  (logic 0.039ns (42.391%)  route 0.053ns (57.609%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.526ns
    Source Clock Delay      (SCD):    2.306ns
    Clock Pessimism Removal (CPR):    4.215ns
  Clock Net Delay (Source):      1.069ns (routing 0.587ns, distribution 0.482ns)
  Clock Net Delay (Destination): 1.215ns (routing 0.658ns, distribution 0.557ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.069     2.306    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X103Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y69        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     2.345 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[8]/Q
                         net (fo=2, routed)           0.053     2.398    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[8]
    SLICE_X103Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.215     6.526    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X103Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/C
                         clock pessimism             -4.215     2.312    
    SLICE_X103Y69        FDRE (Hold_FFF_SLICEM_C_D)
                                                      0.046     2.358    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]
  -------------------------------------------------------------------
                         required time                         -2.358    
                         arrival time                           2.398    
  -------------------------------------------------------------------
                         slack                                  0.040    

Slack (MET) :             0.041ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.094ns  (logic 0.059ns (62.907%)  route 0.035ns (37.093%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.528ns
    Source Clock Delay      (SCD):    2.310ns
    Clock Pessimism Removal (CPR):    4.213ns
  Clock Net Delay (Source):      1.073ns (routing 0.587ns, distribution 0.486ns)
  Clock Net Delay (Destination): 1.217ns (routing 0.658ns, distribution 0.559ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.073     2.310    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X106Y76        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y76        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.349 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]/Q
                         net (fo=6, routed)           0.029     2.377    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[1]
    SLICE_X106Y76        LUT3 (Prop_H5LUT_SLICEL_I2_O)
                                                      0.020     2.397 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT[2]_i_1/O
                         net (fo=1, routed)           0.006     2.403    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/p_0_in[2]
    SLICE_X106Y76        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.217     6.528    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/m_bscan_tck[0]
    SLICE_X106Y76        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]/C
                         clock pessimism             -4.213     2.316    
    SLICE_X106Y76        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     2.363    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_STAT/iSTAT_CNT_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.363    
                         arrival time                           2.403    
  -------------------------------------------------------------------
                         slack                                  0.041    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
Waveform(ns):       { 0.000 25.000 }
Period(ns):         50.000
Sources:            { dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK }

Check Type        Corner  Lib Pin     Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location      Pin
Min Period        n/a     BUFGCE/I    n/a            1.290         50.000      48.710     BUFGCE_X0Y49  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/I
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
Min Period        n/a     RAMD32/CLK  n/a            1.064         50.000      48.936     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAME/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Slow    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK  n/a            0.532         25.000      24.468     SLICE_X99Y63  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK



---------------------------------------------------------------------------------------------------
From Clock:  default_sysclk_c0_300mhz_clk_p
  To Clock:  default_sysclk_c0_300mhz_clk_p

Setup :            0  Failing Endpoints,  Worst Slack        1.983ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.052ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.500ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.983ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.248ns  (logic 0.181ns (14.503%)  route 1.067ns (85.497%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.093ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.459ns = ( 4.793 - 3.334 ) 
    Source Clock Delay      (SCD):    1.716ns
    Clock Pessimism Removal (CPR):    0.163ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.783ns (routing 0.001ns, distribution 0.782ns)
  Clock Net Delay (Destination): 0.673ns (routing 0.001ns, distribution 0.672ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     0.905    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     0.933 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.783     1.716    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y116        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y116        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     1.796 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/Q
                         net (fo=2, routed)           0.672     2.468    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design
    SLICE_X89Y79         LUT2 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.101     2.569 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_i_1/O
                         net (fo=1, routed)           0.395     2.964    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg0
    SLICE_X89Y77         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.334    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.756 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.796    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.796 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.096    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.120 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.673     4.793    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X89Y77         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
                         clock pessimism              0.163     4.957    
                         clock uncertainty           -0.035     4.921    
    SLICE_X89Y77         FDRE (Setup_AFF2_SLICEM_C_D)
                                                      0.025     4.946    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg
  -------------------------------------------------------------------
                         required time                          4.946    
                         arrival time                          -2.964    
  -------------------------------------------------------------------
                         slack                                  1.983    

Slack (MET) :             2.019ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.205ns  (logic 0.281ns (23.312%)  route 0.924ns (76.688%))
  Logic Levels:           2  (LUT3=1 LUT5=1)
  Clock Path Skew:        -0.099ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.453ns = ( 4.787 - 3.334 ) 
    Source Clock Delay      (SCD):    1.716ns
    Clock Pessimism Removal (CPR):    0.163ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.783ns (routing 0.001ns, distribution 0.782ns)
  Clock Net Delay (Destination): 0.667ns (routing 0.001ns, distribution 0.666ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     0.905    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     0.933 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.783     1.716    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y117        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     1.792 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/Q
                         net (fo=7, routed)           0.336     2.128    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]
    SLICE_X91Y116        LUT3 (Prop_C5LUT_SLICEL_I2_O)
                                                      0.068     2.196 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_2/O
                         net (fo=1, routed)           0.223     2.419    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_2_n_0
    SLICE_X90Y117        LUT5 (Prop_C5LUT_SLICEM_I3_O)
                                                      0.137     2.556 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_1/O
                         net (fo=1, routed)           0.365     2.921    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_i_1_n_0
    SLICE_X86Y118        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.334    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.756 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.796    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.796 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.096    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.120 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.667     4.787    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X86Y118        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg/C
                         clock pessimism              0.163     4.951    
                         clock uncertainty           -0.035     4.915    
    SLICE_X86Y118        FDRE (Setup_AFF_SLICEM_C_D)
                                                      0.025     4.940    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_mmcm_reg
  -------------------------------------------------------------------
                         required time                          4.940    
                         arrival time                          -2.921    
  -------------------------------------------------------------------
                         slack                                  2.019    

Slack (MET) :             2.074ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/R
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.125ns  (logic 0.230ns (20.450%)  route 0.895ns (79.550%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.466ns = ( 4.800 - 3.334 ) 
    Source Clock Delay      (SCD):    1.718ns
    Clock Pessimism Removal (CPR):    0.226ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.785ns (routing 0.001ns, distribution 0.784ns)
  Clock Net Delay (Destination): 0.680ns (routing 0.001ns, distribution 0.679ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     0.905    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     0.933 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.785     1.718    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y117        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     1.798 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/Q
                         net (fo=6, routed)           0.258     2.056    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[0]
    SLICE_X90Y117        LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.051     2.107 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.192     2.299    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X91Y116        LUT5 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.099     2.398 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.445     2.842    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/R
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.334    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.756 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.796    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.796 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.096    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.120 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.680     4.800    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                         clock pessimism              0.226     5.026    
                         clock uncertainty           -0.035     4.991    
    SLICE_X90Y117        FDRE (Setup_EFF_SLICEM_C_R)
                                                     -0.074     4.917    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]
  -------------------------------------------------------------------
                         required time                          4.917    
                         arrival time                          -2.842    
  -------------------------------------------------------------------
                         slack                                  2.074    

Slack (MET) :             2.077ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.118ns  (logic 0.323ns (28.900%)  route 0.795ns (71.100%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.467ns = ( 4.801 - 3.334 ) 
    Source Clock Delay      (SCD):    1.711ns
    Clock Pessimism Removal (CPR):    0.214ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.778ns (routing 0.001ns, distribution 0.777ns)
  Clock Net Delay (Destination): 0.681ns (routing 0.001ns, distribution 0.680ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     0.905    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     0.933 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.778     1.711    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y116        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y116        FDSE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     1.790 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/Q
                         net (fo=5, routed)           0.155     1.945    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]
    SLICE_X90Y117        LUT4 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.145     2.090 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.192     2.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X91Y116        LUT5 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.099     2.380 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.448     2.828    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/R
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.334    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.756 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.796    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.796 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.096    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.120 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.681     4.801    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
                         clock pessimism              0.214     5.015    
                         clock uncertainty           -0.035     4.980    
    SLICE_X90Y117        FDRE (Setup_BFF2_SLICEM_C_R)
                                                     -0.074     4.906    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]
  -------------------------------------------------------------------
                         required time                          4.906    
                         arrival time                          -2.828    
  -------------------------------------------------------------------
                         slack                                  2.077    

Slack (MET) :             2.077ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/R
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.118ns  (logic 0.323ns (28.900%)  route 0.795ns (71.100%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.467ns = ( 4.801 - 3.334 ) 
    Source Clock Delay      (SCD):    1.711ns
    Clock Pessimism Removal (CPR):    0.214ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.778ns (routing 0.001ns, distribution 0.777ns)
  Clock Net Delay (Destination): 0.681ns (routing 0.001ns, distribution 0.680ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     0.905    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     0.933 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.778     1.711    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y116        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y116        FDSE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     1.790 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/Q
                         net (fo=5, routed)           0.155     1.945    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]
    SLICE_X90Y117        LUT4 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.145     2.090 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.192     2.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X91Y116        LUT5 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.099     2.380 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.448     2.828    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/R
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.334    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.756 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.796    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.796 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.096    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.120 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.681     4.801    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                         clock pessimism              0.214     5.015    
                         clock uncertainty           -0.035     4.980    
    SLICE_X90Y117        FDRE (Setup_DFF_SLICEM_C_R)
                                                     -0.074     4.906    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]
  -------------------------------------------------------------------
                         required time                          4.906    
                         arrival time                          -2.828    
  -------------------------------------------------------------------
                         slack                                  2.077    

Slack (MET) :             2.077ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.118ns  (logic 0.323ns (28.900%)  route 0.795ns (71.100%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.467ns = ( 4.801 - 3.334 ) 
    Source Clock Delay      (SCD):    1.711ns
    Clock Pessimism Removal (CPR):    0.214ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.778ns (routing 0.001ns, distribution 0.777ns)
  Clock Net Delay (Destination): 0.681ns (routing 0.001ns, distribution 0.680ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     0.905    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     0.933 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.778     1.711    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y116        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y116        FDSE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     1.790 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/Q
                         net (fo=5, routed)           0.155     1.945    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]
    SLICE_X90Y117        LUT4 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.145     2.090 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.192     2.281    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X91Y116        LUT5 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.099     2.380 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1/O
                         net (fo=4, routed)           0.448     2.828    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_1_n_0
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/R
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.334    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.756 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.796    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.796 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.096    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.120 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.681     4.801    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                         clock pessimism              0.214     5.015    
                         clock uncertainty           -0.035     4.980    
    SLICE_X90Y117        FDRE (Setup_DFF2_SLICEM_C_R)
                                                     -0.074     4.906    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]
  -------------------------------------------------------------------
                         required time                          4.906    
                         arrival time                          -2.828    
  -------------------------------------------------------------------
                         slack                                  2.077    

Slack (MET) :             2.105ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        1.124ns  (logic 0.189ns (16.815%)  route 0.935ns (83.185%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        -0.095ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.457ns = ( 4.791 - 3.334 ) 
    Source Clock Delay      (SCD):    1.716ns
    Clock Pessimism Removal (CPR):    0.163ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.783ns (routing 0.001ns, distribution 0.782ns)
  Clock Net Delay (Destination): 0.671ns (routing 0.001ns, distribution 0.670ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     0.905    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     0.933 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.783     1.716    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y116        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y116        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     1.796 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/Q
                         net (fo=2, routed)           0.672     2.468    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design
    SLICE_X89Y79         LUT3 (Prop_H5LUT_SLICEM_I1_O)
                                                      0.109     2.577 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.263     2.840    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X89Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.334    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.756 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.796    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.796 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.096    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.120 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.671     4.791    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X89Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                         clock pessimism              0.163     4.955    
                         clock uncertainty           -0.035     4.919    
    SLICE_X89Y79         FDRE (Setup_AFF2_SLICEM_C_D)
                                                      0.025     4.944    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg
  -------------------------------------------------------------------
                         required time                          4.944    
                         arrival time                          -2.840    
  -------------------------------------------------------------------
                         slack                                  2.105    

Slack (MET) :             2.374ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.924ns  (logic 0.227ns (24.574%)  route 0.697ns (75.426%))
  Logic Levels:           2  (LUT4=2)
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.466ns = ( 4.800 - 3.334 ) 
    Source Clock Delay      (SCD):    1.718ns
    Clock Pessimism Removal (CPR):    0.226ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.785ns (routing 0.001ns, distribution 0.784ns)
  Clock Net Delay (Destination): 0.680ns (routing 0.001ns, distribution 0.679ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     0.905    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     0.933 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.785     1.718    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y117        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     1.798 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/Q
                         net (fo=6, routed)           0.258     2.056    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[0]
    SLICE_X90Y117        LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.051     2.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.143     2.249    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X91Y116        LUT4 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     2.345 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_2/O
                         net (fo=1, routed)           0.296     2.641    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[6]
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.334    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.756 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.796    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.796 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.096    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.120 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.680     4.800    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
                         clock pessimism              0.226     5.026    
                         clock uncertainty           -0.035     4.991    
    SLICE_X90Y117        FDRE (Setup_EFF_SLICEM_C_D)
                                                      0.025     5.016    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]
  -------------------------------------------------------------------
                         required time                          5.016    
                         arrival time                          -2.641    
  -------------------------------------------------------------------
                         slack                                  2.374    

Slack (MET) :             2.500ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.782ns  (logic 0.204ns (26.077%)  route 0.578ns (73.923%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.041ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.463ns = ( 4.797 - 3.334 ) 
    Source Clock Delay      (SCD):    1.718ns
    Clock Pessimism Removal (CPR):    0.214ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.785ns (routing 0.001ns, distribution 0.784ns)
  Clock Net Delay (Destination): 0.677ns (routing 0.001ns, distribution 0.676ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     0.905    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     0.933 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.785     1.718    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y117        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     1.798 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/Q
                         net (fo=6, routed)           0.529     2.327    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[0]
    SLICE_X91Y116        LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.124     2.451 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1/O
                         net (fo=1, routed)           0.049     2.500    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1_n_0
    SLICE_X91Y116        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.334    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.756 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.796    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.796 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.096    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.120 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.677     4.797    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y116        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                         clock pessimism              0.214     5.011    
                         clock uncertainty           -0.035     4.975    
    SLICE_X91Y116        FDSE (Setup_BFF_SLICEL_C_D)
                                                      0.025     5.000    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]
  -------------------------------------------------------------------
                         required time                          5.000    
                         arrival time                          -2.500    
  -------------------------------------------------------------------
                         slack                                  2.500    

Slack (MET) :             2.580ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.334ns  (default_sysclk_c0_300mhz_clk_p rise@3.334ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.705ns  (logic 0.240ns (34.052%)  route 0.465ns (65.948%))
  Logic Levels:           2  (LUT4=2)
  Clock Path Skew:        -0.039ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.465ns = ( 4.799 - 3.334 ) 
    Source Clock Delay      (SCD):    1.718ns
    Clock Pessimism Removal (CPR):    0.214ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.785ns (routing 0.001ns, distribution 0.784ns)
  Clock Net Delay (Destination): 0.679ns (routing 0.001ns, distribution 0.678ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     0.905    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     0.933 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.785     1.718    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y117        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     1.798 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/Q
                         net (fo=6, routed)           0.258     2.056    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[0]
    SLICE_X90Y117        LUT4 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.051     2.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3/O
                         net (fo=6, routed)           0.192     2.299    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[6]_i_3_n_0
    SLICE_X91Y116        LUT4 (Prop_H5LUT_SLICEL_I3_O)
                                                      0.109     2.408 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_i_1/O
                         net (fo=1, routed)           0.015     2.423    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_i_1_n_0
    SLICE_X91Y116        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      3.334     3.334 r  
    AR20                                              0.000     3.334 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.334    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.756 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.796    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.796 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     4.096    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.120 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.679     4.799    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y116        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
                         clock pessimism              0.214     5.013    
                         clock uncertainty           -0.035     4.977    
    SLICE_X91Y116        FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025     5.002    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg
  -------------------------------------------------------------------
                         required time                          5.002    
                         arrival time                          -2.423    
  -------------------------------------------------------------------
                         slack                                  2.580    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.052ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.104ns  (logic 0.062ns (59.798%)  route 0.042ns (40.202%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.178ns
    Source Clock Delay      (SCD):    0.965ns
    Clock Pessimism Removal (CPR):    0.207ns
  Clock Net Delay (Source):      0.437ns (routing 0.000ns, distribution 0.437ns)
  Clock Net Delay (Destination): 0.498ns (routing 0.001ns, distribution 0.497ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.511    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.528 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.437     0.965    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y116        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y116        FDSE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.004 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/Q
                         net (fo=5, routed)           0.027     1.031    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]
    SLICE_X91Y116        LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.023     1.054 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1/O
                         net (fo=1, routed)           0.015     1.069    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[1]_i_1_n_0
    SLICE_X91Y116        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.498     1.178    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y116        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
                         clock pessimism             -0.207     0.971    
    SLICE_X91Y116        FDSE (Hold_BFF_SLICEL_C_D)
                                                      0.046     1.017    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.017    
                         arrival time                           1.069    
  -------------------------------------------------------------------
                         slack                                  0.052    

Slack (MET) :             0.052ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/D
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.105ns  (logic 0.072ns (68.771%)  route 0.033ns (31.229%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.178ns
    Source Clock Delay      (SCD):    0.965ns
    Clock Pessimism Removal (CPR):    0.207ns
  Clock Net Delay (Source):      0.437ns (routing 0.000ns, distribution 0.437ns)
  Clock Net Delay (Destination): 0.498ns (routing 0.001ns, distribution 0.497ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.511    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.528 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.437     0.965    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y116        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y116        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.004 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.027     1.031    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X91Y116        LUT4 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.033     1.064 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[5]_i_1/O
                         net (fo=1, routed)           0.006     1.070    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[5]_i_1_n_0
    SLICE_X91Y116        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.498     1.178    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y116        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
                         clock pessimism             -0.207     0.971    
    SLICE_X91Y116        FDSE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.018    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]
  -------------------------------------------------------------------
                         required time                         -1.018    
                         arrival time                           1.070    
  -------------------------------------------------------------------
                         slack                                  0.052    

Slack (MET) :             0.061ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.114ns  (logic 0.076ns (66.657%)  route 0.038ns (33.343%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.183ns
    Source Clock Delay      (SCD):    0.968ns
    Clock Pessimism Removal (CPR):    0.209ns
  Clock Net Delay (Source):      0.440ns (routing 0.000ns, distribution 0.440ns)
  Clock Net Delay (Destination): 0.503ns (routing 0.001ns, distribution 0.502ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.511    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.528 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.440     0.968    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y117        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.007 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.029     1.036    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X90Y117        LUT4 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.037     1.073 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[3]_i_1/O
                         net (fo=1, routed)           0.009     1.082    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[3]
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.503     1.183    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
                         clock pessimism             -0.209     0.974    
    SLICE_X90Y117        FDRE (Hold_DFF2_SLICEM_C_D)
                                                      0.047     1.021    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.021    
                         arrival time                           1.082    
  -------------------------------------------------------------------
                         slack                                  0.061    

Slack (MET) :             0.065ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/D
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.117ns  (logic 0.074ns (63.413%)  route 0.043ns (36.587%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.178ns
    Source Clock Delay      (SCD):    0.965ns
    Clock Pessimism Removal (CPR):    0.207ns
  Clock Net Delay (Source):      0.437ns (routing 0.000ns, distribution 0.437ns)
  Clock Net Delay (Destination): 0.498ns (routing 0.001ns, distribution 0.497ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.511    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.528 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.437     0.965    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y116        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y116        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.004 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.027     1.031    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X91Y116        LUT4 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     1.066 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]_i_1/O
                         net (fo=1, routed)           0.016     1.082    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]_i_1_n_0
    SLICE_X91Y116        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.498     1.178    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y116        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                         clock pessimism             -0.207     0.971    
    SLICE_X91Y116        FDSE (Hold_DFF_SLICEL_C_D)
                                                      0.046     1.017    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.017    
                         arrival time                           1.082    
  -------------------------------------------------------------------
                         slack                                  0.065    

Slack (MET) :             0.068ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.121ns  (logic 0.040ns (33.058%)  route 0.081ns (66.942%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.174ns
    Source Clock Delay      (SCD):    0.961ns
    Clock Pessimism Removal (CPR):    0.206ns
  Clock Net Delay (Source):      0.433ns (routing 0.000ns, distribution 0.433ns)
  Clock Net Delay (Destination): 0.494ns (routing 0.001ns, distribution 0.493ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.511    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.528 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.433     0.961    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y119        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y119        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.001 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[0]/Q
                         net (fo=1, routed)           0.081     1.082    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[0]
    SLICE_X91Y119        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.494     1.174    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y119        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/C
                         clock pessimism             -0.206     0.967    
    SLICE_X91Y119        FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     1.014    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.014    
                         arrival time                           1.082    
  -------------------------------------------------------------------
                         slack                                  0.068    

Slack (MET) :             0.070ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.123ns  (logic 0.040ns (32.520%)  route 0.083ns (67.480%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.174ns
    Source Clock Delay      (SCD):    0.961ns
    Clock Pessimism Removal (CPR):    0.206ns
  Clock Net Delay (Source):      0.433ns (routing 0.000ns, distribution 0.433ns)
  Clock Net Delay (Destination): 0.494ns (routing 0.001ns, distribution 0.493ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.511    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.528 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.433     0.961    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y119        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y119        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.001 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/Q
                         net (fo=1, routed)           0.083     1.084    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[2]
    SLICE_X91Y119        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.494     1.174    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y119        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]/C
                         clock pessimism             -0.206     0.967    
    SLICE_X91Y119        FDRE (Hold_DFF2_SLICEL_C_D)
                                                      0.047     1.014    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.014    
                         arrival time                           1.084    
  -------------------------------------------------------------------
                         slack                                  0.070    

Slack (MET) :             0.077ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.129ns  (logic 0.074ns (57.357%)  route 0.055ns (42.643%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.183ns
    Source Clock Delay      (SCD):    0.968ns
    Clock Pessimism Removal (CPR):    0.209ns
  Clock Net Delay (Source):      0.440ns (routing 0.000ns, distribution 0.440ns)
  Clock Net Delay (Destination): 0.503ns (routing 0.001ns, distribution 0.502ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.511    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.528 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.440     0.968    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y117        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.007 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/Q
                         net (fo=4, routed)           0.029     1.036    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]
    SLICE_X90Y117        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.035     1.071 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[2]_i_1/O
                         net (fo=1, routed)           0.026     1.097    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst0[2]
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.503     1.183    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X90Y117        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
                         clock pessimism             -0.209     0.974    
    SLICE_X90Y117        FDRE (Hold_DFF_SLICEM_C_D)
                                                      0.046     1.020    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.020    
                         arrival time                           1.097    
  -------------------------------------------------------------------
                         slack                                  0.077    

Slack (MET) :             0.099ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
                            (rising edge-triggered cell FDSE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.161ns  (logic 0.097ns (60.108%)  route 0.064ns (39.892%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.182ns
    Source Clock Delay      (SCD):    0.965ns
    Clock Pessimism Removal (CPR):    0.201ns
  Clock Net Delay (Source):      0.437ns (routing 0.000ns, distribution 0.437ns)
  Clock Net Delay (Destination): 0.502ns (routing 0.001ns, distribution 0.501ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.511    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.528 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.437     0.965    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y116        FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y116        FDSE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.004 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/Q
                         net (fo=7, routed)           0.058     1.062    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst[4]
    SLICE_X91Y116        LUT4 (Prop_H5LUT_SLICEL_I1_O)
                                                      0.058     1.120 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_i_1/O
                         net (fo=1, routed)           0.006     1.126    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_i_1_n_0
    SLICE_X91Y116        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.502     1.182    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y116        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
                         clock pessimism             -0.201     0.981    
    SLICE_X91Y116        FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     1.028    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg
  -------------------------------------------------------------------
                         required time                         -1.028    
                         arrival time                           1.126    
  -------------------------------------------------------------------
                         slack                                  0.099    

Slack (MET) :             0.102ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.155ns  (logic 0.040ns (25.806%)  route 0.115ns (74.194%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.174ns
    Source Clock Delay      (SCD):    0.961ns
    Clock Pessimism Removal (CPR):    0.206ns
  Clock Net Delay (Source):      0.433ns (routing 0.000ns, distribution 0.433ns)
  Clock Net Delay (Destination): 0.494ns (routing 0.001ns, distribution 0.493ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.511    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.528 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.433     0.961    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y119        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y119        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     1.001 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[1]/Q
                         net (fo=1, routed)           0.115     1.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r[1]
    SLICE_X91Y119        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.494     1.174    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y119        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]/C
                         clock pessimism             -0.206     0.967    
    SLICE_X91Y119        FDRE (Hold_CFF2_SLICEL_C_D)
                                                      0.047     1.014    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_sync_r_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.014    
                         arrival time                           1.116    
  -------------------------------------------------------------------
                         slack                                  0.102    

Slack (MET) :             0.137ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/D
                            (rising edge-triggered cell FDPE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             default_sysclk_c0_300mhz_clk_p
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (default_sysclk_c0_300mhz_clk_p rise@0.000ns - default_sysclk_c0_300mhz_clk_p rise@0.000ns)
  Data Path Delay:        0.190ns  (logic 0.040ns (21.053%)  route 0.150ns (78.947%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.174ns
    Source Clock Delay      (SCD):    0.961ns
    Clock Pessimism Removal (CPR):    0.206ns
  Clock Net Delay (Source):      0.433ns (routing 0.000ns, distribution 0.433ns)
  Clock Net Delay (Destination): 0.494ns (routing 0.001ns, distribution 0.493ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.511    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.528 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.433     0.961    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y118        FDPE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y118        FDPE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.001 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/Q
                         net (fo=1, routed)           0.150     1.151    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async[0]
    SLICE_X91Y118        FDPE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.494     1.174    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y118        FDPE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C
                         clock pessimism             -0.206     0.967    
    SLICE_X91Y118        FDPE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     1.014    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.014    
                         arrival time                           1.151    
  -------------------------------------------------------------------
                         slack                                  0.137    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         default_sysclk_c0_300mhz_clk_p
Waveform(ns):       { 0.000 1.667 }
Period(ns):         3.334
Sources:            { default_sysclk_c0_300mhz_clk_p }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFGCE/I           n/a            1.290         3.334       2.044      BUFGCE_X0Y46   d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/I
Min Period        n/a     MMCME4_ADV/CLKIN1  n/a            1.071         3.334       2.263      MMCM_X0Y1      d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X91Y116  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X91Y116  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[4]/C
Min Period        n/a     FDSE/C             n/a            0.550         3.334       2.784      SLICE_X91Y116  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[5]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[6]/C
Min Period        n/a     FDRE/C             n/a            0.550         3.334       2.784      SLICE_X91Y116  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/input_rst_design_reg/C
Max Period        n/a     MMCME4_ADV/CLKIN1  n/a            100.000       3.334       96.666     MMCM_X0Y1      d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Slow    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y1      d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Fast    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y1      d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
Low Pulse Width   Slow    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X91Y116  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Low Pulse Width   Fast    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X91Y116  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
Low Pulse Width   Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
Low Pulse Width   Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
High Pulse Width  Slow    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y1      d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
High Pulse Width  Fast    MMCME4_ADV/CLKIN1  n/a            1.167         1.667       0.500      MMCM_X0Y1      d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKIN1
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[0]/C
High Pulse Width  Slow    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X91Y116  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
High Pulse Width  Fast    FDSE/C             n/a            0.275         1.667       1.392      SLICE_X91Y116  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[1]/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[2]/C
High Pulse Width  Slow    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C
High Pulse Width  Fast    FDRE/C             n/a            0.275         1.667       1.392      SLICE_X90Y117  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/counter_input_rst_reg[3]/C



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        0.106ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.012ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.106ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.788ns  (logic 0.902ns (32.356%)  route 1.886ns (67.644%))
  Logic Levels:           8  (CARRY8=1 LUT3=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.070ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.927ns = ( 5.928 - 3.001 ) 
    Source Clock Delay      (SCD):    2.521ns
    Clock Pessimism Removal (CPR):    -0.476ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.404ns (routing 0.415ns, distribution 0.989ns)
  Clock Net Delay (Destination): 1.247ns (routing 0.379ns, distribution 0.868ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.404     2.521    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X85Y93         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y93         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.600 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.266     2.865    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[39]_0[0]
    SLICE_X83Y94         LUT6 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.090     2.955 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_21__0/O
                         net (fo=1, routed)           0.280     3.235    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_21__0_n_0
    SLICE_X86Y95         LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     3.360 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_6__0/O
                         net (fo=1, routed)           0.013     3.373    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_6__0_n_0
    SLICE_X86Y95         CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[5])
                                                      0.201     3.574 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.254     3.829    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X89Y95         LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.148     3.977 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0/O
                         net (fo=1, routed)           0.042     4.019    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0_n_0
    SLICE_X89Y95         LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.039     4.058 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__2/O
                         net (fo=5, routed)           0.091     4.149    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__2_n_0
    SLICE_X89Y95         LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.052     4.201 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__2/O
                         net (fo=77, routed)          0.316     4.517    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__2_n_0
    SLICE_X88Y95         LUT3 (Prop_E5LUT_SLICEL_I1_O)
                                                      0.070     4.587 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[47]_i_5/O
                         net (fo=31, routed)          0.558     5.144    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[47]_i_5_n_0
    SLICE_X82Y90         LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     5.242 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[25]_i_1__2/O
                         net (fo=1, routed)           0.066     5.308    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[25]_i_1__2_n_0
    SLICE_X82Y90         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.247     5.928    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X82Y90         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[25]/C
                         clock pessimism             -0.476     5.451    
                         clock uncertainty           -0.062     5.389    
    SLICE_X82Y90         FDRE (Setup_CFF_SLICEM_C_D)
                                                      0.025     5.414    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[25]
  -------------------------------------------------------------------
                         required time                          5.414    
                         arrival time                          -5.308    
  -------------------------------------------------------------------
                         slack                                  0.106    

Slack (MET) :             0.175ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[37]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.725ns  (logic 0.902ns (33.097%)  route 1.823ns (66.903%))
  Logic Levels:           8  (CARRY8=1 LUT3=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.063ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.934ns = ( 5.935 - 3.001 ) 
    Source Clock Delay      (SCD):    2.521ns
    Clock Pessimism Removal (CPR):    -0.476ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.404ns (routing 0.415ns, distribution 0.989ns)
  Clock Net Delay (Destination): 1.254ns (routing 0.379ns, distribution 0.875ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.404     2.521    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X85Y93         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y93         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.600 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.266     2.865    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[39]_0[0]
    SLICE_X83Y94         LUT6 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.090     2.955 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_21__0/O
                         net (fo=1, routed)           0.280     3.235    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_21__0_n_0
    SLICE_X86Y95         LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     3.360 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_6__0/O
                         net (fo=1, routed)           0.013     3.373    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_6__0_n_0
    SLICE_X86Y95         CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[5])
                                                      0.201     3.574 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.254     3.829    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X89Y95         LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.148     3.977 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0/O
                         net (fo=1, routed)           0.042     4.019    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0_n_0
    SLICE_X89Y95         LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.039     4.058 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__2/O
                         net (fo=5, routed)           0.091     4.149    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__2_n_0
    SLICE_X89Y95         LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.052     4.201 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__2/O
                         net (fo=77, routed)          0.316     4.517    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__2_n_0
    SLICE_X88Y95         LUT3 (Prop_E5LUT_SLICEL_I1_O)
                                                      0.070     4.587 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[47]_i_5/O
                         net (fo=31, routed)          0.495     5.082    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[47]_i_5_n_0
    SLICE_X83Y90         LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     5.180 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[37]_i_1__2/O
                         net (fo=1, routed)           0.066     5.246    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[37]_i_1__2_n_0
    SLICE_X83Y90         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[37]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.254     5.935    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X83Y90         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[37]/C
                         clock pessimism             -0.476     5.459    
                         clock uncertainty           -0.062     5.396    
    SLICE_X83Y90         FDRE (Setup_CFF_SLICEM_C_D)
                                                      0.025     5.421    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[37]
  -------------------------------------------------------------------
                         required time                          5.421    
                         arrival time                          -5.246    
  -------------------------------------------------------------------
                         slack                                  0.175    

Slack (MET) :             0.179ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.720ns  (logic 0.927ns (34.081%)  route 1.793ns (65.919%))
  Logic Levels:           8  (CARRY8=1 LUT3=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.064ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.933ns = ( 5.934 - 3.001 ) 
    Source Clock Delay      (SCD):    2.521ns
    Clock Pessimism Removal (CPR):    -0.476ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.404ns (routing 0.415ns, distribution 0.989ns)
  Clock Net Delay (Destination): 1.253ns (routing 0.379ns, distribution 0.874ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.404     2.521    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X85Y93         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y93         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.600 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.266     2.865    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[39]_0[0]
    SLICE_X83Y94         LUT6 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.090     2.955 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_21__0/O
                         net (fo=1, routed)           0.280     3.235    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_21__0_n_0
    SLICE_X86Y95         LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     3.360 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_6__0/O
                         net (fo=1, routed)           0.013     3.373    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_6__0_n_0
    SLICE_X86Y95         CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[5])
                                                      0.201     3.574 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.254     3.829    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X89Y95         LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.148     3.977 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0/O
                         net (fo=1, routed)           0.042     4.019    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0_n_0
    SLICE_X89Y95         LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.039     4.058 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__2/O
                         net (fo=5, routed)           0.091     4.149    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__2_n_0
    SLICE_X89Y95         LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.052     4.201 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__2/O
                         net (fo=77, routed)          0.316     4.517    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__2_n_0
    SLICE_X88Y95         LUT3 (Prop_E5LUT_SLICEL_I1_O)
                                                      0.070     4.587 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[47]_i_5/O
                         net (fo=31, routed)          0.481     5.068    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[47]_i_5_n_0
    SLICE_X81Y97         LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     5.191 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[15]_i_1__2/O
                         net (fo=1, routed)           0.050     5.241    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[15]_i_1__2_n_0
    SLICE_X81Y97         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.253     5.934    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X81Y97         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[15]/C
                         clock pessimism             -0.476     5.457    
                         clock uncertainty           -0.062     5.395    
    SLICE_X81Y97         FDRE (Setup_CFF_SLICEL_C_D)
                                                      0.025     5.420    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[15]
  -------------------------------------------------------------------
                         required time                          5.420    
                         arrival time                          -5.241    
  -------------------------------------------------------------------
                         slack                                  0.179    

Slack (MET) :             0.186ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[26]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.720ns  (logic 0.952ns (35.003%)  route 1.768ns (64.997%))
  Logic Levels:           8  (CARRY8=1 LUT3=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.058ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.939ns = ( 5.940 - 3.001 ) 
    Source Clock Delay      (SCD):    2.521ns
    Clock Pessimism Removal (CPR):    -0.476ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.404ns (routing 0.415ns, distribution 0.989ns)
  Clock Net Delay (Destination): 1.259ns (routing 0.379ns, distribution 0.880ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.404     2.521    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X85Y93         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y93         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.600 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.266     2.865    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[39]_0[0]
    SLICE_X83Y94         LUT6 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.090     2.955 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_21__0/O
                         net (fo=1, routed)           0.280     3.235    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_21__0_n_0
    SLICE_X86Y95         LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     3.360 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_6__0/O
                         net (fo=1, routed)           0.013     3.373    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_6__0_n_0
    SLICE_X86Y95         CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[5])
                                                      0.201     3.574 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.254     3.829    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X89Y95         LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.148     3.977 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0/O
                         net (fo=1, routed)           0.042     4.019    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0_n_0
    SLICE_X89Y95         LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.039     4.058 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__2/O
                         net (fo=5, routed)           0.091     4.149    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__2_n_0
    SLICE_X89Y95         LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.052     4.201 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__2/O
                         net (fo=77, routed)          0.171     4.371    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__2_n_0
    SLICE_X88Y95         LUT3 (Prop_F5LUT_SLICEL_I1_O)
                                                      0.167     4.538 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[47]_i_2__1/O
                         net (fo=31, routed)          0.585     5.123    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[47]_i_2__1_n_0
    SLICE_X82Y100        LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.051     5.174 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[26]_i_1__2/O
                         net (fo=1, routed)           0.066     5.240    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[26]_i_1__2_n_0
    SLICE_X82Y100        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[26]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.259     5.940    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X82Y100        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[26]/C
                         clock pessimism             -0.476     5.463    
                         clock uncertainty           -0.062     5.401    
    SLICE_X82Y100        FDRE (Setup_CFF_SLICEM_C_D)
                                                      0.025     5.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[26]
  -------------------------------------------------------------------
                         required time                          5.426    
                         arrival time                          -5.240    
  -------------------------------------------------------------------
                         slack                                  0.186    

Slack (MET) :             0.206ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_reg[32]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.713ns  (logic 0.902ns (33.249%)  route 1.811ns (66.751%))
  Logic Levels:           8  (CARRY8=1 LUT3=1 LUT4=1 LUT6=5)
  Clock Path Skew:        -0.045ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.950ns = ( 5.951 - 3.001 ) 
    Source Clock Delay      (SCD):    2.519ns
    Clock Pessimism Removal (CPR):    -0.476ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.402ns (routing 0.415ns, distribution 0.987ns)
  Clock Net Delay (Destination): 1.270ns (routing 0.379ns, distribution 0.891ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.402     2.519    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/cmdGroupP_reg[1]_1
    SLICE_X93Y104        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y104        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     2.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=52, routed)          0.378     2.973    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/Q[0]
    SLICE_X95Y96         LUT6 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.124     3.097 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/i__carry_i_18/O
                         net (fo=1, routed)           0.277     3.374    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/i__carry_i_18_n_0
    SLICE_X92Y103        LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.051     3.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/i__carry_i_5/O
                         net (fo=1, routed)           0.009     3.434    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/i__carry_i_5_n_0
    SLICE_X92Y103        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[5])
                                                      0.195     3.629 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.188     3.817    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/issue_cas3215_in
    SLICE_X92Y106        LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.035     3.852 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/FSM_sequential_grSt[2]_i_14/O
                         net (fo=2, routed)           0.049     3.901    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/FSM_sequential_grSt[2]_i_14_n_0
    SLICE_X92Y106        LUT4 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.090     3.991 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2/O
                         net (fo=3, routed)           0.111     4.102    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2_n_0
    SLICE_X92Y105        LUT6 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.051     4.153 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/cas_fifo_wptr[1]_i_2/O
                         net (fo=79, routed)          0.255     4.408    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/cas_fifo_wptr[1]_i_2_n_0
    SLICE_X91Y104        LUT3 (Prop_G5LUT_SLICEL_I1_O)
                                                      0.135     4.543 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output[48]_i_2/O
                         net (fo=32, routed)          0.472     5.015    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output[48]_i_2_n_0
    SLICE_X83Y105        LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.145     5.160 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output[32]_i_1/O
                         net (fo=1, routed)           0.072     5.232    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_nxt[32]
    SLICE_X83Y105        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_reg[32]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.270     5.951    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/cmdGroupP_reg[1]_1
    SLICE_X83Y105        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_reg[32]/C
                         clock pessimism             -0.476     5.475    
                         clock uncertainty           -0.062     5.412    
    SLICE_X83Y105        FDRE (Setup_DFF_SLICEM_C_D)
                                                      0.025     5.437    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_reg[32]
  -------------------------------------------------------------------
                         required time                          5.437    
                         arrival time                          -5.232    
  -------------------------------------------------------------------
                         slack                                  0.206    

Slack (MET) :             0.209ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.709ns  (logic 0.840ns (31.011%)  route 1.869ns (68.989%))
  Logic Levels:           8  (CARRY8=1 LUT3=1 LUT4=1 LUT6=5)
  Clock Path Skew:        -0.046ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.949ns = ( 5.950 - 3.001 ) 
    Source Clock Delay      (SCD):    2.519ns
    Clock Pessimism Removal (CPR):    -0.476ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.402ns (routing 0.415ns, distribution 0.987ns)
  Clock Net Delay (Destination): 1.269ns (routing 0.379ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.402     2.519    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/cmdGroupP_reg[1]_1
    SLICE_X93Y104        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y104        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     2.595 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=52, routed)          0.378     2.973    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/Q[0]
    SLICE_X95Y96         LUT6 (Prop_A6LUT_SLICEL_I3_O)
                                                      0.124     3.097 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/i__carry_i_18/O
                         net (fo=1, routed)           0.277     3.374    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/i__carry_i_18_n_0
    SLICE_X92Y103        LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.051     3.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/i__carry_i_5/O
                         net (fo=1, routed)           0.009     3.434    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/i__carry_i_5_n_0
    SLICE_X92Y103        CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[5])
                                                      0.195     3.629 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.188     3.817    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/issue_cas3215_in
    SLICE_X92Y106        LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.035     3.852 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/FSM_sequential_grSt[2]_i_14/O
                         net (fo=2, routed)           0.049     3.901    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/FSM_sequential_grSt[2]_i_14_n_0
    SLICE_X92Y106        LUT4 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.090     3.991 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2/O
                         net (fo=3, routed)           0.111     4.102    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2_n_0
    SLICE_X92Y105        LUT6 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.051     4.153 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/cas_fifo_wptr[1]_i_2/O
                         net (fo=79, routed)          0.305     4.458    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/cas_fifo_wptr[1]_i_2_n_0
    SLICE_X91Y103        LUT3 (Prop_C5LUT_SLICEL_I0_O)
                                                      0.068     4.526 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output[48]_i_5/O
                         net (fo=32, routed)          0.500     5.026    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output[48]_i_5_n_0
    SLICE_X84Y106        LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     5.176 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output[24]_i_1/O
                         net (fo=1, routed)           0.051     5.227    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_nxt[24]
    SLICE_X84Y106        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.269     5.950    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/cmdGroupP_reg[1]_1
    SLICE_X84Y106        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_reg[24]/C
                         clock pessimism             -0.476     5.474    
                         clock uncertainty           -0.062     5.411    
    SLICE_X84Y106        FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.025     5.436    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[0].u_ddr_mc_group/txn_fifo_output_reg[24]
  -------------------------------------------------------------------
                         required time                          5.436    
                         arrival time                          -5.227    
  -------------------------------------------------------------------
                         slack                                  0.209    

Slack (MET) :             0.218ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.688ns  (logic 0.900ns (33.483%)  route 1.788ns (66.517%))
  Logic Levels:           8  (CARRY8=1 LUT3=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.057ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.940ns = ( 5.940 - 3.001 ) 
    Source Clock Delay      (SCD):    2.521ns
    Clock Pessimism Removal (CPR):    -0.476ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.404ns (routing 0.415ns, distribution 0.989ns)
  Clock Net Delay (Destination): 1.259ns (routing 0.379ns, distribution 0.880ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.404     2.521    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X85Y93         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y93         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.600 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.266     2.865    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[39]_0[0]
    SLICE_X83Y94         LUT6 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.090     2.955 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_21__0/O
                         net (fo=1, routed)           0.280     3.235    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_21__0_n_0
    SLICE_X86Y95         LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     3.360 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_6__0/O
                         net (fo=1, routed)           0.013     3.373    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_6__0_n_0
    SLICE_X86Y95         CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[5])
                                                      0.201     3.574 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.254     3.829    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X89Y95         LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.148     3.977 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0/O
                         net (fo=1, routed)           0.042     4.019    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0_n_0
    SLICE_X89Y95         LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.039     4.058 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__2/O
                         net (fo=5, routed)           0.091     4.149    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__2_n_0
    SLICE_X89Y95         LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.052     4.201 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__2/O
                         net (fo=77, routed)          0.316     4.517    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__2_n_0
    SLICE_X88Y95         LUT3 (Prop_E5LUT_SLICEL_I1_O)
                                                      0.070     4.587 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[47]_i_5/O
                         net (fo=31, routed)          0.476     5.063    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[47]_i_5_n_0
    SLICE_X81Y98         LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     5.159 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[11]_i_1__2/O
                         net (fo=1, routed)           0.050     5.209    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[11]_i_1__2_n_0
    SLICE_X81Y98         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.259     5.940    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X81Y98         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[11]/C
                         clock pessimism             -0.476     5.464    
                         clock uncertainty           -0.062     5.402    
    SLICE_X81Y98         FDRE (Setup_CFF_SLICEL_C_D)
                                                      0.025     5.427    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[11]
  -------------------------------------------------------------------
                         required time                          5.427    
                         arrival time                          -5.209    
  -------------------------------------------------------------------
                         slack                                  0.218    

Slack (MET) :             0.219ns  (required time - arrival time)
  Source:                 d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_w_cmd_fifo.w_cmd_fifo/gen_pipelined.state_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.688ns  (logic 0.497ns (18.489%)  route 2.191ns (81.511%))
  Logic Levels:           5  (LUT2=1 LUT3=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.056ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.085ns = ( 6.086 - 3.001 ) 
    Source Clock Delay      (SCD):    2.673ns
    Clock Pessimism Removal (CPR):    -0.469ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.556ns (routing 0.415ns, distribution 1.141ns)
  Clock Net Delay (Destination): 1.405ns (routing 0.379ns, distribution 1.026ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.556     2.673    d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_w_cmd_fifo.w_cmd_fifo/aclk
    SLICE_X76Y78         FDRE                                         r  d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_w_cmd_fifo.w_cmd_fifo/gen_pipelined.state_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X76Y78         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.751 f  d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_w_cmd_fifo.w_cmd_fifo/gen_pipelined.state_reg[2]/Q
                         net (fo=10, routed)          0.649     3.400    d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/Q[0]
    SLICE_X90Y76         LUT2 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.088     3.488 f  d_1_i/axi_smc_1/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/s_axi_awready_INST_0/O
                         net (fo=12, routed)          0.943     4.431    d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/m_sc_recv[0]
    SLICE_X63Y81         LUT3 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.111     4.542 f  d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/gen_mem_rep[0].inst_xpm_memory_i_1/O
                         net (fo=53, routed)          0.261     4.803    d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/rd_addrb_incr
    SLICE_X64Y81         LUT5 (Prop_A6LUT_SLICEL_I1_O)
                                                      0.035     4.838 r  d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_rd.fifo_empty_r_i_10__0/O
                         net (fo=1, routed)           0.134     4.972    d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.full_r_reg_inv_2
    SLICE_X65Y81         LUT6 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.035     5.007 r  d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_7__0/O
                         net (fo=2, routed)           0.152     5.160    d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_7__0_n_0
    SLICE_X65Y79         LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.150     5.310 r  d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.full_r_inv_i_1/O
                         net (fo=1, routed)           0.051     5.361    d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r0
    SLICE_X65Y79         FDRE                                         r  d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.405     6.086    d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/s_sc_aclk
    SLICE_X65Y79         FDRE                                         r  d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv/C
                         clock pessimism             -0.469     5.617    
                         clock uncertainty           -0.062     5.555    
    SLICE_X65Y79         FDRE (Setup_HFF_SLICEL_C_D)
                                                      0.025     5.580    d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv
  -------------------------------------------------------------------
                         required time                          5.580    
                         arrival time                          -5.361    
  -------------------------------------------------------------------
                         slack                                  0.219    

Slack (MET) :             0.221ns  (required time - arrival time)
  Source:                 d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/m_vector_i_reg[1132]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/gen_pipelined.mesg_reg_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.569ns  (logic 0.473ns (18.415%)  route 2.096ns (81.585%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        -0.174ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.188ns = ( 6.189 - 3.001 ) 
    Source Clock Delay      (SCD):    2.908ns
    Clock Pessimism Removal (CPR):    -0.454ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.791ns (routing 0.415ns, distribution 1.376ns)
  Clock Net Delay (Destination): 1.508ns (routing 0.379ns, distribution 1.129ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.791     2.908    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/aclk
    SLICE_X30Y76         FDRE                                         r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/m_vector_i_reg[1132]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y76         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.986 r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/m_vector_i_reg[1132]/Q
                         net (fo=17, routed)          0.567     3.553    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/gen_srls[3].srl_nx1/s_axi_awlen[4]
    SLICE_X37Y84         LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.124     3.677 r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/gen_srls[3].srl_nx1/skid_buffer[1128]_i_3/O
                         net (fo=2, routed)           0.480     4.157    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/gen_srls[4].srl_nx1/skid_buffer_reg[1129][0]
    SLICE_X38Y84         LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.146     4.303 r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/gen_srls[4].srl_nx1/skid_buffer[1130]_i_4/O
                         net (fo=5, routed)           0.477     4.780    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/m_vector_i_reg[1129]
    SLICE_X37Y84         LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.090     4.870 r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/gen_pipelined.mesg_reg[7]_i_2/O
                         net (fo=1, routed)           0.521     5.391    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/gen_srls[7].srl_nx1/gen_pipelined.mesg_reg_reg[7]_0
    SLICE_X38Y83         LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.035     5.426 r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/gen_srls[7].srl_nx1/gen_pipelined.mesg_reg[7]_i_1__2/O
                         net (fo=1, routed)           0.050     5.476    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/gen_srls[7].srl_nx1_n_0
    SLICE_X38Y83         FDRE                                         r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/gen_pipelined.mesg_reg_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.508     6.189    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/aclk
    SLICE_X38Y83         FDRE                                         r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/gen_pipelined.mesg_reg_reg[7]/C
                         clock pessimism             -0.454     5.735    
                         clock uncertainty           -0.062     5.672    
    SLICE_X38Y83         FDRE (Setup_CFF_SLICEL_C_D)
                                                      0.025     5.697    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_payld_fifo/cmd_fifo/gen_pipelined.mesg_reg_reg[7]
  -------------------------------------------------------------------
                         required time                          5.697    
                         arrival time                          -5.476    
  -------------------------------------------------------------------
                         slack                                  0.221    

Slack (MET) :             0.222ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout0 rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        2.679ns  (logic 0.902ns (33.665%)  route 1.777ns (66.335%))
  Logic Levels:           8  (CARRY8=1 LUT3=1 LUT5=1 LUT6=5)
  Clock Path Skew:        -0.062ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.935ns = ( 5.936 - 3.001 ) 
    Source Clock Delay      (SCD):    2.521ns
    Clock Pessimism Removal (CPR):    -0.476ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.404ns (routing 0.415ns, distribution 0.989ns)
  Clock Net Delay (Destination): 1.255ns (routing 0.379ns, distribution 0.876ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.404     2.521    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X85Y93         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y93         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.600 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[0]/Q
                         net (fo=46, routed)          0.266     2.865    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[39]_0[0]
    SLICE_X83Y94         LUT6 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.090     2.955 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_21__0/O
                         net (fo=1, routed)           0.280     3.235    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_21__0_n_0
    SLICE_X86Y95         LUT6 (Prop_A6LUT_SLICEM_I3_O)
                                                      0.125     3.360 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_6__0/O
                         net (fo=1, routed)           0.013     3.373    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/i__carry_i_6__0_n_0
    SLICE_X86Y95         CARRY8 (Prop_CARRY8_SLICEM_S[0]_CO[5])
                                                      0.201     3.574 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/issue_cas3_inferred__0/i__carry/CO[5]
                         net (fo=5, routed)           0.254     3.829    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/issue_cas3_inferred__0/i__carry_n_2
    SLICE_X89Y95         LUT5 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.148     3.977 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0/O
                         net (fo=1, routed)           0.042     4.019    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_6__0_n_0
    SLICE_X89Y95         LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.039     4.058 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__2/O
                         net (fo=5, routed)           0.091     4.149    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/FSM_sequential_grSt[1]_i_2__2_n_0
    SLICE_X89Y95         LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.052     4.201 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__2/O
                         net (fo=77, routed)          0.316     4.517    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/cas_fifo_wptr[1]_i_2__2_n_0
    SLICE_X88Y95         LUT3 (Prop_E5LUT_SLICEL_I1_O)
                                                      0.070     4.587 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[47]_i_5/O
                         net (fo=31, routed)          0.449     5.036    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[47]_i_5_n_0
    SLICE_X82Y97         LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     5.134 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[17]_i_1__2/O
                         net (fo=1, routed)           0.066     5.200    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output[17]_i_1__2_n_0
    SLICE_X82Y97         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.255     5.936    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/rst_r1_reg_0
    SLICE_X82Y97         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[17]/C
                         clock pessimism             -0.476     5.459    
                         clock uncertainty           -0.062     5.397    
    SLICE_X82Y97         FDRE (Setup_CFF_SLICEM_C_D)
                                                      0.025     5.422    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_mc/bgr[1].u_ddr_mc_group/txn_fifo_output_reg[17]
  -------------------------------------------------------------------
                         required time                          5.422    
                         arrival time                          -5.200    
  -------------------------------------------------------------------
                         slack                                  0.222    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.012ns  (arrival time - required time)
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[181]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1206]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.132ns  (logic 0.060ns (45.455%)  route 0.072ns (54.545%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.616ns
    Source Clock Delay      (SCD):    2.979ns
    Clock Pessimism Removal (CPR):    -0.424ns
  Clock Net Delay (Source):      1.299ns (routing 0.379ns, distribution 0.920ns)
  Clock Net Delay (Destination): 1.499ns (routing 0.415ns, distribution 1.084ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.299     2.979    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X100Y112       FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[181]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y112       FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     3.039 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[181]/Q
                         net (fo=2, routed)           0.072     3.111    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[2080]_0[182]
    SLICE_X100Y110       FDRE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1206]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.499     2.616    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/aclk
    SLICE_X100Y110       FDRE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1206]/C
                         clock pessimism              0.424     3.039    
    SLICE_X100Y110       FDRE (Hold_GFF_SLICEL_C_D)
                                                      0.060     3.099    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1206]
  -------------------------------------------------------------------
                         required time                         -3.099    
                         arrival time                           3.111    
  -------------------------------------------------------------------
                         slack                                  0.012    

Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/m_vector_i_reg[1077]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1077]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.176ns  (logic 0.058ns (32.955%)  route 0.118ns (67.045%))
  Logic Levels:           0  
  Clock Path Skew:        0.103ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.828ns
    Source Clock Delay      (SCD):    3.179ns
    Clock Pessimism Removal (CPR):    -0.454ns
  Clock Net Delay (Source):      1.498ns (routing 0.379ns, distribution 1.119ns)
  Clock Net Delay (Destination): 1.711ns (routing 0.415ns, distribution 1.296ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.498     3.179    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/aclk
    SLICE_X48Y31         FDRE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/m_vector_i_reg[1077]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y31         FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.058     3.237 r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/m_vector_i_reg[1077]/Q
                         net (fo=2, routed)           0.118     3.355    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1144]_0[22]
    SLICE_X47Y30         FDRE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1077]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.711     2.828    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/aclk
    SLICE_X47Y30         FDRE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1077]/C
                         clock pessimism              0.454     3.281    
    SLICE_X47Y30         FDRE (Hold_GFF_SLICEL_C_D)
                                                      0.060     3.341    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1077]
  -------------------------------------------------------------------
                         required time                         -3.341    
                         arrival time                           3.355    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.014ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/m_vector_i_reg[1131]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1131]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.168ns  (logic 0.058ns (34.524%)  route 0.110ns (65.476%))
  Logic Levels:           0  
  Clock Path Skew:        0.092ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.820ns
    Source Clock Delay      (SCD):    3.181ns
    Clock Pessimism Removal (CPR):    -0.454ns
  Clock Net Delay (Source):      1.501ns (routing 0.379ns, distribution 1.122ns)
  Clock Net Delay (Destination): 1.703ns (routing 0.415ns, distribution 1.288ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.501     3.181    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/aclk
    SLICE_X49Y29         FDRE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/m_vector_i_reg[1131]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y29         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     3.239 r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/m_vector_i_reg[1131]/Q
                         net (fo=2, routed)           0.110     3.349    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1144]_0[44]
    SLICE_X47Y27         FDRE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1131]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.703     2.820    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/aclk
    SLICE_X47Y27         FDRE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1131]/C
                         clock pessimism              0.454     3.273    
    SLICE_X47Y27         FDRE (Hold_CFF2_SLICEL_C_D)
                                                      0.062     3.335    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer_reg[1131]
  -------------------------------------------------------------------
                         required time                         -3.335    
                         arrival time                           3.349    
  -------------------------------------------------------------------
                         slack                                  0.014    

Slack (MET) :             0.016ns  (arrival time - required time)
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[142]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1167]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.130ns  (logic 0.058ns (44.505%)  route 0.072ns (55.495%))
  Logic Levels:           0  
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.616ns
    Source Clock Delay      (SCD):    2.987ns
    Clock Pessimism Removal (CPR):    -0.424ns
  Clock Net Delay (Source):      1.306ns (routing 0.379ns, distribution 0.927ns)
  Clock Net Delay (Destination): 1.499ns (routing 0.415ns, distribution 1.084ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.306     2.987    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X101Y109       FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[142]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y109       FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     3.045 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/fifo_dout_r_reg[142]/Q
                         net (fo=2, routed)           0.072     3.117    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[2080]_0[143]
    SLICE_X101Y107       FDRE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1167]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.499     2.616    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/aclk
    SLICE_X101Y107       FDRE                                         r  d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1167]/C
                         clock pessimism              0.424     3.039    
    SLICE_X101Y107       FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.062     3.101    d_1_i/axi_smc_1/inst/s01_entry_pipeline/s01_mmu/inst/w_sreg/skid_buffer_reg[1167]
  -------------------------------------------------------------------
                         required time                         -3.101    
                         arrival time                           3.117    
  -------------------------------------------------------------------
                         slack                                  0.016    

Slack (MET) :             0.016ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[23]/C
                            (rising edge-triggered cell FDSE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_EN
                            (rising edge-triggered cell RXTX_BITSLICE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.193ns  (logic 0.040ns (20.725%)  route 0.153ns (79.275%))
  Logic Levels:           0  
  Clock Path Skew:        0.136ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.603ns
    Source Clock Delay      (SCD):    1.742ns
    Clock Pessimism Removal (CPR):    -0.274ns
  Clock Net Delay (Source):      0.815ns (routing 0.230ns, distribution 0.585ns)
  Clock Net Delay (Destination): 1.041ns (routing 0.255ns, distribution 0.786ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.815     1.742    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y54         FDSE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y54         FDSE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.782 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_clb2phy_fifo_rden_reg[23]/Q
                         net (fo=1, routed)           0.153     1.935    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_clb2phy_fifo_rden[0]
    BITSLICE_RX_TX_X0Y49 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_EN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.041     1.603    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/div_clk
    BITSLICE_RX_TX_X0Y49 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
                         clock pessimism              0.274     1.877    
    BITSLICE_RX_TX_X0Y49 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_FIFO_RD_CLK_FIFO_RD_EN)
                                                      0.041     1.918    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -1.918    
                         arrival time                           1.935    
  -------------------------------------------------------------------
                         slack                                  0.016    

Slack (MET) :             0.017ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.occ_cnt_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.occ_cnt_r_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.168ns  (logic 0.094ns (55.805%)  route 0.074ns (44.195%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.089ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.538ns
    Source Clock Delay      (SCD):    2.925ns
    Clock Pessimism Removal (CPR):    -0.476ns
  Clock Net Delay (Source):      1.245ns (routing 0.379ns, distribution 0.866ns)
  Clock Net Delay (Destination): 1.421ns (routing 0.415ns, distribution 1.006ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.245     2.925    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf_indx_sts_r_reg[3][5]_0
    SLICE_X85Y83         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.occ_cnt_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y83         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     2.984 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.occ_cnt_r_reg[2]/Q
                         net (fo=6, routed)           0.063     3.048    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.occ_cnt_r_reg[2]
    SLICE_X86Y83         LUT5 (Prop_B5LUT_SLICEM_I1_O)
                                                      0.035     3.083 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.occ_cnt_r[5]_i_2/O
                         net (fo=1, routed)           0.011     3.094    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.occ_cnt_r[5]
    SLICE_X86Y83         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.occ_cnt_r_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.421     2.538    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.rd_buf_indx_sts_r_reg[3][5]_0
    SLICE_X86Y83         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.occ_cnt_r_reg[5]/C
                         clock pessimism              0.476     3.014    
    SLICE_X86Y83         FDRE (Hold_BFF2_SLICEM_C_D)
                                                      0.062     3.076    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_ui/u_ddr_ui_rd_data/not_strict_mode.occ_cnt_r_reg[5]
  -------------------------------------------------------------------
                         required time                         -3.076    
                         arrival time                           3.094    
  -------------------------------------------------------------------
                         slack                                  0.017    

Slack (MET) :             0.020ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/w_sreg/m_vector_i_reg[1029]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.186ns  (logic 0.061ns (32.796%)  route 0.125ns (67.204%))
  Logic Levels:           0  
  Clock Path Skew:        0.104ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.925ns
    Source Clock Delay      (SCD):    3.267ns
    Clock Pessimism Removal (CPR):    -0.446ns
  Clock Net Delay (Source):      1.587ns (routing 0.379ns, distribution 1.208ns)
  Clock Net Delay (Destination): 1.808ns (routing 0.415ns, distribution 1.393ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.587     3.267    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/w_sreg/aclk
    SLICE_X29Y77         FDRE                                         r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/w_sreg/m_vector_i_reg[1029]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X29Y77         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     3.328 r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_mmu/inst/w_sreg/m_vector_i_reg[1029]/Q
                         net (fo=1, routed)           0.125     3.453    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/s_axi_wdata[4]
    SLICE_X32Y76         FDRE                                         r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.808     2.925    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/aclk
    SLICE_X32Y76         FDRE                                         r  d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][4]/C
                         clock pessimism              0.446     3.371    
    SLICE_X32Y76         FDRE (Hold_FFF2_SLICEL_C_D)
                                                      0.062     3.433    d_1_i/axi_smc_1/inst/s00_entry_pipeline/s00_si_converter/inst/converter.wrap_narrow_inst/w_accum_reg[data][4]
  -------------------------------------------------------------------
                         required time                         -3.433    
                         arrival time                           3.453    
  -------------------------------------------------------------------
                         slack                                  0.020    

Slack (MET) :             0.020ns  (arrival time - required time)
  Source:                 d_1_i/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[90]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][90]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.180ns  (logic 0.061ns (33.889%)  route 0.119ns (66.111%))
  Logic Levels:           0  
  Clock Path Skew:        0.098ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.565ns
    Source Clock Delay      (SCD):    2.940ns
    Clock Pessimism Removal (CPR):    -0.473ns
  Clock Net Delay (Source):      1.260ns (routing 0.379ns, distribution 0.881ns)
  Clock Net Delay (Destination): 1.448ns (routing 0.415ns, distribution 1.033ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.260     2.940    d_1_i/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/clka
    SLICE_X89Y44         FDRE                                         r  d_1_i/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[90]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y44         FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.061     3.001 r  d_1_i/axi_smc_1/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[90]/Q
                         net (fo=1, routed)           0.119     3.120    d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/s_sc_payld[80]
    SLICE_X87Y45         FDRE                                         r  d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][90]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.448     2.565    d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk
    SLICE_X87Y45         FDRE                                         r  d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][90]/C
                         clock pessimism              0.473     3.038    
    SLICE_X87Y45         FDRE (Hold_CFF2_SLICEM_C_D)
                                                      0.062     3.100    d_1_i/axi_smc_1/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][90]
  -------------------------------------------------------------------
                         required time                         -3.100    
                         arrival time                           3.120    
  -------------------------------------------------------------------
                         slack                                  0.020    

Slack (MET) :             0.021ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/lowCL1_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/lowCL1_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.135ns  (logic 0.059ns (43.573%)  route 0.076ns (56.427%))
  Logic Levels:           0  
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.559ns
    Source Clock Delay      (SCD):    2.931ns
    Clock Pessimism Removal (CPR):    -0.425ns
  Clock Net Delay (Source):      1.251ns (routing 0.379ns, distribution 0.872ns)
  Clock Net Delay (Destination): 1.442ns (routing 0.415ns, distribution 1.027ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.251     2.931    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X91Y24         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/lowCL1_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y24         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     2.990 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/lowCL1_reg[6]/Q
                         net (fo=2, routed)           0.076     3.066    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/ub_lowCL1[6]
    SLICE_X91Y25         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/lowCL1_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.442     2.559    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/SYNC[0].sync_reg_reg[0]
    SLICE_X91Y25         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/lowCL1_reg[6]/C
                         clock pessimism              0.425     2.984    
    SLICE_X91Y25         FDRE (Hold_FFF2_SLICEL_C_D)
                                                      0.062     3.046    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/lowCL1_reg[6]
  -------------------------------------------------------------------
                         required time                         -3.046    
                         arrival time                           3.066    
  -------------------------------------------------------------------
                         slack                                  0.021    

Slack (MET) :             0.021ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/bram_di_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout0 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.188ns  (logic 0.060ns (31.915%)  route 0.128ns (68.085%))
  Logic Levels:           0  
  Clock Path Skew:        0.105ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.548ns
    Source Clock Delay      (SCD):    2.919ns
    Clock Pessimism Removal (CPR):    -0.476ns
  Clock Net Delay (Source):      1.239ns (routing 0.379ns, distribution 0.860ns)
  Clock Net Delay (Destination): 1.431ns (routing 0.415ns, distribution 1.016ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.239     2.919    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[1]_0
    SLICE_X92Y64         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y64         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.060     2.979 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[1]/Q
                         net (fo=1, routed)           0.128     3.107    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_fclk[0]
    SLICE_X91Y65         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/bram_di_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.431     2.548    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X91Y65         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/bram_di_reg[0]/C
                         clock pessimism              0.476     3.024    
    SLICE_X91Y65         FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.062     3.086    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/bram_di_reg[0]
  -------------------------------------------------------------------
                         required time                         -3.086    
                         arrival time                           3.107    
  -------------------------------------------------------------------
                         slack                                  0.021    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout0
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0 }

Check Type        Corner  Lib Pin                    Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location              Pin
Min Period        n/a     PS8/MAXIGP1ACLK            n/a            3.000         3.001       0.001      PS8_X0Y0              d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y3   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y4   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y5   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y6   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y8   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y9   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Min Period        n/a     RXTX_BITSLICE/FIFO_RD_CLK  n/a            1.694         3.001       1.307      BITSLICE_RX_TX_X0Y10  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/FIFO_RD_CLK
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y0              d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Max Period        n/a     PLLE4_ADV/CLKIN            n/a            14.286        3.001       11.285     PLL_X0Y2              d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0              d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Low Pulse Width   Slow    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0              d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y0              d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y0              d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y2              d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y2              d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
Low Pulse Width   Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Low Pulse Width   Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Low Pulse Width   Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
Low Pulse Width   Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Slow    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0              d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
High Pulse Width  Fast    PS8/MAXIGP1ACLK            n/a            1.500         1.500       0.000      PS8_X0Y0              d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/MAXIGP1ACLK
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y0              d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y0              d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y2              d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Fast    PLLE4_ADV/CLKIN            n/a            1.050         1.500       0.450      PLL_X0Y2              d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKIN
High Pulse Width  Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Slow    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK
High Pulse Width  Fast    RXTX_BITSLICE/FIFO_RD_CLK  n/a            0.762         1.500       0.738      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/FIFO_RD_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[0]
  To Clock:  pll_clk[0]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[0]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location               Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y0  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y1  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y2  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y3  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y4  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y5  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y6  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a                       0.375         0.375       0.000      BITSLICE_CONTROL_X0Y7  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a                       0.333         0.375       0.042      PLL_X0Y0               d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y0  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y0  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y1  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y1  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y2  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y2  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y3  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y3  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y4  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y4  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y0  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y0  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y1  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y1  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y2  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y2  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y3  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y3  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y4  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a                       0.169         0.188       0.019      BITSLICE_CONTROL_X0Y4  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.329      1.029      BITSLICE_CONTROL_X0Y4  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.333      1.033      BITSLICE_CONTROL_X0Y6  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.335      1.035      BITSLICE_CONTROL_X0Y5  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.336      1.036      BITSLICE_CONTROL_X0Y2  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.336      1.036      BITSLICE_CONTROL_X0Y3  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.337      1.037      BITSLICE_CONTROL_X0Y0  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.337      1.037      BITSLICE_CONTROL_X0Y7  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Fast    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.342      1.042      BITSLICE_CONTROL_X0Y1  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.483      1.183      BITSLICE_CONTROL_X0Y4  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Max Skew          Slow    BITSLICE_CONTROL/PLL_CLK  BITSLICE_CONTROL/RIU_CLK  -0.300        -1.491      1.191      BITSLICE_CONTROL_X0Y6  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[0]_DIV
  To Clock:  pll_clk[0]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[0]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location              Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y3   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y4   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y5   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y6   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y8   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y9   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y10  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y11  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y3   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y3   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y4   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y4   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y5   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y5   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y3   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y3   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y4   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y4   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y5   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y5   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[1]
  To Clock:  pll_clk[1]

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[1]
Waveform(ns):       { 0.000 0.188 }
Period(ns):         0.375
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY }

Check Type        Corner  Lib Pin                   Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y8   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y10  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y11  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y12  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y13  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y14  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     BITSLICE_CONTROL/PLL_CLK  n/a            0.375         0.375       0.000      BITSLICE_CONTROL_X0Y15  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Min Period        n/a     PLLE4_ADV/CLKOUTPHY       n/a            0.333         0.375       0.042      PLL_X0Y2                d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y8   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y8   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y10  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y10  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y11  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y11  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y12  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y12  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y13  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y13  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y8   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y8   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y10  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y10  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y11  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y11  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y12  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y12  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y13  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/PLL_CLK  n/a            0.169         0.188       0.019      BITSLICE_CONTROL_X0Y13  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PLL_CLK



---------------------------------------------------------------------------------------------------
From Clock:  pll_clk[1]_DIV
  To Clock:  pll_clk[1]_DIV

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        0.300ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         pll_clk[1]_DIV
Waveform(ns):       { 0.000 1.500 }
Period(ns):         3.001
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q }

Check Type        Corner  Lib Pin                           Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location              Pin
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y56  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y67  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y68  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y71  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y72  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y78  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y80  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y81  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y82  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Min Period        n/a     RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            2.667         3.001       0.334      BITSLICE_RX_TX_X0Y83  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y56  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y56  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y67  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y67  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y68  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y68  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y71  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y71  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y72  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
Low Pulse Width   Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y72  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y56  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y56  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y67  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y67  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y68  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y68  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y71  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y71  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Slow    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y72  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
High Pulse Width  Fast    RXTX_BITSLICE/TX_BIT_CTRL_IN[26]  n/a            1.200         1.500       0.300      BITSLICE_RX_TX_X0Y72  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack        9.414ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.030ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        5.469ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             9.414ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]/CE
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.377ns  (logic 0.660ns (27.771%)  route 1.717ns (72.229%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.076ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.775ns = ( 14.778 - 12.002 ) 
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    -0.487ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.257ns (routing 0.171ns, distribution 1.086ns)
  Clock Net Delay (Destination): 1.104ns (routing 0.155ns, distribution 0.949ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.257     2.364    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X103Y68        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y68        FDCE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     2.444 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/Q
                         net (fo=4, routed)           0.671     3.114    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg_n_0_[13]
    SLICE_X104Y69        LUT4 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.158     3.272 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.229     3.501    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X104Y69        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.150     3.651 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.163     3.814    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X104Y68        LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.124     3.938 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.124     4.063    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X104Y70        LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.148     4.211 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_rst_r[0]_i_1/O
                         net (fo=2, routed)           0.530     4.740    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode
    SLICE_X104Y72        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.104    14.778    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y72        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]/C
                         clock pessimism             -0.487    14.291    
                         clock uncertainty           -0.076    14.215    
    SLICE_X104Y72        FDCE (Setup_HFF2_SLICEM_C_CE)
                                                     -0.061    14.154    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_rst_r_reg[0]
  -------------------------------------------------------------------
                         required time                         14.154    
                         arrival time                          -4.740    
  -------------------------------------------------------------------
                         slack                                  9.414    

Slack (MET) :             9.469ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.407ns  (logic 0.731ns (30.365%)  route 1.676ns (69.635%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.076ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.775ns = ( 14.778 - 12.002 ) 
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    -0.487ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.257ns (routing 0.171ns, distribution 1.086ns)
  Clock Net Delay (Destination): 1.104ns (routing 0.155ns, distribution 0.949ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.257     2.364    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X103Y68        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y68        FDCE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     2.444 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/Q
                         net (fo=4, routed)           0.671     3.114    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg_n_0_[13]
    SLICE_X104Y69        LUT4 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.158     3.272 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.229     3.501    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X104Y69        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.150     3.651 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.163     3.814    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X104Y68        LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.124     3.938 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.154     4.092    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X105Y70        LUT5 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.096     4.188 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9/O
                         net (fo=1, routed)           0.414     4.602    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_n_0
    SLICE_X105Y70        LUT6 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.123     4.725 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_dwe_r[0]_i_1/O
                         net (fo=1, routed)           0.046     4.771    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_13
    SLICE_X105Y70        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.104    14.778    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X105Y70        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]/C
                         clock pessimism             -0.487    14.291    
                         clock uncertainty           -0.076    14.215    
    SLICE_X105Y70        FDCE (Setup_EFF_SLICEL_C_D)
                                                      0.025    14.240    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_dwe_r_reg[0]
  -------------------------------------------------------------------
                         required time                         14.240    
                         arrival time                          -4.771    
  -------------------------------------------------------------------
                         slack                                  9.469    

Slack (MET) :             9.503ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg/CE
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.289ns  (logic 0.660ns (28.839%)  route 1.629ns (71.161%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.076ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.775ns = ( 14.778 - 12.002 ) 
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    -0.487ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.257ns (routing 0.171ns, distribution 1.086ns)
  Clock Net Delay (Destination): 1.104ns (routing 0.155ns, distribution 0.949ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.257     2.364    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X103Y68        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y68        FDCE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     2.444 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/Q
                         net (fo=4, routed)           0.671     3.114    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg_n_0_[13]
    SLICE_X104Y69        LUT4 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.158     3.272 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.229     3.501    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X104Y69        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.150     3.651 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.163     3.814    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X104Y68        LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.124     3.938 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.124     4.063    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X104Y70        LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.148     4.211 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/sl_rst_r[0]_i_1/O
                         net (fo=2, routed)           0.442     4.652    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode
    SLICE_X105Y70        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.104    14.778    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X105Y70        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg/C
                         clock pessimism             -0.487    14.291    
                         clock uncertainty           -0.076    14.215    
    SLICE_X105Y70        FDCE (Setup_HFF2_SLICEL_C_CE)
                                                     -0.060    14.155    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/in_normal_mode_reg
  -------------------------------------------------------------------
                         required time                         14.155    
                         arrival time                          -4.652    
  -------------------------------------------------------------------
                         slack                                  9.503    

Slack (MET) :             9.532ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.367ns  (logic 0.769ns (32.494%)  route 1.598ns (67.506%))
  Logic Levels:           5  (LUT3=1 LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.053ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.798ns = ( 14.800 - 12.002 ) 
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    -0.487ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.257ns (routing 0.171ns, distribution 1.086ns)
  Clock Net Delay (Destination): 1.127ns (routing 0.155ns, distribution 0.972ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.257     2.364    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X103Y68        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y68        FDCE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     2.444 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/Q
                         net (fo=4, routed)           0.671     3.114    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg_n_0_[13]
    SLICE_X104Y69        LUT4 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.158     3.272 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.229     3.501    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X104Y69        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.150     3.651 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.163     3.814    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X104Y68        LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.124     3.938 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.172     4.110    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X105Y69        LUT5 (Prop_H5LUT_SLICEL_I1_O)
                                                      0.158     4.268 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__6/O
                         net (fo=1, routed)           0.291     4.559    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__6_n_0
    SLICE_X107Y69        LUT3 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.099     4.658 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/dec_wdc_r_i_1/O
                         net (fo=1, routed)           0.072     4.730    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_10
    SLICE_X107Y69        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.127    14.800    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X107Y69        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg/C
                         clock pessimism             -0.487    14.313    
                         clock uncertainty           -0.076    14.237    
    SLICE_X107Y69        FDCE (Setup_DFF_SLICEM_C_D)
                                                      0.025    14.262    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/dec_wdc_r_reg
  -------------------------------------------------------------------
                         required time                         14.262    
                         arrival time                          -4.730    
  -------------------------------------------------------------------
                         slack                                  9.532    

Slack (MET) :             9.589ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.304ns  (logic 0.768ns (33.334%)  route 1.536ns (66.666%))
  Logic Levels:           5  (LUT4=2 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.059ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.792ns = ( 14.795 - 12.002 ) 
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    -0.487ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.257ns (routing 0.171ns, distribution 1.086ns)
  Clock Net Delay (Destination): 1.121ns (routing 0.155ns, distribution 0.966ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.257     2.364    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X103Y68        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y68        FDCE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     2.444 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/Q
                         net (fo=4, routed)           0.671     3.114    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg_n_0_[13]
    SLICE_X104Y69        LUT4 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.158     3.272 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.229     3.501    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X104Y69        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.150     3.651 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.163     3.814    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X104Y68        LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.124     3.938 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.339     4.278    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X104Y65        LUT5 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.098     4.376 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b1/O
                         net (fo=1, routed)           0.104     4.480    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_16
    SLICE_X104Y65        LUT4 (Prop_D5LUT_SLICEM_I2_O)
                                                      0.158     4.638 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r[1]_i_1/O
                         net (fo=1, routed)           0.030     4.668    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r[1]_i_1_n_0
    SLICE_X104Y65        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.121    14.795    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y65        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]/C
                         clock pessimism             -0.487    14.307    
                         clock uncertainty           -0.076    14.232    
    SLICE_X104Y65        FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    14.257    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/ma_err_r_reg[1]
  -------------------------------------------------------------------
                         required time                         14.257    
                         arrival time                          -4.668    
  -------------------------------------------------------------------
                         slack                                  9.589    

Slack (MET) :             9.624ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.268ns  (logic 0.674ns (29.718%)  route 1.594ns (70.282%))
  Logic Levels:           5  (LUT3=1 LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.060ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.791ns = ( 14.794 - 12.002 ) 
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    -0.487ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.257ns (routing 0.171ns, distribution 1.086ns)
  Clock Net Delay (Destination): 1.120ns (routing 0.155ns, distribution 0.965ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.257     2.364    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X103Y68        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y68        FDCE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     2.444 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[13]/Q
                         net (fo=4, routed)           0.671     3.114    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg_n_0_[13]
    SLICE_X104Y69        LUT4 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.158     3.272 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/g0_b0__9_i_12/O
                         net (fo=2, routed)           0.229     3.501    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/ma_err_r_reg[0]_1
    SLICE_X104Y69        LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.150     3.651 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10/O
                         net (fo=2, routed)           0.163     3.814    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_10_n_0
    SLICE_X104Y68        LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.124     3.938 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__9_i_2/O
                         net (fo=23, routed)          0.339     4.278    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg_0
    SLICE_X104Y65        LUT5 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.111     4.389 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__2/O
                         net (fo=1, routed)           0.125     4.514    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__2_n_0
    SLICE_X104Y66        LUT3 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.051     4.565 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/auto_sl_drdy_i_1/O
                         net (fo=1, routed)           0.067     4.632    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_8
    SLICE_X104Y66        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.120    14.794    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y66        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg/C
                         clock pessimism             -0.487    14.306    
                         clock uncertainty           -0.076    14.231    
    SLICE_X104Y66        FDCE (Setup_FFF_SLICEM_C_D)
                                                      0.025    14.256    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/auto_sl_drdy_reg
  -------------------------------------------------------------------
                         required time                         14.256    
                         arrival time                          -4.632    
  -------------------------------------------------------------------
                         slack                                  9.624    

Slack (MET) :             9.689ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[14]/CE
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.035ns  (logic 0.116ns (5.702%)  route 1.919ns (94.298%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.143ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.715ns = ( 14.717 - 12.002 ) 
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    -0.494ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.257ns (routing 0.171ns, distribution 1.086ns)
  Clock Net Delay (Destination): 1.044ns (routing 0.155ns, distribution 0.889ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.257     2.364    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X101Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y71        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     2.443 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[9]/Q
                         net (fo=5, routed)           1.052     3.495    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[13]
    SLICE_X96Y72         LUT6 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.037     3.532 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test[15]_i_1/O
                         net (fo=16, routed)          0.866     4.398    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test0
    SLICE_X96Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[14]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.044    14.717    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[14]/C
                         clock pessimism             -0.494    14.223    
                         clock uncertainty           -0.076    14.148    
    SLICE_X96Y67         FDRE (Setup_HFF_SLICEM_C_CE)
                                                     -0.061    14.087    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[14]
  -------------------------------------------------------------------
                         required time                         14.087    
                         arrival time                          -4.398    
  -------------------------------------------------------------------
                         slack                                  9.689    

Slack (MET) :             9.689ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[15]/CE
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.035ns  (logic 0.116ns (5.702%)  route 1.919ns (94.298%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        -0.143ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.715ns = ( 14.717 - 12.002 ) 
    Source Clock Delay      (SCD):    2.364ns
    Clock Pessimism Removal (CPR):    -0.494ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.257ns (routing 0.171ns, distribution 1.086ns)
  Clock Net Delay (Destination): 1.044ns (routing 0.155ns, distribution 0.889ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.257     2.364    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X101Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y71        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     2.443 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[9]/Q
                         net (fo=5, routed)           1.052     3.495    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[13]
    SLICE_X96Y72         LUT6 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.037     3.532 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test[15]_i_1/O
                         net (fo=16, routed)          0.866     4.398    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test0
    SLICE_X96Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[15]/CE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.044    14.717    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[15]/C
                         clock pessimism             -0.494    14.223    
                         clock uncertainty           -0.076    14.148    
    SLICE_X96Y67         FDRE (Setup_GFF_SLICEM_C_CE)
                                                     -0.061    14.087    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_test_reg[15]
  -------------------------------------------------------------------
                         required time                         14.087    
                         arrival time                          -4.398    
  -------------------------------------------------------------------
                         slack                                  9.689    

Slack (MET) :             9.728ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.128ns  (logic 0.605ns (28.425%)  route 1.523ns (71.575%))
  Logic Levels:           5  (LUT3=1 LUT5=2 LUT6=2)
  Clock Path Skew:        -0.095ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.790ns = ( 14.793 - 12.002 ) 
    Source Clock Delay      (SCD):    2.398ns
    Clock Pessimism Removal (CPR):    -0.488ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.291ns (routing 0.171ns, distribution 1.120ns)
  Clock Net Delay (Destination): 1.119ns (routing 0.155ns, distribution 0.964ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.291     2.398    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X107Y69        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y69        FDCE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     2.478 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[1]/Q
                         net (fo=3, routed)           0.438     2.916    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/Q[1]
    SLICE_X105Y69        LUT5 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.123     3.039 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state[2]_i_2/O
                         net (fo=2, routed)           0.430     3.469    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[16]
    SLICE_X103Y69        LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.037     3.506 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_4/O
                         net (fo=1, routed)           0.109     3.615    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_4_n_0
    SLICE_X104Y69        LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.125     3.740 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/in_normal_mode_i_1/O
                         net (fo=24, routed)          0.375     4.115    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/FSM_onehot_current_state_reg[11]
    SLICE_X105Y69        LUT5 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.088     4.203 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__5/O
                         net (fo=1, routed)           0.113     4.316    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/g0_b0__5_n_0
    SLICE_X104Y69        LUT3 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.152     4.468 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/inc_addr_r_i_1/O
                         net (fo=1, routed)           0.058     4.526    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER_n_9
    SLICE_X104Y69        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.119    14.793    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y69        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg/C
                         clock pessimism             -0.488    14.305    
                         clock uncertainty           -0.076    14.230    
    SLICE_X104Y69        FDCE (Setup_HFF_SLICEM_C_D)
                                                      0.025    14.255    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/inc_addr_r_reg
  -------------------------------------------------------------------
                         required time                         14.255    
                         arrival time                          -4.526    
  -------------------------------------------------------------------
                         slack                                  9.728    

Slack (MET) :             9.769ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        2.047ns  (logic 0.415ns (20.271%)  route 1.632ns (79.729%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        -0.136ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.727ns = ( 14.729 - 12.002 ) 
    Source Clock Delay      (SCD):    2.369ns
    Clock Pessimism Removal (CPR):    -0.494ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.262ns (routing 0.171ns, distribution 1.091ns)
  Clock Net Delay (Destination): 1.055ns (routing 0.155ns, distribution 0.900ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.262     2.369    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/clk
    SLICE_X101Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y70        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.448 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_ADDRESS_CONTROLLER/addr_reg[7]/Q
                         net (fo=6, routed)           0.827     3.274    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[11]
    SLICE_X95Y70         LUT5 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.146     3.420 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4/O
                         net (fo=14, routed)          0.467     3.888    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[15]_i_4_n_0
    SLICE_X91Y69         LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.090     3.978 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]_i_2/O
                         net (fo=1, routed)           0.279     4.257    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]_i_2_n_0
    SLICE_X94Y69         LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.100     4.357 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]_i_1/O
                         net (fo=1, routed)           0.059     4.416    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do[5]
    SLICE_X94Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.055    14.729    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X94Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[5]/C
                         clock pessimism             -0.494    14.235    
                         clock uncertainty           -0.076    14.160    
    SLICE_X94Y69         FDRE (Setup_BFF_SLICEM_C_D)
                                                      0.025    14.185    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/reg_do_reg[5]
  -------------------------------------------------------------------
                         required time                         14.185    
                         arrival time                          -4.416    
  -------------------------------------------------------------------
                         slack                                  9.769    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[122]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[122]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.082ns  (logic 0.039ns (47.561%)  route 0.043ns (52.439%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.326ns
    Source Clock Delay      (SCD):    1.595ns
    Clock Pessimism Removal (CPR):    -0.275ns
  Clock Net Delay (Source):      0.677ns (routing 0.096ns, distribution 0.581ns)
  Clock Net Delay (Destination): 0.771ns (routing 0.108ns, distribution 0.663ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.677     1.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[122]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y70         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.634 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[122]/Q
                         net (fo=2, routed)           0.043     1.677    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[122]
    SLICE_X95Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[122]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.771     1.326    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[122]/C
                         clock pessimism              0.275     1.601    
    SLICE_X95Y70         FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.046     1.647    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[122]
  -------------------------------------------------------------------
                         required time                         -1.647    
                         arrival time                           1.677    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.083ns  (logic 0.039ns (47.074%)  route 0.044ns (52.926%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.328ns
    Source Clock Delay      (SCD):    1.596ns
    Clock Pessimism Removal (CPR):    -0.274ns
  Clock Net Delay (Source):      0.678ns (routing 0.096ns, distribution 0.582ns)
  Clock Net Delay (Destination): 0.773ns (routing 0.108ns, distribution 0.665ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.678     1.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y66         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y66         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.635 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[12]/Q
                         net (fo=2, routed)           0.044     1.679    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[12]
    SLICE_X96Y66         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.773     1.328    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y66         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[12]/C
                         clock pessimism              0.274     1.602    
    SLICE_X96Y66         FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.046     1.648    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[12]
  -------------------------------------------------------------------
                         required time                         -1.648    
                         arrival time                           1.679    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[77]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[77]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.083ns  (logic 0.039ns (47.074%)  route 0.044ns (52.926%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.328ns
    Source Clock Delay      (SCD):    1.595ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Net Delay (Source):      0.677ns (routing 0.096ns, distribution 0.581ns)
  Clock Net Delay (Destination): 0.773ns (routing 0.108ns, distribution 0.665ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.677     1.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y68         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[77]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y68         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.634 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[77]/Q
                         net (fo=2, routed)           0.044     1.678    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[77]
    SLICE_X96Y68         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[77]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.773     1.328    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y68         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[77]/C
                         clock pessimism              0.273     1.601    
    SLICE_X96Y68         FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.046     1.647    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[77]
  -------------------------------------------------------------------
                         required time                         -1.647    
                         arrival time                           1.678    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.084ns  (logic 0.039ns (46.377%)  route 0.045ns (53.623%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.323ns
    Source Clock Delay      (SCD):    1.592ns
    Clock Pessimism Removal (CPR):    -0.276ns
  Clock Net Delay (Source):      0.674ns (routing 0.096ns, distribution 0.578ns)
  Clock Net Delay (Destination): 0.768ns (routing 0.108ns, distribution 0.660ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.674     1.592    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y66         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y66         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.631 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[25]/Q
                         net (fo=2, routed)           0.045     1.677    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[25]
    SLICE_X95Y66         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.768     1.323    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X95Y66         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[25]/C
                         clock pessimism              0.276     1.598    
    SLICE_X95Y66         FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.046     1.644    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[25]
  -------------------------------------------------------------------
                         required time                         -1.644    
                         arrival time                           1.677    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.032ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[101]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[101]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.084ns  (logic 0.039ns (46.377%)  route 0.045ns (53.623%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.321ns
    Source Clock Delay      (SCD):    1.588ns
    Clock Pessimism Removal (CPR):    -0.274ns
  Clock Net Delay (Source):      0.670ns (routing 0.096ns, distribution 0.574ns)
  Clock Net Delay (Destination): 0.766ns (routing 0.108ns, distribution 0.658ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.670     1.588    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X91Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[101]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y69         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[101]/Q
                         net (fo=2, routed)           0.045     1.673    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[101]
    SLICE_X91Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[101]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.766     1.321    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X91Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[101]/C
                         clock pessimism              0.274     1.594    
    SLICE_X91Y69         FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.046     1.640    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[101]
  -------------------------------------------------------------------
                         required time                         -1.640    
                         arrival time                           1.673    
  -------------------------------------------------------------------
                         slack                                  0.032    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[59]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[59]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.086ns  (logic 0.039ns (45.517%)  route 0.047ns (54.483%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.321ns
    Source Clock Delay      (SCD):    1.590ns
    Clock Pessimism Removal (CPR):    -0.276ns
  Clock Net Delay (Source):      0.672ns (routing 0.096ns, distribution 0.576ns)
  Clock Net Delay (Destination): 0.766ns (routing 0.108ns, distribution 0.658ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.672     1.590    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X92Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[59]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y70         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.629 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[59]/Q
                         net (fo=2, routed)           0.047     1.676    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[59]
    SLICE_X92Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[59]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.766     1.321    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X92Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[59]/C
                         clock pessimism              0.276     1.596    
    SLICE_X92Y70         FDRE (Hold_FFF_SLICEL_C_D)
                                                      0.046     1.642    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[59]
  -------------------------------------------------------------------
                         required time                         -1.642    
                         arrival time                           1.676    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.090ns  (logic 0.037ns (41.111%)  route 0.053ns (58.889%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.328ns
    Source Clock Delay      (SCD):    1.595ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Net Delay (Source):      0.677ns (routing 0.096ns, distribution 0.581ns)
  Clock Net Delay (Destination): 0.773ns (routing 0.108ns, distribution 0.665ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.677     1.595    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y68         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y68         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     1.632 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[13]/Q
                         net (fo=2, routed)           0.053     1.685    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[13]
    SLICE_X96Y68         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.773     1.328    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y68         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[13]/C
                         clock pessimism              0.273     1.601    
    SLICE_X96Y68         FDRE (Hold_FFF_SLICEM_C_D)
                                                      0.046     1.647    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[13]
  -------------------------------------------------------------------
                         required time                         -1.647    
                         arrival time                           1.685    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.038ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.090ns  (logic 0.037ns (41.111%)  route 0.053ns (58.889%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.326ns
    Source Clock Delay      (SCD):    1.592ns
    Clock Pessimism Removal (CPR):    -0.272ns
  Clock Net Delay (Source):      0.674ns (routing 0.096ns, distribution 0.578ns)
  Clock Net Delay (Destination): 0.771ns (routing 0.108ns, distribution 0.663ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.674     1.592    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X90Y75         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[21]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y75         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     1.629 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[21]/Q
                         net (fo=2, routed)           0.053     1.682    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[21]
    SLICE_X90Y75         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[21]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.771     1.326    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X90Y75         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[21]/C
                         clock pessimism              0.272     1.598    
    SLICE_X90Y75         FDRE (Hold_FFF_SLICEM_C_D)
                                                      0.046     1.644    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[21]
  -------------------------------------------------------------------
                         required time                         -1.644    
                         arrival time                           1.682    
  -------------------------------------------------------------------
                         slack                                  0.038    

Slack (MET) :             0.040ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/count_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.093ns  (logic 0.060ns (64.516%)  route 0.033ns (35.484%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.374ns
    Source Clock Delay      (SCD):    1.636ns
    Clock Pessimism Removal (CPR):    -0.268ns
  Clock Net Delay (Source):      0.718ns (routing 0.096ns, distribution 0.622ns)
  Clock Net Delay (Destination): 0.819ns (routing 0.108ns, distribution 0.711ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.718     1.636    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/clk
    SLICE_X103Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/count_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y67        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     1.674 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/count_reg[6]/Q
                         net (fo=2, routed)           0.025     1.699    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/count_reg[6]
    SLICE_X103Y67        LUT2 (Prop_B5LUT_SLICEM_I0_O)
                                                      0.022     1.721 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_i_1/O
                         net (fo=1, routed)           0.008     1.729    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_i_1_n_0
    SLICE_X103Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.819     1.374    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/clk
    SLICE_X103Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg/C
                         clock pessimism              0.268     1.642    
    SLICE_X103Y67        FDRE (Hold_BFF2_SLICEM_C_D)
                                                      0.047     1.689    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/U_TIMER/timeout_reg
  -------------------------------------------------------------------
                         required time                         -1.689    
                         arrival time                           1.729    
  -------------------------------------------------------------------
                         slack                                  0.040    

Slack (MET) :             0.042ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.094ns  (logic 0.039ns (41.448%)  route 0.055ns (58.552%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.329ns
    Source Clock Delay      (SCD):    1.596ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Net Delay (Source):      0.678ns (routing 0.096ns, distribution 0.582ns)
  Clock Net Delay (Destination): 0.774ns (routing 0.108ns, distribution 0.666ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.678     1.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y70         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.635 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/Q
                         net (fo=2, routed)           0.055     1.690    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp[7]
    SLICE_X96Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.774     1.329    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/sl_iport_i[1]
    SLICE_X96Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]/C
                         clock pessimism              0.273     1.602    
    SLICE_X96Y70         FDRE (Hold_DFF_SLICEM_C_D)
                                                      0.046     1.648    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/U_XSDB_SLAVE/uuid_stamp_reg[7]
  -------------------------------------------------------------------
                         required time                         -1.648    
                         arrival time                           1.690    
  -------------------------------------------------------------------
                         slack                                  0.042    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout5
Waveform(ns):       { 0.000 6.001 }
Period(ns):         12.002
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFGCE/I            n/a            1.290         12.002      10.712     BUFGCE_X0Y32   d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/I
Min Period        n/a     MMCME4_ADV/CLKOUT5  n/a            1.071         12.002      10.931     MMCM_X0Y1      d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC_D1/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
Min Period        n/a     RAMD32/CLK          n/a            1.064         12.002      10.938     SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMA_D1/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB_D1/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            0.532         6.001       5.469      SLICE_X103Y66  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMC/CLK



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout6

Setup :            0  Failing Endpoints,  Worst Slack        1.605ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.021ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        1.018ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.605ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[9]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.397ns  (logic 0.077ns (1.751%)  route 4.320ns (98.249%))
  Logic Levels:           0  
  Clock Path Skew:        -0.122ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.977ns = ( 8.979 - 6.001 ) 
    Source Clock Delay      (SCD):    2.580ns
    Clock Pessimism Removal (CPR):    -0.520ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.446ns (routing 0.415ns, distribution 1.031ns)
  Clock Net Delay (Destination): 1.284ns (routing 0.379ns, distribution 0.905ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.446     2.580    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X83Y15         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y15         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.657 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[9]/Q
                         net (fo=15, routed)          4.320     6.976    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_1[9]
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[9]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     6.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.424 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.464    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.464 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.813    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.443 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     7.671    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.695 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.284     8.979    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
                         clock pessimism             -0.520     8.459    
                         clock uncertainty           -0.068     8.390    
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_RIU_CLK_RIU_WR_DATA[9])
                                                      0.191     8.581    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          8.581    
                         arrival time                          -6.976    
  -------------------------------------------------------------------
                         slack                                  1.605    

Slack (MET) :             1.679ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[14]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        3.784ns  (logic 0.579ns (15.301%)  route 3.205ns (84.699%))
  Logic Levels:           5  (CARRY8=3 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.140ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.962ns = ( 8.963 - 6.001 ) 
    Source Clock Delay      (SCD):    2.583ns
    Clock Pessimism Removal (CPR):    -0.520ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.449ns (routing 0.415ns, distribution 1.034ns)
  Clock Net Delay (Destination): 1.269ns (routing 0.379ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.449     2.583    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X90Y2          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y2          FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.661 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/Q
                         net (fo=50, routed)          0.762     3.423    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X91Y8          LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     3.571 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.009     3.580    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/lopt_3
    SLICE_X91Y8          CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[7])
                                                      0.186     3.766 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     3.792    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X91Y9          CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
                                                      0.015     3.807 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     3.833    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[16].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X91Y10         CARRY8 (Prop_CARRY8_SLICEL_CI_O[0])
                                                      0.063     3.896 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[16].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[0]
                         net (fo=19, routed)          0.430     4.326    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Data_Addr[13]
    SLICE_X91Y5          LUT3 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.089     4.415 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[16]_INST_0/O
                         net (fo=17, routed)          1.952     6.367    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/addrb[13]
    RAMB36_X9Y14         RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[14]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     6.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.424 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.464    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.464 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.813    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.443 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     7.671    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.695 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.269     8.963    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/clkb
    RAMB36_X9Y14         RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.520     8.444    
                         clock uncertainty           -0.068     8.375    
    RAMB36_X9Y14         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[14])
                                                     -0.329     8.046    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.046    
                         arrival time                          -6.367    
  -------------------------------------------------------------------
                         slack                                  1.679    

Slack (MET) :             1.687ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[9]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        4.397ns  (logic 0.077ns (1.751%)  route 4.320ns (98.249%))
  Logic Levels:           0  
  Clock Path Skew:        -0.108ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.991ns = ( 8.993 - 6.001 ) 
    Source Clock Delay      (SCD):    2.580ns
    Clock Pessimism Removal (CPR):    -0.520ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.446ns (routing 0.415ns, distribution 1.031ns)
  Clock Net Delay (Destination): 1.298ns (routing 0.379ns, distribution 0.919ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.446     2.580    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X83Y15         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y15         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.657 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[9]/Q
                         net (fo=15, routed)          4.320     6.976    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_3[9]
    BITSLICE_CONTROL_X0Y13
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[9]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     6.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.424 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.464    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.464 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.813    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.443 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     7.671    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.695 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.298     8.993    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y13
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
                         clock pessimism             -0.520     8.473    
                         clock uncertainty           -0.068     8.404    
    BITSLICE_CONTROL_X0Y13
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_RIU_CLK_RIU_WR_DATA[9])
                                                      0.259     8.663    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          8.663    
                         arrival time                          -6.976    
  -------------------------------------------------------------------
                         slack                                  1.687    

Slack (MET) :             1.698ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[14]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        3.770ns  (logic 0.579ns (15.359%)  route 3.191ns (84.641%))
  Logic Levels:           5  (CARRY8=3 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.136ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.966ns = ( 8.967 - 6.001 ) 
    Source Clock Delay      (SCD):    2.583ns
    Clock Pessimism Removal (CPR):    -0.520ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.449ns (routing 0.415ns, distribution 1.034ns)
  Clock Net Delay (Destination): 1.273ns (routing 0.379ns, distribution 0.894ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.449     2.583    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X90Y2          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y2          FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.661 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/Q
                         net (fo=50, routed)          0.762     3.423    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X91Y8          LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     3.571 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.009     3.580    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/lopt_3
    SLICE_X91Y8          CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[7])
                                                      0.186     3.766 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     3.792    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X91Y9          CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
                                                      0.015     3.807 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     3.833    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[16].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X91Y10         CARRY8 (Prop_CARRY8_SLICEL_CI_O[0])
                                                      0.063     3.896 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[16].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[0]
                         net (fo=19, routed)          0.430     4.326    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Data_Addr[13]
    SLICE_X91Y5          LUT3 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.089     4.415 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[16]_INST_0/O
                         net (fo=17, routed)          1.937     6.352    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/addrb[13]
    RAMB36_X9Y12         RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[14]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     6.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.424 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.464    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.464 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.813    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.443 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     7.671    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.695 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.273     8.967    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/clkb
    RAMB36_X9Y12         RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.520     8.448    
                         clock uncertainty           -0.068     8.379    
    RAMB36_X9Y12         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[14])
                                                     -0.329     8.050    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[5].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.050    
                         arrival time                          -6.352    
  -------------------------------------------------------------------
                         slack                                  1.698    

Slack (MET) :             1.732ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_ilmb_cntlr/U0/No_ECC.lmb_as_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        3.829ns  (logic 0.434ns (11.333%)  route 3.395ns (88.667%))
  Logic Levels:           4  (LUT2=3 LUT6=1)
  Clock Path Skew:        -0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.995ns = ( 8.996 - 6.001 ) 
    Source Clock Delay      (SCD):    2.558ns
    Clock Pessimism Removal (CPR):    -0.467ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.424ns (routing 0.415ns, distribution 1.009ns)
  Clock Net Delay (Destination): 1.302ns (routing 0.379ns, distribution 0.923ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.424     2.558    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_ilmb_cntlr/U0/LMB_Clk
    SLICE_X92Y10         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_ilmb_cntlr/U0/No_ECC.lmb_as_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y10         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.639 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_ilmb_cntlr/U0/No_ECC.lmb_as_reg/Q
                         net (fo=1, routed)           0.154     2.793    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_ilmb_cntlr/U0/lmb_as
    SLICE_X92Y10         LUT2 (Prop_E5LUT_SLICEL_I0_O)
                                                      0.101     2.894 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_ilmb_cntlr/U0/Sl_Ready_INST_0/O
                         net (fo=33, routed)          0.549     3.443    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/Sl_Ready[1]
    SLICE_X92Y30         LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.110     3.553 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/LMB_Ready_INST_0/O
                         net (fo=80, routed)          0.781     4.334    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/IReady
    SLICE_X95Y8          LUT6 (Prop_A6LUT_SLICEL_I5_O)
                                                      0.090     4.424 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/I_AS_INST_0/O
                         net (fo=5, routed)           0.345     4.769    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/enb
    SLICE_X94Y12         LUT2 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.052     4.821 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram_i_2/O
                         net (fo=16, routed)          1.566     6.387    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/ENB_I
    RAMB36_X8Y9          RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     6.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.424 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.464    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.464 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.813    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.443 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     7.671    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.695 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.302     8.996    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/clkb
    RAMB36_X8Y9          RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.467     8.529    
                         clock uncertainty           -0.068     8.461    
    RAMB36_X8Y9          RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN)
                                                     -0.342     8.119    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[12].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.119    
                         arrival time                          -6.387    
  -------------------------------------------------------------------
                         slack                                  1.732    

Slack (MET) :             1.761ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_ilmb_cntlr/U0/No_ECC.lmb_as_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        3.715ns  (logic 0.434ns (11.684%)  route 3.281ns (88.316%))
  Logic Levels:           4  (LUT2=3 LUT6=1)
  Clock Path Skew:        -0.115ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.962ns = ( 8.963 - 6.001 ) 
    Source Clock Delay      (SCD):    2.558ns
    Clock Pessimism Removal (CPR):    -0.520ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.424ns (routing 0.415ns, distribution 1.009ns)
  Clock Net Delay (Destination): 1.269ns (routing 0.379ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.424     2.558    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_ilmb_cntlr/U0/LMB_Clk
    SLICE_X92Y10         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_ilmb_cntlr/U0/No_ECC.lmb_as_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y10         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.639 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_ilmb_cntlr/U0/No_ECC.lmb_as_reg/Q
                         net (fo=1, routed)           0.154     2.793    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_ilmb_cntlr/U0/lmb_as
    SLICE_X92Y10         LUT2 (Prop_E5LUT_SLICEL_I0_O)
                                                      0.101     2.894 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/second_ilmb_cntlr/U0/Sl_Ready_INST_0/O
                         net (fo=33, routed)          0.549     3.443    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/Sl_Ready[1]
    SLICE_X92Y30         LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.110     3.553 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/ilmb/U0/LMB_Ready_INST_0/O
                         net (fo=80, routed)          0.781     4.334    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/IReady
    SLICE_X95Y8          LUT6 (Prop_A6LUT_SLICEL_I5_O)
                                                      0.090     4.424 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Gen_Mux_Select_LUT6[2].Gen_Sel_DFF/I_AS_INST_0/O
                         net (fo=5, routed)           0.345     4.769    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/enb
    SLICE_X94Y12         LUT2 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.052     4.821 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[9].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram_i_2/O
                         net (fo=16, routed)          1.451     6.272    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/ENB_I
    RAMB36_X9Y14         RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ENBWREN
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     6.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.424 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.464    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.464 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.813    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.443 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     7.671    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.695 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.269     8.963    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/clkb
    RAMB36_X9Y14         RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.520     8.444    
                         clock uncertainty           -0.068     8.375    
    RAMB36_X9Y14         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ENBWREN)
                                                     -0.342     8.033    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.033    
                         arrival time                          -6.272    
  -------------------------------------------------------------------
                         slack                                  1.761    

Slack (MET) :             1.806ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[14].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[14]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        3.727ns  (logic 0.579ns (15.534%)  route 3.148ns (84.466%))
  Logic Levels:           5  (CARRY8=3 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.071ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.979ns = ( 8.980 - 6.001 ) 
    Source Clock Delay      (SCD):    2.583ns
    Clock Pessimism Removal (CPR):    -0.467ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.449ns (routing 0.415ns, distribution 1.034ns)
  Clock Net Delay (Destination): 1.286ns (routing 0.379ns, distribution 0.907ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.449     2.583    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X90Y2          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y2          FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.661 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/Q
                         net (fo=50, routed)          0.762     3.423    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X91Y8          LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     3.571 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.009     3.580    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/lopt_3
    SLICE_X91Y8          CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[7])
                                                      0.186     3.766 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     3.792    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X91Y9          CARRY8 (Prop_CARRY8_SLICEL_CI_CO[7])
                                                      0.015     3.807 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     3.833    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[16].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X91Y10         CARRY8 (Prop_CARRY8_SLICEL_CI_O[0])
                                                      0.063     3.896 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[16].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[0]
                         net (fo=19, routed)          0.430     4.326    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Data_Addr[13]
    SLICE_X91Y5          LUT3 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.089     4.415 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[16]_INST_0/O
                         net (fo=17, routed)          1.895     6.310    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[14].ram.r/prim_noinit.ram/addrb[13]
    RAMB36_X9Y10         RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[14].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[14]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     6.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.424 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.464    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.464 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.813    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.443 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     7.671    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.695 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.286     8.980    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[14].ram.r/prim_noinit.ram/clkb
    RAMB36_X9Y10         RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[14].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.467     8.513    
                         clock uncertainty           -0.068     8.445    
    RAMB36_X9Y10         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[14])
                                                     -0.329     8.116    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[14].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.116    
                         arrival time                          -6.310    
  -------------------------------------------------------------------
                         slack                                  1.806    

Slack (MET) :             1.807ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[4]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        3.642ns  (logic 0.522ns (14.333%)  route 3.120ns (85.667%))
  Logic Levels:           3  (CARRY8=1 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.140ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.962ns = ( 8.963 - 6.001 ) 
    Source Clock Delay      (SCD):    2.583ns
    Clock Pessimism Removal (CPR):    -0.520ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.449ns (routing 0.415ns, distribution 1.034ns)
  Clock Net Delay (Destination): 1.269ns (routing 0.379ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.449     2.583    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X90Y2          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y2          FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.661 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/Q
                         net (fo=50, routed)          0.762     3.423    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X91Y8          LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     3.571 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.009     3.580    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/lopt_3
    SLICE_X91Y8          CARRY8 (Prop_CARRY8_SLICEL_S[1]_O[6])
                                                      0.227     3.807 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/Using_FPGA.Native_CARRY4_CARRY8/O[6]
                         net (fo=27, routed)          0.387     4.194    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Data_Addr[3]
    SLICE_X92Y3          LUT3 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.069     4.263 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[26]_INST_0/O
                         net (fo=25, routed)          1.962     6.225    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/addrb[3]
    RAMB36_X9Y14         RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[4]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     6.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.424 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.464    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.464 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.813    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.443 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     7.671    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.695 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.269     8.963    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/clkb
    RAMB36_X9Y14         RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.520     8.444    
                         clock uncertainty           -0.068     8.375    
    RAMB36_X9Y14         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[4])
                                                     -0.343     8.032    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.032    
                         arrival time                          -6.225    
  -------------------------------------------------------------------
                         slack                                  1.807    

Slack (MET) :             1.867ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[13]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        3.635ns  (logic 0.645ns (17.742%)  route 2.990ns (82.258%))
  Logic Levels:           4  (CARRY8=2 LUT3=1 LUT6=1)
  Clock Path Skew:        -0.140ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.962ns = ( 8.963 - 6.001 ) 
    Source Clock Delay      (SCD):    2.583ns
    Clock Pessimism Removal (CPR):    -0.520ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.449ns (routing 0.415ns, distribution 1.034ns)
  Clock Net Delay (Destination): 1.269ns (routing 0.379ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.449     2.583    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X90Y2          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y2          FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.661 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/Q
                         net (fo=50, routed)          0.762     3.423    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X91Y8          LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     3.571 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.009     3.580    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/lopt_3
    SLICE_X91Y8          CARRY8 (Prop_CARRY8_SLICEL_S[1]_CO[7])
                                                      0.186     3.766 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/Using_FPGA.Native_CARRY4_CARRY8/CO[7]
                         net (fo=1, routed)           0.026     3.792    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/LO
    SLICE_X91Y9          CARRY8 (Prop_CARRY8_SLICEL_CI_O[7])
                                                      0.123     3.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[24].ALU_Bit_I1/Not_Last_Bit.MUXCY_XOR_I/Using_FPGA.Native_I1_CARRY4_CARRY8/O[7]
                         net (fo=27, routed)          0.476     4.391    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Data_Addr[12]
    SLICE_X91Y5          LUT3 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.110     4.501 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/jump_logic_I1/MUXCY_JUMP_CARRY6/Instr_Addr[17]_INST_0/O
                         net (fo=25, routed)          1.717     6.218    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/addrb[12]
    RAMB36_X9Y14         RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRBWRADDR[13]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     6.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.424 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.464    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.464 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.813    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.443 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     7.671    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.695 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.269     8.963    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/clkb
    RAMB36_X9Y14         RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKBWRCLK
                         clock pessimism             -0.520     8.444    
                         clock uncertainty           -0.068     8.375    
    RAMB36_X9Y14         RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKBWRCLK_ADDRBWRADDR[13])
                                                     -0.290     8.085    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[4].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.085    
                         arrival time                          -6.218    
  -------------------------------------------------------------------
                         slack                                  1.867    

Slack (MET) :             1.909ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[13].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRARDADDR[3]
                            (rising edge-triggered cell RAMB36E2 clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        3.604ns  (logic 0.466ns (12.930%)  route 3.138ns (87.070%))
  Logic Levels:           2  (CARRY8=1 LUT6=1)
  Clock Path Skew:        -0.082ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.968ns = ( 8.969 - 6.001 ) 
    Source Clock Delay      (SCD):    2.583ns
    Clock Pessimism Removal (CPR):    -0.467ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.449ns (routing 0.415ns, distribution 1.034ns)
  Clock Net Delay (Destination): 1.275ns (routing 0.379ns, distribution 0.896ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.449     2.583    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X90Y2          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y2          FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.661 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op2_reg[31]/Q
                         net (fo=50, routed)          0.762     3.423    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/I0
    SLICE_X91Y8          LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.148     3.571 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Using_FPGA.ALL_Bits[31].ALU_Bit_I1/Not_Last_Bit.I_ALU_LUT_V5/Using_FPGA.Native/LUT6/O
                         net (fo=1, routed)           0.009     3.580    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/lopt_3
    SLICE_X91Y8          CARRY8 (Prop_CARRY8_SLICEL_S[1]_O[5])
                                                      0.240     3.820 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/ALU_I/Use_Carry_Decoding.CarryIn_MUXCY/Using_FPGA.Native_CARRY4_CARRY8/O[5]
                         net (fo=27, routed)          2.367     6.187    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[13].ram.r/prim_noinit.ram/addra[2]
    RAMB36_X9Y8          RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[13].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/ADDRARDADDR[3]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     6.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.424 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.464    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.464 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.813    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.443 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     7.671    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.695 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.275     8.969    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[13].ram.r/prim_noinit.ram/clka
    RAMB36_X9Y8          RAMB36E2                                     r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[13].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram/CLKARDCLK
                         clock pessimism             -0.467     8.502    
                         clock uncertainty           -0.068     8.434    
    RAMB36_X9Y8          RAMB36E2 (Setup_RAMB36E2_RAMB36_CLKARDCLK_ADDRARDADDR[3])
                                                     -0.338     8.096    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/lmb_bram_I/U0/inst_blk_mem_gen/gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen/valid.cstr/ramloop[13].ram.r/prim_noinit.ram/DEVICE_8SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.SERIES8_TDP_SP36_NO_ECC_ATTR.ram
  -------------------------------------------------------------------
                         required time                          8.096    
                         arrival time                          -6.187    
  -------------------------------------------------------------------
                         slack                                  1.909    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.021ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.173ns  (logic 0.058ns (33.526%)  route 0.115ns (66.474%))
  Logic Levels:           0  
  Clock Path Skew:        0.092ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.582ns
    Source Clock Delay      (SCD):    2.959ns
    Clock Pessimism Removal (CPR):    -0.469ns
  Clock Net Delay (Source):      1.266ns (routing 0.379ns, distribution 0.887ns)
  Clock Net Delay (Destination): 1.448ns (routing 0.415ns, distribution 1.033ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     1.669    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.693 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.266     2.959    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X86Y15         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y15         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.058     3.017 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.IO_Write_Data_reg[9]/Q
                         net (fo=1, routed)           0.115     3.132    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_ub[9]
    SLICE_X85Y14         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.448     2.582    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X85Y14         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[9]/C
                         clock pessimism              0.469     3.051    
    SLICE_X85Y14         FDRE (Hold_GFF_SLICEL_C_D)
                                                      0.060     3.111    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[9]
  -------------------------------------------------------------------
                         required time                         -3.111    
                         arrival time                           3.132    
  -------------------------------------------------------------------
                         slack                                  0.021    

Slack (MET) :             0.022ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_logic_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk_rst_r1_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.075ns  (logic 0.039ns (52.106%)  route 0.036ns (47.894%))
  Logic Levels:           0  
  Clock Path Skew:        0.006ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.447ns
    Source Clock Delay      (SCD):    1.707ns
    Clock Pessimism Removal (CPR):    -0.267ns
  Clock Net Delay (Source):      0.771ns (routing 0.230ns, distribution 0.541ns)
  Clock Net Delay (Destination): 0.873ns (routing 0.255ns, distribution 0.618ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.771     1.707    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X95Y78         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_logic_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y78         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.746 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_logic_r1_reg/Q
                         net (fo=2, routed)           0.036     1.782    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk_rst
    SLICE_X95Y78         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk_rst_r1_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.873     1.447    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X95Y78         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk_rst_r1_reg/C
                         clock pessimism              0.267     1.713    
    SLICE_X95Y78         FDRE (Hold_BFF2_SLICEL_C_D)
                                                      0.047     1.760    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk_rst_r1_reg
  -------------------------------------------------------------------
                         required time                         -1.760    
                         arrival time                           1.782    
  -------------------------------------------------------------------
                         slack                                  0.022    

Slack (MET) :             0.026ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op3_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[10].mem_Rd_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.196ns  (logic 0.058ns (29.560%)  route 0.138ns (70.440%))
  Logic Levels:           0  
  Clock Path Skew:        0.108ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.607ns
    Source Clock Delay      (SCD):    2.968ns
    Clock Pessimism Removal (CPR):    -0.470ns
  Clock Net Delay (Source):      1.275ns (routing 0.379ns, distribution 0.896ns)
  Clock Net Delay (Destination): 1.473ns (routing 0.415ns, distribution 1.058ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     1.669    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.693 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.275     2.968    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X86Y10         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op3_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y10         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     3.026 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op3_reg[10]/Q
                         net (fo=2, routed)           0.138     3.164    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Q[21]
    SLICE_X85Y8          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[10].mem_Rd_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.473     2.607    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Clk
    SLICE_X85Y8          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[10].mem_Rd_reg[10]/C
                         clock pessimism              0.470     3.076    
    SLICE_X85Y8          FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.062     3.138    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[10].mem_Rd_reg[10]
  -------------------------------------------------------------------
                         required time                         -3.138    
                         arrival time                           3.164    
  -------------------------------------------------------------------
                         slack                                  0.026    

Slack (MET) :             0.030ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.100ns  (logic 0.039ns (39.000%)  route 0.061ns (61.000%))
  Logic Levels:           0  
  Clock Path Skew:        0.023ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.474ns
    Source Clock Delay      (SCD):    1.723ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Net Delay (Source):      0.787ns (routing 0.230ns, distribution 0.557ns)
  Clock Net Delay (Destination): 0.900ns (routing 0.255ns, distribution 0.645ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.787     1.723    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X88Y36         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y36         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.762 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[9]/Q
                         net (fo=1, routed)           0.061     1.823    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/IO_Read_Data[9]
    SLICE_X88Y33         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.900     1.474    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Clk
    SLICE_X88Y33         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[9]/C
                         clock pessimism              0.273     1.747    
    SLICE_X88Y33         FDRE (Hold_GFF2_SLICEL_C_D)
                                                      0.047     1.794    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/iomodule_0/U0/Using_IO_Bus.io_bus_read_data_reg[9]
  -------------------------------------------------------------------
                         required time                         -1.794    
                         arrival time                           1.823    
  -------------------------------------------------------------------
                         slack                                  0.030    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/ex_hold_div_overflow_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/MEM_Div_Overflow_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.128ns  (logic 0.053ns (41.376%)  route 0.075ns (58.624%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.477ns
    Source Clock Delay      (SCD):    1.728ns
    Clock Pessimism Removal (CPR):    -0.302ns
  Clock Net Delay (Source):      0.792ns (routing 0.230ns, distribution 0.562ns)
  Clock Net Delay (Destination): 0.903ns (routing 0.255ns, distribution 0.648ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.792     1.728    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X92Y12         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/ex_hold_div_overflow_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y12         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.767 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/ex_hold_div_overflow_reg/Q
                         net (fo=2, routed)           0.051     1.818    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Using_Div_Unit.Div_unit_I1/ex_hold_div_overflow
    SLICE_X93Y12         LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.014     1.832 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/MEM_Div_Overflow_i_1/O
                         net (fo=1, routed)           0.024     1.856    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/MEM_Div_Overflow_reg_1
    SLICE_X93Y12         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/MEM_Div_Overflow_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.903     1.477    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X93Y12         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/MEM_Div_Overflow_reg/C
                         clock pessimism              0.302     1.779    
    SLICE_X93Y12         FDRE (Hold_FFF_SLICEM_C_D)
                                                      0.046     1.825    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/MEM_Div_Overflow_reg
  -------------------------------------------------------------------
                         required time                         -1.825    
                         arrival time                           1.856    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.033ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/FPGA_Shift.cnt_shifts_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/last_cycle_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.155ns  (logic 0.060ns (38.609%)  route 0.095ns (61.391%))
  Logic Levels:           0  
  Clock Path Skew:        0.061ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.555ns
    Source Clock Delay      (SCD):    2.963ns
    Clock Pessimism Removal (CPR):    -0.469ns
  Clock Net Delay (Source):      1.270ns (routing 0.379ns, distribution 0.891ns)
  Clock Net Delay (Destination): 1.421ns (routing 0.415ns, distribution 1.006ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     1.669    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.693 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.270     2.963    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X94Y6          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/FPGA_Shift.cnt_shifts_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y6          FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.060     3.023 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/FPGA_Shift.cnt_shifts_reg[0]/Q
                         net (fo=2, routed)           0.095     3.119    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/div_count_is_2
    SLICE_X93Y6          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/last_cycle_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.421     2.555    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/Clk
    SLICE_X93Y6          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/last_cycle_reg/C
                         clock pessimism              0.469     3.024    
    SLICE_X93Y6          FDRE (Hold_EFF2_SLICEM_C_D)
                                                      0.062     3.086    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Using_Div_Unit.Div_unit_I1/last_cycle_reg
  -------------------------------------------------------------------
                         required time                         -3.086    
                         arrival time                           3.119    
  -------------------------------------------------------------------
                         slack                                  0.033    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Instruction_Prefetch_Mux[7].Gen_Instr_DFF/Using_FPGA.Native/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.101ns  (logic 0.039ns (38.474%)  route 0.062ns (61.526%))
  Logic Levels:           0  
  Clock Path Skew:        0.020ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.483ns
    Source Clock Delay      (SCD):    1.736ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Net Delay (Source):      0.800ns (routing 0.230ns, distribution 0.570ns)
  Clock Net Delay (Destination): 0.909ns (routing 0.255ns, distribution 0.654ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.800     1.736    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Instruction_Prefetch_Mux[7].Gen_Instr_DFF/Clk
    SLICE_X95Y12         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Instruction_Prefetch_Mux[7].Gen_Instr_DFF/Using_FPGA.Native/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y12         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.775 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/PreFetch_Buffer_I1/Instruction_Prefetch_Mux[7].Gen_Instr_DFF/Using_FPGA.Native/Q
                         net (fo=42, routed)          0.062     1.837    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/of_gpr_op3_rd_addr[1]
    SLICE_X95Y11         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.909     1.483    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X95Y11         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[1]/C
                         clock pessimism              0.273     1.756    
    SLICE_X95Y11         FDRE (Hold_HFF2_SLICEL_C_D)
                                                      0.047     1.803    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/ex_gpr_write_addr_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.803    
                         arrival time                           1.837    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.034ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/wb_gpr_write_addr_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.143ns  (logic 0.060ns (41.840%)  route 0.083ns (58.160%))
  Logic Levels:           0  
  Clock Path Skew:        0.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.590ns
    Source Clock Delay      (SCD):    2.962ns
    Clock Pessimism Removal (CPR):    -0.421ns
  Clock Net Delay (Source):      1.269ns (routing 0.379ns, distribution 0.890ns)
  Clock Net Delay (Destination): 1.456ns (routing 0.415ns, distribution 1.041ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     1.669    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.693 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.269     2.962    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X94Y10         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y10         FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.060     3.022 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr_reg[2]/Q
                         net (fo=8, routed)           0.083     3.106    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/mem_gpr_write_addr[2]
    SLICE_X94Y8          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/wb_gpr_write_addr_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.456     2.590    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/Clk
    SLICE_X94Y8          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/wb_gpr_write_addr_reg[2]/C
                         clock pessimism              0.421     3.011    
    SLICE_X94Y8          FDRE (Hold_DFF2_SLICEM_C_D)
                                                      0.061     3.072    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Decode_I/wb_gpr_write_addr_reg[2]
  -------------------------------------------------------------------
                         required time                         -3.072    
                         arrival time                           3.106    
  -------------------------------------------------------------------
                         slack                                  0.034    

Slack (MET) :             0.036ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[27].sync_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[27]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.133ns  (logic 0.053ns (39.850%)  route 0.080ns (60.150%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.051ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.474ns
    Source Clock Delay      (SCD):    1.725ns
    Clock Pessimism Removal (CPR):    -0.302ns
  Clock Net Delay (Source):      0.789ns (routing 0.230ns, distribution 0.559ns)
  Clock Net Delay (Destination): 0.900ns (routing 0.255ns, distribution 0.645ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.789     1.725    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X90Y35         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[27].sync_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y35         FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     1.764 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[27].sync_reg_reg[1]/Q
                         net (fo=1, routed)           0.056     1.820    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_riuclk[27]
    SLICE_X89Y35         LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.014     1.834 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub[27]_i_1/O
                         net (fo=1, routed)           0.024     1.858    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_mux[27]
    SLICE_X89Y35         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[27]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.900     1.474    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X89Y35         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[27]/C
                         clock pessimism              0.302     1.776    
    SLICE_X89Y35         FDRE (Hold_CFF_SLICEM_C_D)
                                                      0.046     1.822    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_read_data_ub_reg[27]
  -------------------------------------------------------------------
                         required time                         -1.822    
                         arrival time                           1.858    
  -------------------------------------------------------------------
                         slack                                  0.036    

Slack (MET) :             0.041ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op3_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[18].mem_Rd_reg[18]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout6 rise@0.000ns)
  Data Path Delay:        0.109ns  (logic 0.038ns (34.964%)  route 0.071ns (65.036%))
  Logic Levels:           0  
  Clock Path Skew:        0.021ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.483ns
    Source Clock Delay      (SCD):    1.734ns
    Clock Pessimism Removal (CPR):    -0.273ns
  Clock Net Delay (Source):      0.798ns (routing 0.230ns, distribution 0.568ns)
  Clock Net Delay (Destination): 0.909ns (routing 0.255ns, distribution 0.654ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.798     1.734    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/Clk
    SLICE_X89Y7          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op3_reg[18]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y7          FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.772 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Operand_Select_I/EX_Op3_reg[18]/Q
                         net (fo=3, routed)           0.071     1.843    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Q[13]
    SLICE_X89Y6          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[18].mem_Rd_reg[18]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.909     1.483    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Clk
    SLICE_X89Y6          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[18].mem_Rd_reg[18]/C
                         clock pessimism              0.273     1.756    
    SLICE_X89Y6          FDRE (Hold_HFF_SLICEM_C_D)
                                                      0.046     1.802    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Performance.Core/Data_Flow_I/Barrel_Shifter_I/Use_HW_BS.Using_BitField.Gen_Bits[18].mem_Rd_reg[18]
  -------------------------------------------------------------------
                         required time                         -1.802    
                         arrival time                           1.843    
  -------------------------------------------------------------------
                         slack                                  0.041    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         mmcm_clkout6
Waveform(ns):       { 0.000 3.001 }
Period(ns):         6.001
Sources:            { d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6 }

Check Type        Corner  Lib Pin                   Reference Pin             Required(ns)  Actual(ns)  Slack(ns)  Location                Pin
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y1   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y3   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y4   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y5   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y6   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y7   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y8   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[4].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Min Period        n/a     BITSLICE_CONTROL/RIU_CLK  n/a                       3.846         6.001       2.155      BITSLICE_CONTROL_X0Y10  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y1   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y1   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y3   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y3   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y4   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Low Pulse Width   Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y4   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y1   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y1   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y3   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y3   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Slow    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y4   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
High Pulse Width  Fast    BITSLICE_CONTROL/RIU_CLK  n/a                       1.731         3.001       1.270      BITSLICE_CONTROL_X0Y4   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.800       1.018      BITSLICE_CONTROL_X0Y1   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.796       1.022      BITSLICE_CONTROL_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.793       1.025      BITSLICE_CONTROL_X0Y2   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.793       1.025      BITSLICE_CONTROL_X0Y7   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.791       1.027      BITSLICE_CONTROL_X0Y3   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.791       1.027      BITSLICE_CONTROL_X0Y5   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.790       1.028      BITSLICE_CONTROL_X0Y6   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Fast    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.786       1.032      BITSLICE_CONTROL_X0Y4   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Slow    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.432       1.386      BITSLICE_CONTROL_X0Y1   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK
Max Skew          Slow    BITSLICE_CONTROL/RIU_CLK  BITSLICE_CONTROL/PLL_CLK  1.818         0.425       1.393      BITSLICE_CONTROL_X0Y0   d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK



---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       11.414ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             11.414ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.613ns  (logic 0.079ns (12.887%)  route 0.534ns (87.113%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y63                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
    SLICE_X103Y63        FDCE (Prop_FFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.534     0.613    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
    SLICE_X103Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X103Y62        FDCE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.613    
  -------------------------------------------------------------------
                         slack                                 11.414    

Slack (MET) :             11.609ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.418ns  (logic 0.079ns (18.900%)  route 0.339ns (81.100%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y64                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
    SLICE_X106Y64        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.339     0.418    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
    SLICE_X106Y63        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X106Y63        FDCE (Setup_BFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.418    
  -------------------------------------------------------------------
                         slack                                 11.609    

Slack (MET) :             11.686ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.341ns  (logic 0.079ns (23.167%)  route 0.262ns (76.833%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y62                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
    SLICE_X106Y62        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.262     0.341    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
    SLICE_X106Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X106Y62        FDCE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.341    
  -------------------------------------------------------------------
                         slack                                 11.686    

Slack (MET) :             11.690ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.337ns  (logic 0.079ns (23.442%)  route 0.258ns (76.558%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y62                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
    SLICE_X102Y62        FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.258     0.337    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
    SLICE_X102Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X102Y62        FDCE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.337    
  -------------------------------------------------------------------
                         slack                                 11.690    

Slack (MET) :             11.741ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.286ns  (logic 0.079ns (27.622%)  route 0.207ns (72.378%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y62                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
    SLICE_X106Y62        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.207     0.286    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X106Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X106Y62        FDCE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.286    
  -------------------------------------------------------------------
                         slack                                 11.741    

Slack (MET) :             11.775ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.252ns  (logic 0.076ns (30.159%)  route 0.176ns (69.841%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y63                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
    SLICE_X103Y63        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.176     0.252    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
    SLICE_X103Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X103Y62        FDCE (Setup_GFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.252    
  -------------------------------------------------------------------
                         slack                                 11.775    

Slack (MET) :             11.780ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.247ns  (logic 0.079ns (31.984%)  route 0.168ns (68.016%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y63                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
    SLICE_X103Y63        FDCE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.168     0.247    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X103Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X103Y62        FDCE (Setup_BFF2_SLICEM_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.247    
  -------------------------------------------------------------------
                         slack                                 11.780    

Slack (MET) :             11.799ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.002ns  (MaxDelay Path 12.002ns)
  Data Path Delay:        0.228ns  (logic 0.081ns (35.526%)  route 0.147ns (64.474%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.002ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y64                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
    SLICE_X106Y64        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.147     0.228    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X106Y63        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.002    12.002    
    SLICE_X106Y63        FDCE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    12.027    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         12.027    
                         arrival time                          -0.228    
  -------------------------------------------------------------------
                         slack                                 11.799    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        2.056ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.056ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.969ns  (logic 0.079ns (8.153%)  route 0.890ns (91.847%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y69                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/C
    SLICE_X91Y69         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[2]/Q
                         net (fo=1, routed)           0.890     0.969    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[2]
    SLICE_X91Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X91Y69         FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[2].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.969    
  -------------------------------------------------------------------
                         slack                                  2.056    

Slack (MET) :             2.213ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.812ns  (logic 0.079ns (9.729%)  route 0.733ns (90.271%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y70                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/C
    SLICE_X91Y70         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[0]/Q
                         net (fo=1, routed)           0.733     0.812    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[0]
    SLICE_X90Y65         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X90Y65         FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.812    
  -------------------------------------------------------------------
                         slack                                  2.213    

Slack (MET) :             2.377ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.648ns  (logic 0.080ns (12.346%)  route 0.568ns (87.654%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y69                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/C
    SLICE_X91Y69         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[3]/Q
                         net (fo=1, routed)           0.568     0.648    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[3]
    SLICE_X96Y57         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X96Y57         FDRE (Setup_CFF_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[3].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.648    
  -------------------------------------------------------------------
                         slack                                  2.377    

Slack (MET) :             2.389ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.636ns  (logic 0.079ns (12.421%)  route 0.557ns (87.579%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y70                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[5]/C
    SLICE_X92Y70         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[5]/Q
                         net (fo=1, routed)           0.557     0.636    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[5]
    SLICE_X96Y57         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X96Y57         FDRE (Setup_BFF_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.636    
  -------------------------------------------------------------------
                         slack                                  2.389    

Slack (MET) :             2.422ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.603ns  (logic 0.079ns (13.101%)  route 0.524ns (86.899%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y69                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/C
    SLICE_X92Y69         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[6]/Q
                         net (fo=1, routed)           0.524     0.603    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[6]
    SLICE_X92Y64         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y64         FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.603    
  -------------------------------------------------------------------
                         slack                                  2.422    

Slack (MET) :             2.467ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[13].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.558ns  (logic 0.081ns (14.516%)  route 0.477ns (85.484%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y80                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/C
    SLICE_X95Y80         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[13]/Q
                         net (fo=1, routed)           0.477     0.558    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[13]
    SLICE_X92Y82         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[13].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y82         FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[13].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.558    
  -------------------------------------------------------------------
                         slack                                  2.467    

Slack (MET) :             2.496ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.529ns  (logic 0.081ns (15.312%)  route 0.448ns (84.688%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y70                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[5]/C
    SLICE_X91Y70         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[5]/Q
                         net (fo=1, routed)           0.448     0.529    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[5]
    SLICE_X91Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X91Y70         FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.529    
  -------------------------------------------------------------------
                         slack                                  2.496    

Slack (MET) :             2.522ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.503ns  (logic 0.079ns (15.706%)  route 0.424ns (84.294%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y67                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[1]/C
    SLICE_X92Y67         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[1]/Q
                         net (fo=1, routed)           0.424     0.503    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[1]
    SLICE_X90Y66         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X90Y66         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.503    
  -------------------------------------------------------------------
                         slack                                  2.522    

Slack (MET) :             2.549ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.476ns  (logic 0.081ns (17.017%)  route 0.395ns (82.983%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y72                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[4]/C
    SLICE_X91Y72         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[4]/Q
                         net (fo=1, routed)           0.395     0.476    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[4]
    SLICE_X90Y72         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X90Y72         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[4].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.476    
  -------------------------------------------------------------------
                         slack                                  2.549    

Slack (MET) :             2.567ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_we_r_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.458ns  (logic 0.078ns (17.031%)  route 0.380ns (82.969%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y70                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_we_r_reg/C
    SLICE_X96Y70         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_we_r_reg/Q
                         net (fo=1, routed)           0.380     0.458    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/D[0]
    SLICE_X92Y68         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X92Y68         FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_we_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.458    
  -------------------------------------------------------------------
                         slack                                  2.567    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout0

Setup :            0  Failing Endpoints,  Worst Slack        1.557ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.557ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[22].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.468ns  (logic 0.078ns (5.313%)  route 1.390ns (94.687%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y15                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/C
    SLICE_X90Y15         FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[22]/Q
                         net (fo=52, routed)          1.390     1.468    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[22]
    SLICE_X91Y39         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[22].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X91Y39         FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[22].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.468    
  -------------------------------------------------------------------
                         slack                                  1.557    

Slack (MET) :             1.969ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_riuclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_i_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.056ns  (logic 0.079ns (7.481%)  route 0.977ns (92.519%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y63                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_riuclk_reg/C
    SLICE_X81Y63         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_riuclk_reg/Q
                         net (fo=1, routed)           0.977     1.056    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_riuclk
    SLICE_X81Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_i_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X81Y69         FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_i_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.056    
  -------------------------------------------------------------------
                         slack                                  1.969    

Slack (MET) :             1.971ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        1.054ns  (logic 0.080ns (7.593%)  route 0.974ns (92.407%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y15                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[5]/C
    SLICE_X91Y15         FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[5]/Q
                         net (fo=29, routed)          0.974     1.054    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[5]
    SLICE_X90Y40         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X90Y40         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -1.054    
  -------------------------------------------------------------------
                         slack                                  1.971    

Slack (MET) :             2.039ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.986ns  (logic 0.080ns (8.116%)  route 0.906ns (91.884%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y15                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[7]/C
    SLICE_X91Y15         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[7]/Q
                         net (fo=42, routed)          0.906     0.986    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[7]
    SLICE_X89Y40         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X89Y40         FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[7].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.986    
  -------------------------------------------------------------------
                         slack                                  2.039    

Slack (MET) :             2.109ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[13].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.916ns  (logic 0.076ns (8.296%)  route 0.840ns (91.704%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y11                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[13]/C
    SLICE_X94Y11         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[13]/Q
                         net (fo=35, routed)          0.840     0.916    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[13]
    SLICE_X86Y13         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[13].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X86Y13         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[13].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.916    
  -------------------------------------------------------------------
                         slack                                  2.109    

Slack (MET) :             2.110ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[18].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.915ns  (logic 0.078ns (8.524%)  route 0.837ns (91.476%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y15                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[18]/C
    SLICE_X90Y15         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[18]/Q
                         net (fo=4, routed)           0.837     0.915    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[18]
    SLICE_X90Y39         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[18].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X90Y39         FDRE (Setup_HFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[18].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.915    
  -------------------------------------------------------------------
                         slack                                  2.110    

Slack (MET) :             2.117ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[15].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.908ns  (logic 0.081ns (8.916%)  route 0.827ns (91.084%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y15                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[15]/C
    SLICE_X91Y15         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[15]/Q
                         net (fo=33, routed)          0.827     0.908    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[15]
    SLICE_X93Y33         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[15].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X93Y33         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[15].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.908    
  -------------------------------------------------------------------
                         slack                                  2.117    

Slack (MET) :             2.140ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[14].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.885ns  (logic 0.079ns (8.931%)  route 0.806ns (91.069%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y15                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[14]/C
    SLICE_X90Y15         FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[14]/Q
                         net (fo=39, routed)          0.806     0.885    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[14]
    SLICE_X89Y15         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[14].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X89Y15         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[14].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.885    
  -------------------------------------------------------------------
                         slack                                  2.140    

Slack (MET) :             2.153ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.872ns  (logic 0.079ns (9.062%)  route 0.793ns (90.938%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y15                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[6]/C
    SLICE_X91Y15         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[6]/Q
                         net (fo=28, routed)          0.793     0.872    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[6]
    SLICE_X90Y43         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X90Y43         FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.872    
  -------------------------------------------------------------------
                         slack                                  2.153    

Slack (MET) :             2.166ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[16].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             mmcm_clkout0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.000ns  (MaxDelay Path 3.000ns)
  Data Path Delay:        0.859ns  (logic 0.076ns (8.844%)  route 0.783ns (91.156%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 3.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y15                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[16]/C
    SLICE_X90Y15         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     0.076 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[16]/Q
                         net (fo=41, routed)          0.783     0.859    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[16]
    SLICE_X88Y18         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[16].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    3.000     3.000    
    SLICE_X88Y18         FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025     3.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[16].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          3.025    
                         arrival time                          -0.859    
  -------------------------------------------------------------------
                         slack                                  2.166    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[0]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.754ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.505ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.754ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.615ns  (logic 0.079ns (4.892%)  route 1.536ns (95.108%))
  Logic Levels:           0  
  Clock Path Skew:        -0.434ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.608ns = ( 5.609 - 3.001 ) 
    Source Clock Delay      (SCD):    2.565ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.448ns (routing 0.415ns, distribution 1.033ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.448     2.565    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[0]_0
    SLICE_X91Y53         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y53         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.644 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[4]/Q
                         net (fo=1, routed)           1.536     4.180    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[4]
    BITSLICE_RX_TX_X0Y9  RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.141     5.822    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.192 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.102     5.294    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     5.400 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.475 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y1
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.122     5.597 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     5.609    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y9  RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.477     5.132    
                         clock uncertainty           -0.170     4.962    
    BITSLICE_RX_TX_X0Y9  RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                     -0.028     4.934    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.934    
                         arrival time                          -4.180    
  -------------------------------------------------------------------
                         slack                                  0.754    

Slack (MET) :             0.770ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.597ns  (logic 0.079ns (4.947%)  route 1.518ns (95.053%))
  Logic Levels:           0  
  Clock Path Skew:        -0.415ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.632ns = ( 5.633 - 3.001 ) 
    Source Clock Delay      (SCD):    2.570ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.453ns (routing 0.415ns, distribution 1.038ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.453     2.570    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[13]_0
    SLICE_X91Y54         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y54         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     2.649 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           1.518     4.167    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y5  RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.141     5.822    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.192 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.103     5.295    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.412 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.487 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.131     5.618 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     5.633    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y5  RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.477     5.156    
                         clock uncertainty           -0.170     4.986    
    BITSLICE_RX_TX_X0Y5  RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                     -0.049     4.937    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.937    
                         arrival time                          -4.167    
  -------------------------------------------------------------------
                         slack                                  0.770    

Slack (MET) :             0.774ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.631ns  (logic 0.079ns (4.844%)  route 1.552ns (95.156%))
  Logic Levels:           0  
  Clock Path Skew:        -0.415ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.632ns = ( 5.633 - 3.001 ) 
    Source Clock Delay      (SCD):    2.570ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.453ns (routing 0.415ns, distribution 1.038ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.453     2.570    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[13]_0
    SLICE_X91Y55         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y55         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     2.649 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[3]/Q
                         net (fo=1, routed)           1.552     4.201    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[3]
    BITSLICE_RX_TX_X0Y5  RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.141     5.822    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.192 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.103     5.295    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.412 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.487 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.131     5.618 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     5.633    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y5  RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.477     5.156    
                         clock uncertainty           -0.170     4.986    
    BITSLICE_RX_TX_X0Y5  RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.011     4.975    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.975    
                         arrival time                          -4.201    
  -------------------------------------------------------------------
                         slack                                  0.774    

Slack (MET) :             0.776ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.614ns  (logic 0.079ns (4.895%)  route 1.535ns (95.105%))
  Logic Levels:           0  
  Clock Path Skew:        -0.421ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.628ns = ( 5.629 - 3.001 ) 
    Source Clock Delay      (SCD):    2.572ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.455ns (routing 0.415ns, distribution 1.040ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.455     2.572    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[0]_0
    SLICE_X88Y48         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y48         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.651 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[3].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[7]/Q
                         net (fo=1, routed)           1.535     4.186    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[7]
    BITSLICE_RX_TX_X0Y2  RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.141     5.822    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.192 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.103     5.295    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.412 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.487 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     5.616 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.629    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y2  RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.477     5.152    
                         clock uncertainty           -0.170     4.982    
    BITSLICE_RX_TX_X0Y2  RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.020     4.962    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.962    
                         arrival time                          -4.186    
  -------------------------------------------------------------------
                         slack                                  0.776    

Slack (MET) :             0.777ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.513ns  (logic 0.079ns (5.221%)  route 1.434ns (94.779%))
  Logic Levels:           0  
  Clock Path Skew:        -0.456ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.623ns = ( 5.624 - 3.001 ) 
    Source Clock Delay      (SCD):    2.556ns
    Clock Pessimism Removal (CPR):    -0.524ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.439ns (routing 0.415ns, distribution 1.024ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.439     2.556    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[0]_0
    SLICE_X81Y65         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y65         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.635 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[3].u_ddr_mc_wr_bit/dReg_reg[7]/Q
                         net (fo=1, routed)           1.434     4.069    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[7]
    BITSLICE_RX_TX_X0Y17 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.141     5.822    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.192 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.100     5.292    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.484 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.127     5.611 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.013     5.624    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y17 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.524     5.100    
                         clock uncertainty           -0.170     4.930    
    BITSLICE_RX_TX_X0Y17 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.084     4.846    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.846    
                         arrival time                          -4.069    
  -------------------------------------------------------------------
                         slack                                  0.777    

Slack (MET) :             0.785ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.537ns  (logic 0.077ns (5.010%)  route 1.460ns (94.990%))
  Logic Levels:           0  
  Clock Path Skew:        -0.490ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.603ns = ( 5.604 - 3.001 ) 
    Source Clock Delay      (SCD):    2.570ns
    Clock Pessimism Removal (CPR):    -0.524ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.453ns (routing 0.415ns, distribution 1.038ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.453     2.570    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[0]_0
    SLICE_X87Y60         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X87Y60         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.647 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[7].u_ddr_mc_wr_bit/dReg_reg[6]/Q
                         net (fo=1, routed)           1.460     4.107    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[6]
    BITSLICE_RX_TX_X0Y22 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.141     5.822    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.192 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.097     5.289    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     5.395 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.470 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.122     5.592 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     5.604    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y22 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.524     5.080    
                         clock uncertainty           -0.170     4.910    
    BITSLICE_RX_TX_X0Y22 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                     -0.018     4.892    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.892    
                         arrival time                          -4.107    
  -------------------------------------------------------------------
                         slack                                  0.785    

Slack (MET) :             0.790ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.579ns  (logic 0.077ns (4.877%)  route 1.502ns (95.123%))
  Logic Levels:           0  
  Clock Path Skew:        -0.449ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.624ns = ( 5.625 - 3.001 ) 
    Source Clock Delay      (SCD):    2.596ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.479ns (routing 0.415ns, distribution 1.064ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.479     2.596    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[0]_0
    SLICE_X83Y51         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y51         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.673 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[0].u_ddr_mc_wr_byte/genBit[1].u_ddr_mc_wr_bit/dReg_reg[5]/Q
                         net (fo=1, routed)           1.502     4.175    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[5]
    BITSLICE_RX_TX_X0Y28 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.141     5.822    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.192 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.099     5.291    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y4
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.408 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y4
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.483 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y4
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     5.612 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.625    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y28 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.477     5.148    
                         clock uncertainty           -0.170     4.977    
    BITSLICE_RX_TX_X0Y28 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                     -0.013     4.964    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[2].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.964    
                         arrival time                          -4.175    
  -------------------------------------------------------------------
                         slack                                  0.790    

Slack (MET) :             0.790ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.544ns  (logic 0.079ns (5.117%)  route 1.465ns (94.883%))
  Logic Levels:           0  
  Clock Path Skew:        -0.448ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.606ns = ( 5.607 - 3.001 ) 
    Source Clock Delay      (SCD):    2.577ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.460ns (routing 0.415ns, distribution 1.045ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.460     2.577    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[13]_2
    SLICE_X88Y17         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y17         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.656 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/u_ddr_mc_wr_dm/dReg_reg[1]/Q
                         net (fo=1, routed)           1.465     4.121    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[1]
    BITSLICE_RX_TX_X0Y13 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.141     5.822    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.192 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.100     5.292    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.484 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.109     5.593 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.014     5.607    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y13 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.477     5.130    
                         clock uncertainty           -0.170     4.960    
    BITSLICE_RX_TX_X0Y13 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                     -0.049     4.911    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.911    
                         arrival time                          -4.121    
  -------------------------------------------------------------------
                         slack                                  0.790    

Slack (MET) :             0.790ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rdEn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.442ns  (logic 0.079ns (5.479%)  route 1.363ns (94.522%))
  Logic Levels:           0  
  Clock Path Skew:        -0.554ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.486ns = ( 5.487 - 3.001 ) 
    Source Clock Delay      (SCD):    2.563ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.446ns (routing 0.415ns, distribution 1.031ns)
  Clock Net Delay (Destination): 1.141ns (routing 0.379ns, distribution 0.762ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.446     2.563    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rsMask_reg[6][9]_0
    SLICE_X88Y25         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rdEn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y25         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.642 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_upp/rdEn_reg[0]/Q
                         net (fo=1, routed)           1.363     4.005    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_upp[0]
    BITSLICE_CONTROL_X0Y7
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.141     5.822    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.192 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.105     5.297    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y7
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.112     5.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y7
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.078     5.487 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism             -0.477     5.010    
                         clock uncertainty           -0.170     4.840    
    BITSLICE_CONTROL_X0Y7
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[0])
                                                     -0.045     4.795    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          4.795    
                         arrival time                          -4.005    
  -------------------------------------------------------------------
                         slack                                  0.790    

Slack (MET) :             0.790ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[0]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.526ns  (logic 0.078ns (5.111%)  route 1.448ns (94.889%))
  Logic Levels:           0  
  Clock Path Skew:        -0.464ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.623ns = ( 5.624 - 3.001 ) 
    Source Clock Delay      (SCD):    2.564ns
    Clock Pessimism Removal (CPR):    -0.524ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.447ns (routing 0.415ns, distribution 1.032ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.447     2.564    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[13]_2
    SLICE_X82Y65         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y65         FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     2.642 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[2]/Q
                         net (fo=1, routed)           1.448     4.090    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[2]
    BITSLICE_RX_TX_X0Y16 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.141     5.822    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.192 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.100     5.292    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.409 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.484 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.128     5.612 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.012     5.624    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y16 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.524     5.100    
                         clock uncertainty           -0.170     4.930    
    BITSLICE_RX_TX_X0Y16 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                     -0.050     4.880    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.880    
                         arrival time                          -4.090    
  -------------------------------------------------------------------
                         slack                                  0.790    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.505ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.261ns  (logic 0.058ns (22.222%)  route 0.203ns (77.778%))
  Logic Levels:           0  
  Clock Path Skew:        -0.684ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.800ns
    Source Clock Delay      (SCD):    2.961ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.281ns (routing 0.379ns, distribution 0.902ns)
  Clock Net Delay (Destination): 1.281ns (routing 0.415ns, distribution 0.866ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.281     2.961    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rsMask_reg[7][9]_0
    SLICE_X83Y48         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y48         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.058     3.019 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[1].u_ddr_mc_rd_en_low/rdEn_reg[2]/Q
                         net (fo=1, routed)           0.203     3.222    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[2]
    BITSLICE_CONTROL_X0Y6
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.281     2.398    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.340 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.148     1.488    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y6
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     1.681 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y6
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     1.800 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.477     2.277    
                         clock uncertainty            0.170     2.447    
    BITSLICE_CONTROL_X0Y6
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[2])
                                                      0.270     2.717    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[3].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -2.717    
                         arrival time                           3.222    
  -------------------------------------------------------------------
                         slack                                  0.505    

Slack (MET) :             0.527ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.278ns  (logic 0.059ns (21.223%)  route 0.219ns (78.777%))
  Logic Levels:           0  
  Clock Path Skew:        -0.689ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.795ns
    Source Clock Delay      (SCD):    2.961ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.281ns (routing 0.379ns, distribution 0.902ns)
  Clock Net Delay (Destination): 1.281ns (routing 0.415ns, distribution 0.866ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.281     2.961    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_low/rsMask_reg[6][9]_0
    SLICE_X81Y17         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_low/rdEn_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y17         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     3.020 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_low/rdEn_reg[2]/Q
                         net (fo=1, routed)           0.219     3.239    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[2]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.281     2.398    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.340 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.143     1.483    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     1.676 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     1.795 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.477     2.272    
                         clock uncertainty            0.170     2.442    
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[2])
                                                      0.270     2.712    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -2.712    
                         arrival time                           3.239    
  -------------------------------------------------------------------
                         slack                                  0.527    

Slack (MET) :             0.560ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.228ns  (logic 0.059ns (25.877%)  route 0.169ns (74.123%))
  Logic Levels:           0  
  Clock Path Skew:        -0.718ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.758ns
    Source Clock Delay      (SCD):    2.953ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.273ns (routing 0.379ns, distribution 0.894ns)
  Clock Net Delay (Destination): 1.281ns (routing 0.415ns, distribution 0.866ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.273     2.953    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rsMask_reg[7][12]_0
    SLICE_X81Y28         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y28         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     3.012 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rdEn_reg[3]/Q
                         net (fo=1, routed)           0.169     3.181    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_upp[3]
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.281     2.398    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.340 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.138     1.478    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.162     1.640 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.118     1.758 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.477     2.235    
                         clock uncertainty            0.170     2.405    
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                      0.216     2.621    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -2.621    
                         arrival time                           3.181    
  -------------------------------------------------------------------
                         slack                                  0.560    

Slack (MET) :             0.562ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.316ns  (logic 0.058ns (18.354%)  route 0.258ns (81.646%))
  Logic Levels:           0  
  Clock Path Skew:        -0.684ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.799ns
    Source Clock Delay      (SCD):    2.960ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.280ns (routing 0.379ns, distribution 0.901ns)
  Clock Net Delay (Destination): 1.281ns (routing 0.415ns, distribution 0.866ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.280     2.960    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rsMask_reg[6][9]_0
    SLICE_X81Y12         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y12         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     3.018 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[3]/Q
                         net (fo=1, routed)           0.258     3.276    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[3]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.281     2.398    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.340 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.147     1.487    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     1.799 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.477     2.276    
                         clock uncertainty            0.170     2.446    
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                      0.268     2.714    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -2.714    
                         arrival time                           3.276    
  -------------------------------------------------------------------
                         slack                                  0.562    

Slack (MET) :             0.564ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.306ns  (logic 0.058ns (18.954%)  route 0.248ns (81.046%))
  Logic Levels:           0  
  Clock Path Skew:        -0.696ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.795ns
    Source Clock Delay      (SCD):    2.968ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.287ns (routing 0.379ns, distribution 0.908ns)
  Clock Net Delay (Destination): 1.281ns (routing 0.415ns, distribution 0.866ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.287     2.968    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_low/rsMask_reg[6][9]_0
    SLICE_X84Y18         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_low/rdEn_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y18         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.058     3.026 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_low/rdEn_reg[3]/Q
                         net (fo=1, routed)           0.248     3.274    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[3]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.281     2.398    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.340 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.143     1.483    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     1.676 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     1.795 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.477     2.272    
                         clock uncertainty            0.170     2.442    
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[3])
                                                      0.268     2.710    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -2.710    
                         arrival time                           3.274    
  -------------------------------------------------------------------
                         slack                                  0.564    

Slack (MET) :             0.601ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.341ns  (logic 0.059ns (17.302%)  route 0.282ns (82.698%))
  Logic Levels:           0  
  Clock Path Skew:        -0.697ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.799ns
    Source Clock Delay      (SCD):    2.973ns
    Clock Pessimism Removal (CPR):    -0.478ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.293ns (routing 0.379ns, distribution 0.914ns)
  Clock Net Delay (Destination): 1.281ns (routing 0.415ns, distribution 0.866ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.293     2.973    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rsMask_reg[6][9]_0
    SLICE_X81Y9          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y9          FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.059     3.032 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[0]/Q
                         net (fo=1, routed)           0.282     3.314    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.281     2.398    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.340 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.147     1.487    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     1.799 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.478     2.276    
                         clock uncertainty            0.170     2.446    
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[0])
                                                      0.267     2.713    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -2.713    
                         arrival time                           3.314    
  -------------------------------------------------------------------
                         slack                                  0.601    

Slack (MET) :             0.603ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rdEn_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.268ns  (logic 0.058ns (21.642%)  route 0.210ns (78.358%))
  Logic Levels:           0  
  Clock Path Skew:        -0.732ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.758ns
    Source Clock Delay      (SCD):    2.967ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.286ns (routing 0.379ns, distribution 0.907ns)
  Clock Net Delay (Destination): 1.281ns (routing 0.415ns, distribution 0.866ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.286     2.967    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rsMask_reg[7][12]_0
    SLICE_X83Y23         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rdEn_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y23         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.058     3.025 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[2].u_ddr_mc_rd_en_upp/rdEn_reg[0]/Q
                         net (fo=1, routed)           0.210     3.235    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_upp[0]
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.281     2.398    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.340 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.138     1.478    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.162     1.640 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.118     1.758 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.477     2.235    
                         clock uncertainty            0.170     2.405    
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[0])
                                                      0.227     2.632    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -2.632    
                         arrival time                           3.235    
  -------------------------------------------------------------------
                         slack                                  0.603    

Slack (MET) :             0.613ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.325ns  (logic 0.058ns (17.846%)  route 0.267ns (82.154%))
  Logic Levels:           0  
  Clock Path Skew:        -0.510ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.977ns
    Source Clock Delay      (SCD):    2.964ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.284ns (routing 0.379ns, distribution 0.905ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.284     2.964    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[13]_2
    SLICE_X82Y19         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y19         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.058     3.022 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[4].u_ddr_mc_wr_bit/dReg_reg[0]/Q
                         net (fo=1, routed)           0.267     3.289    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/ch0_mcal_DQOut[0]
    BITSLICE_RX_TX_X0Y16 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.281     2.398    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.340 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.143     1.483    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.660 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     1.769 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT3[26])
                                                      0.187     1.956 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT3[26]
                         net (fo=1, routed)           0.021     1.977    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT3[26]
    BITSLICE_RX_TX_X0Y16 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.477     2.454    
                         clock uncertainty            0.170     2.624    
    BITSLICE_RX_TX_X0Y16 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.052     2.676    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[3].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.676    
                         arrival time                           3.289    
  -------------------------------------------------------------------
                         slack                                  0.613    

Slack (MET) :             0.624ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.319ns  (logic 0.058ns (18.182%)  route 0.261ns (81.818%))
  Logic Levels:           0  
  Clock Path Skew:        -0.532ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.940ns
    Source Clock Delay      (SCD):    2.949ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.269ns (routing 0.379ns, distribution 0.890ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.269     2.949    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[13]_2
    SLICE_X81Y27         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y27         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     3.007 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/u_ddr_mc_write/genByte[2].u_ddr_mc_wr_byte/genBit[6].u_ddr_mc_wr_bit/dReg_reg[1]/Q
                         net (fo=1, routed)           0.261     3.268    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/ch0_mcal_DQOut[1]
    BITSLICE_RX_TX_X0Y23 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.281     2.398    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.340 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.138     1.478    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     1.629 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     1.738 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.180     1.918 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.022     1.940    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y23 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.477     2.417    
                         clock uncertainty            0.170     2.587    
    BITSLICE_RX_TX_X0Y23 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                      0.057     2.644    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.644    
                         arrival time                           3.268    
  -------------------------------------------------------------------
                         slack                                  0.624    

Slack (MET) :             0.625ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[0]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[0]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[0]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.336ns  (logic 0.058ns (17.262%)  route 0.278ns (82.738%))
  Logic Levels:           0  
  Clock Path Skew:        -0.695ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.799ns
    Source Clock Delay      (SCD):    2.971ns
    Clock Pessimism Removal (CPR):    -0.477ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.291ns (routing 0.379ns, distribution 0.912ns)
  Clock Net Delay (Destination): 1.281ns (routing 0.415ns, distribution 0.866ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.291     2.971    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rsMask_reg[6][9]_0
    SLICE_X81Y9          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y9          FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.058     3.029 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_mc_pi/rdEn[3].u_ddr_mc_rd_en_low/rdEn_reg[1]/Q
                         net (fo=1, routed)           0.278     3.307    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/ch0_mcal_clb2phy_rden_low[1]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/PHY_RDEN[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[0]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.281     2.398    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y0             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.340 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=8, routed)           0.147     1.487    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_RX_DIV2_CLK_Q)
                                                      0.193     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_RX_DIV2_CLK_Q_RX_DIV4_CLK_Q)
                                                      0.119     1.799 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RX_DIV4_CLK_Q
                         clock pessimism              0.477     2.276    
                         clock uncertainty            0.170     2.446    
    BITSLICE_CONTROL_X0Y0
                         BITSLICE_CONTROL (Hold_CONTROL_BITSLICE_CONTROL_RX_DIV4_CLK_Q_PHY_RDEN[1])
                                                      0.236     2.682    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[0].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                         -2.682    
                         arrival time                           3.307    
  -------------------------------------------------------------------
                         slack                                  0.625    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  pll_clk[1]_DIV

Setup :            0  Failing Endpoints,  Worst Slack        0.475ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.588ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.475ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CKE_dly_reg[0][6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.880ns  (logic 0.079ns (4.202%)  route 1.801ns (95.798%))
  Logic Levels:           0  
  Clock Path Skew:        -0.433ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.600ns = ( 5.601 - 3.001 ) 
    Source Clock Delay      (SCD):    2.553ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.436ns (routing 0.415ns, distribution 1.021ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.436     2.553    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y116        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CKE_dly_reg[0][6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y116        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.632 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CKE_dly_reg[0][6]/Q
                         net (fo=6, routed)           1.801     4.433    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_CKE[1]
    BITSLICE_RX_TX_X0Y102
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.123     5.804    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.174 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.105     5.279    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     5.385 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.460 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.126     5.586 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.015     5.601    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y102
                         RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.480     5.121    
                         clock uncertainty           -0.170     4.951    
    BITSLICE_RX_TX_X0Y102
                         RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                     -0.043     4.908    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.908    
                         arrival time                          -4.433    
  -------------------------------------------------------------------
                         slack                                  0.475    

Slack (MET) :             0.684ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.678ns  (logic 0.079ns (4.709%)  route 1.599ns (95.291%))
  Logic Levels:           0  
  Clock Path Skew:        -0.398ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.611ns = ( 5.612 - 3.001 ) 
    Source Clock Delay      (SCD):    2.529ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.412ns (routing 0.415ns, distribution 0.997ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.412     2.529    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X88Y102        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y102        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     2.608 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][7]/Q
                         net (fo=3, routed)           1.599     4.206    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ODT[6]
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.123     5.804    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.174 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.104     5.278    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.395 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.470 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     5.599 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.612    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.480     5.132    
                         clock uncertainty           -0.170     4.962    
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                     -0.071     4.891    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.891    
                         arrival time                          -4.206    
  -------------------------------------------------------------------
                         slack                                  0.684    

Slack (MET) :             0.733ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.680ns  (logic 0.079ns (4.703%)  route 1.601ns (95.297%))
  Logic Levels:           0  
  Clock Path Skew:        -0.398ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.611ns = ( 5.612 - 3.001 ) 
    Source Clock Delay      (SCD):    2.529ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.412ns (routing 0.415ns, distribution 0.997ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.412     2.529    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X88Y102        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y102        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     2.608 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][7]/Q
                         net (fo=3, routed)           1.601     4.208    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ODT[7]
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.123     5.804    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.174 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.104     5.278    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.395 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.470 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     5.599 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.612    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.480     5.132    
                         clock uncertainty           -0.170     4.962    
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.020     4.942    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.942    
                         arrival time                          -4.208    
  -------------------------------------------------------------------
                         slack                                  0.733    

Slack (MET) :             0.793ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][135]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.546ns  (logic 0.080ns (5.175%)  route 1.466ns (94.825%))
  Logic Levels:           0  
  Clock Path Skew:        -0.409ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.611ns = ( 5.612 - 3.001 ) 
    Source Clock Delay      (SCD):    2.540ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.423ns (routing 0.415ns, distribution 1.008ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.423     2.540    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y85         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][135]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y85         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     2.620 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][135]/Q
                         net (fo=1, routed)           1.466     4.086    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[7]
    BITSLICE_RX_TX_X0Y92 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.123     5.804    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.174 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.104     5.278    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.395 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.470 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT1[26])
                                                      0.127     5.597 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26]
                         net (fo=1, routed)           0.015     5.612    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT1[26]
    BITSLICE_RX_TX_X0Y92 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.480     5.132    
                         clock uncertainty           -0.170     4.962    
    BITSLICE_RX_TX_X0Y92 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                     -0.083     4.879    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.879    
                         arrival time                          -4.086    
  -------------------------------------------------------------------
                         slack                                  0.793    

Slack (MET) :             0.810ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.563ns  (logic 0.079ns (5.055%)  route 1.484ns (94.945%))
  Logic Levels:           0  
  Clock Path Skew:        -0.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.611ns = ( 5.612 - 3.001 ) 
    Source Clock Delay      (SCD):    2.554ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.437ns (routing 0.415ns, distribution 1.022ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.437     2.554    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X88Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y79         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.633 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][4]/Q
                         net (fo=4, routed)           1.484     4.116    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ODT[3]
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.123     5.804    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.174 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.104     5.278    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.395 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.470 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     5.599 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.612    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.480     5.132    
                         clock uncertainty           -0.170     4.962    
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                     -0.035     4.927    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.927    
                         arrival time                          -4.116    
  -------------------------------------------------------------------
                         slack                                  0.810    

Slack (MET) :             0.813ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.295ns  (logic 0.079ns (6.100%)  route 1.216ns (93.900%))
  Logic Levels:           0  
  Clock Path Skew:        -0.565ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.459ns = ( 5.460 - 3.001 ) 
    Source Clock Delay      (SCD):    2.544ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.427ns (routing 0.415ns, distribution 1.012ns)
  Clock Net Delay (Destination): 1.123ns (routing 0.379ns, distribution 0.744ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.427     2.544    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/div_clk
    SLICE_X81Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y69         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.623 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2phy_t_b_addr_reg[0]/Q
                         net (fo=7, routed)           1.216     3.839    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/clb2phy_t_b_low[0]
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TBYTE_IN[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.123     5.804    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.174 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.105     5.279    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     5.385 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.460 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
                         clock pessimism             -0.480     4.980    
                         clock uncertainty           -0.170     4.810    
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Setup_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TBYTE_IN[0])
                                                     -0.158     4.652    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control
  -------------------------------------------------------------------
                         required time                          4.652    
                         arrival time                          -3.839    
  -------------------------------------------------------------------
                         slack                                  0.813    

Slack (MET) :             0.813ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.571ns  (logic 0.079ns (5.029%)  route 1.492ns (94.971%))
  Logic Levels:           0  
  Clock Path Skew:        -0.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.611ns = ( 5.612 - 3.001 ) 
    Source Clock Delay      (SCD):    2.554ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.437ns (routing 0.415ns, distribution 1.022ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.437     2.554    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X88Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y79         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.633 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][4]/Q
                         net (fo=4, routed)           1.492     4.124    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ODT[2]
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.123     5.804    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.174 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.104     5.278    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.395 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.470 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     5.599 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.612    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.480     5.132    
                         clock uncertainty           -0.170     4.962    
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                     -0.024     4.938    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.938    
                         arrival time                          -4.124    
  -------------------------------------------------------------------
                         slack                                  0.813    

Slack (MET) :             0.831ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.531ns  (logic 0.079ns (5.162%)  route 1.452ns (94.838%))
  Logic Levels:           0  
  Clock Path Skew:        -0.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.611ns = ( 5.612 - 3.001 ) 
    Source Clock Delay      (SCD):    2.554ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.437ns (routing 0.415ns, distribution 1.022ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.437     2.554    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X88Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y79         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.633 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][4]/Q
                         net (fo=4, routed)           1.452     4.084    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ODT[1]
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.123     5.804    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.174 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.104     5.278    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.395 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.470 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     5.599 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.612    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.480     5.132    
                         clock uncertainty           -0.170     4.962    
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                     -0.046     4.916    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.916    
                         arrival time                          -4.084    
  -------------------------------------------------------------------
                         slack                                  0.831    

Slack (MET) :             0.844ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.476ns  (logic 0.079ns (5.352%)  route 1.397ns (94.648%))
  Logic Levels:           0  
  Clock Path Skew:        -0.435ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.596ns = ( 5.597 - 3.001 ) 
    Source Clock Delay      (SCD):    2.551ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.434ns (routing 0.415ns, distribution 1.019ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.434     2.551    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X88Y82         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y82         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.630 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_CS_n_dly_reg[0][1]/Q
                         net (fo=1, routed)           1.397     4.027    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_CS_n[1]
    BITSLICE_RX_TX_X0Y99 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[1]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 f  
    AR20                                              0.000     3.001 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.123     5.804    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.174 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.105     5.279    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.106     5.385 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.460 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y15
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.124     5.584 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.597    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y99 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.480     5.117    
                         clock uncertainty           -0.170     4.947    
    BITSLICE_RX_TX_X0Y99 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[1])
                                                     -0.076     4.871    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.871    
                         arrival time                          -4.027    
  -------------------------------------------------------------------
                         slack                                  0.844    

Slack (MET) :             0.865ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (pll_clk[1]_DIV rise@3.001ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        1.505ns  (logic 0.079ns (5.250%)  route 1.426ns (94.750%))
  Logic Levels:           0  
  Clock Path Skew:        -0.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.611ns = ( 5.612 - 3.001 ) 
    Source Clock Delay      (SCD):    2.554ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.437ns (routing 0.415ns, distribution 1.022ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.437     2.554    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X88Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X88Y79         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.633 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ODT_dly_reg[0][4]/Q
                         net (fo=4, routed)           1.426     4.058    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ODT[4]
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     3.423 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     3.463    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.463 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     3.812    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     4.442 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     4.657    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     4.681 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.123     5.804    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -0.630     5.174 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.104     5.278    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.117     5.395 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.075     5.470 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.129     5.599 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.013     5.612    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism             -0.480     5.132    
                         clock uncertainty           -0.170     4.962    
    BITSLICE_RX_TX_X0Y93 RXTX_BITSLICE (Setup_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                     -0.038     4.924    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                          4.924    
                         arrival time                          -4.058    
  -------------------------------------------------------------------
                         slack                                  0.865    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.588ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][78]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.313ns  (logic 0.060ns (19.144%)  route 0.253ns (80.856%))
  Logic Levels:           0  
  Clock Path Skew:        -0.497ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.954ns
    Source Clock Delay      (SCD):    2.931ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.251ns (routing 0.379ns, distribution 0.872ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.251     2.931    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y95         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][78]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y95         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.060     2.991 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][78]/Q
                         net (fo=2, routed)           0.253     3.244    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq4[6]
    BITSLICE_RX_TX_X0Y82 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.260     2.377    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.319 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.141     1.460    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.637 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     1.746 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.186     1.932 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.022     1.954    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y82 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.480     2.434    
                         clock uncertainty            0.170     2.604    
    BITSLICE_RX_TX_X0Y82 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.052     2.656    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.656    
                         arrival time                           3.244    
  -------------------------------------------------------------------
                         slack                                  0.588    

Slack (MET) :             0.591ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][95]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.336ns  (logic 0.061ns (18.155%)  route 0.275ns (81.845%))
  Logic Levels:           0  
  Clock Path Skew:        -0.492ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.951ns
    Source Clock Delay      (SCD):    2.922ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.242ns (routing 0.379ns, distribution 0.863ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.242     2.922    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y92         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][95]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y92         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.061     2.983 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][95]/Q
                         net (fo=1, routed)           0.275     3.258    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[7]
    BITSLICE_RX_TX_X0Y80 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[7]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.260     2.377    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.319 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.141     1.460    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.637 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     1.746 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.187     1.933 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.018     1.951    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y80 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.480     2.431    
                         clock uncertainty            0.170     2.601    
    BITSLICE_RX_TX_X0Y80 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[7])
                                                      0.066     2.667    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.667    
                         arrival time                           3.258    
  -------------------------------------------------------------------
                         slack                                  0.591    

Slack (MET) :             0.592ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BG_dly_reg[0][5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.341ns  (logic 0.058ns (17.009%)  route 0.283ns (82.991%))
  Logic Levels:           0  
  Clock Path Skew:        -0.495ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.969ns
    Source Clock Delay      (SCD):    2.944ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.264ns (routing 0.379ns, distribution 0.885ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.264     2.944    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y110        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BG_dly_reg[0][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y110        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.058     3.002 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BG_dly_reg[0][5]/Q
                         net (fo=1, routed)           0.283     3.285    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_BG[5]
    BITSLICE_RX_TX_X0Y96 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[5]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.260     2.377    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.319 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.148     1.467    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.644 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     1.753 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     1.945 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     1.969    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y96 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.480     2.449    
                         clock uncertainty            0.170     2.619    
    BITSLICE_RX_TX_X0Y96 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[5])
                                                      0.074     2.693    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.693    
                         arrival time                           3.285    
  -------------------------------------------------------------------
                         slack                                  0.592    

Slack (MET) :             0.595ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][90]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.336ns  (logic 0.060ns (17.857%)  route 0.276ns (82.143%))
  Logic Levels:           0  
  Clock Path Skew:        -0.492ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.951ns
    Source Clock Delay      (SCD):    2.922ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.242ns (routing 0.379ns, distribution 0.863ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.242     2.922    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y92         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][90]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y92         FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.060     2.982 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][90]/Q
                         net (fo=1, routed)           0.276     3.258    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_ADR[2]
    BITSLICE_RX_TX_X0Y80 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[2]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.260     2.377    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.319 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.141     1.460    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.637 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     1.746 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT2[26])
                                                      0.187     1.933 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT2[26]
                         net (fo=1, routed)           0.018     1.951    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT2[26]
    BITSLICE_RX_TX_X0Y80 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.480     2.431    
                         clock uncertainty            0.170     2.601    
    BITSLICE_RX_TX_X0Y80 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[2])
                                                      0.062     2.663    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[2].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.663    
                         arrival time                           3.258    
  -------------------------------------------------------------------
                         slack                                  0.595    

Slack (MET) :             0.596ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.321ns  (logic 0.058ns (18.070%)  route 0.263ns (81.930%))
  Logic Levels:           0  
  Clock Path Skew:        -0.509ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.958ns
    Source Clock Delay      (SCD):    2.947ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.266ns (routing 0.379ns, distribution 0.887ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.266     2.947    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y103        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y103        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     3.005 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][4]/Q
                         net (fo=2, routed)           0.263     3.268    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[4]
    BITSLICE_RX_TX_X0Y91 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[4]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.260     2.377    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.319 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.148     1.467    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.644 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     1.753 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.162     1.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     1.958    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y91 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.480     2.438    
                         clock uncertainty            0.170     2.608    
    BITSLICE_RX_TX_X0Y91 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[4])
                                                      0.064     2.672    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.672    
                         arrival time                           3.268    
  -------------------------------------------------------------------
                         slack                                  0.596    

Slack (MET) :             0.596ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][72]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.314ns  (logic 0.059ns (18.790%)  route 0.255ns (81.210%))
  Logic Levels:           0  
  Clock Path Skew:        -0.497ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.954ns
    Source Clock Delay      (SCD):    2.931ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.251ns (routing 0.379ns, distribution 0.872ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.251     2.931    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y95         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][72]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y95         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     2.990 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][72]/Q
                         net (fo=1, routed)           0.255     3.245    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq4[0]
    BITSLICE_RX_TX_X0Y82 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[0]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.260     2.377    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.319 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.141     1.460    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.637 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     1.746 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y12
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT4[26])
                                                      0.186     1.932 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT4[26]
                         net (fo=1, routed)           0.022     1.954    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT4[26]
    BITSLICE_RX_TX_X0Y82 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.480     2.434    
                         clock uncertainty            0.170     2.604    
    BITSLICE_RX_TX_X0Y82 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[0])
                                                      0.045     2.649    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[4].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.649    
                         arrival time                           3.245    
  -------------------------------------------------------------------
                         slack                                  0.596    

Slack (MET) :             0.601ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.319ns  (logic 0.058ns (18.183%)  route 0.261ns (81.817%))
  Logic Levels:           0  
  Clock Path Skew:        -0.509ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.958ns
    Source Clock Delay      (SCD):    2.947ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.266ns (routing 0.379ns, distribution 0.887ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.266     2.947    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y103        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y103        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.058     3.005 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][4]/Q
                         net (fo=2, routed)           0.261     3.266    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/clb2phy_wr_dq0[3]
    BITSLICE_RX_TX_X0Y91 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.260     2.377    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.319 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.148     1.467    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.644 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     1.753 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.162     1.915 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     1.958    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y91 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.480     2.438    
                         clock uncertainty            0.170     2.608    
    BITSLICE_RX_TX_X0Y91 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.057     2.665    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.665    
                         arrival time                           3.266    
  -------------------------------------------------------------------
                         slack                                  0.601    

Slack (MET) :             0.603ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][14]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.347ns  (logic 0.059ns (17.003%)  route 0.288ns (82.997%))
  Logic Levels:           0  
  Clock Path Skew:        -0.512ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.942ns
    Source Clock Delay      (SCD):    2.933ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.253ns (routing 0.379ns, distribution 0.874ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.253     2.933    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y82         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y82         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.059     2.992 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BA_dly_reg[0][14]/Q
                         net (fo=1, routed)           0.288     3.280    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/clb2phy_wr_dq6[6]
    BITSLICE_RX_TX_X0Y71 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[6]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.260     2.377    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.319 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.138     1.457    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     1.608 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     1.717 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y11
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT0[26])
                                                      0.182     1.899 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT0[26]
                         net (fo=1, routed)           0.043     1.942    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT0[26]
    BITSLICE_RX_TX_X0Y71 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.480     2.422    
                         clock uncertainty            0.170     2.592    
    BITSLICE_RX_TX_X0Y71 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[6])
                                                      0.085     2.677    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[5].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[0].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.677    
                         arrival time                           3.280    
  -------------------------------------------------------------------
                         slack                                  0.603    

Slack (MET) :             0.605ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][51]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.303ns  (logic 0.059ns (19.472%)  route 0.244ns (80.528%))
  Logic Levels:           0  
  Clock Path Skew:        -0.529ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.927ns
    Source Clock Delay      (SCD):    2.936ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.256ns (routing 0.379ns, distribution 0.877ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.256     2.936    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y99         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][51]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y99         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     2.995 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_ADR_dly_reg[0][51]/Q
                         net (fo=1, routed)           0.244     3.239    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/mcal_ADR[3]
    BITSLICE_RX_TX_X0Y85 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 f  
    AR20                                              0.000     0.000 f  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.260     2.377    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.319 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.146     1.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y13
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.151     1.616 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y13
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     1.725 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y13
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT1[26])
                                                      0.179     1.904 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT1[26]
                         net (fo=1, routed)           0.023     1.927    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/TX_BIT_CTRL_OUT1[26]
    BITSLICE_RX_TX_X0Y85 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.480     2.407    
                         clock uncertainty            0.170     2.577    
    BITSLICE_RX_TX_X0Y85 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.057     2.634    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[6].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_UPPER[1].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_upper/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.634    
                         arrival time                           3.239    
  -------------------------------------------------------------------
                         slack                                  0.605    

Slack (MET) :             0.610ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BG_dly_reg[0][3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
                            (rising edge-triggered cell RXTX_BITSLICE clocked by pll_clk[1]_DIV  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             pll_clk[1]_DIV
  Path Type:              Hold (Min at Slow Process Corner)
  Requirement:            0.000ns  (pll_clk[1]_DIV rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.358ns  (logic 0.059ns (16.480%)  route 0.299ns (83.520%))
  Logic Levels:           0  
  Clock Path Skew:        -0.495ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.969ns
    Source Clock Delay      (SCD):    2.944ns
    Clock Pessimism Removal (CPR):    -0.480ns
  Clock Uncertainty:      0.170ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.062ns
    Phase Error              (PE):    0.123ns
  Clock Net Delay (Source):      1.264ns (routing 0.379ns, distribution 0.885ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.264     2.944    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X81Y110        FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BG_dly_reg[0][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y110        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.059     3.003 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/mcal_BG_dly_reg[0][3]/Q
                         net (fo=1, routed)           0.299     3.302    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/mcal_BG[3]
    BITSLICE_RX_TX_X0Y96 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/D[3]
  -------------------------------------------------------------------    -------------------

                         (clock pll_clk[1]_DIV rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
                         net (fo=27067, routed)       1.260     2.377    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/div_clk
    PLL_X0Y2             PLLE4_ADV (Prop_PLL_CLKIN_CLKOUTPHY)
                                                     -1.058     1.319 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[1].gen_plle4.PLLE4_BASE_INST_OTHER/CLKOUTPHY
                         net (fo=7, routed)           0.148     1.467    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/pll_clk[0]
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_PLL_CLK_TX_DIV2_CLK_Q)
                                                      0.177     1.644 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV2_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV2_CLK_Q_TX_DIV4_CLK_Q)
                                                      0.109     1.753 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_DIV4_CLK_Q
    BITSLICE_CONTROL_X0Y14
                         BITSLICE_CONTROL (Prop_CONTROL_BITSLICE_CONTROL_TX_DIV4_CLK_Q_TX_BIT_CTRL_OUT5[26])
                                                      0.192     1.945 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/TX_BIT_CTRL_OUT5[26]
                         net (fo=1, routed)           0.024     1.969    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/TX_BIT_CTRL_OUT5[26]
    BITSLICE_RX_TX_X0Y96 RXTX_BITSLICE                                r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice/TX_BIT_CTRL_IN[26]
                         clock pessimism              0.480     2.449    
                         clock uncertainty            0.170     2.619    
    BITSLICE_RX_TX_X0Y96 RXTX_BITSLICE (Hold_RXTX_BITSLICE_BITSLICE_RX_TX_TX_BIT_CTRL_IN[26]_D[3])
                                                      0.073     2.692    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[7].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_BITSLICE_LOWER[5].GEN_RXTX_BITSLICE_EN.u_xiphy_bitslice_lower/xiphy_rxtx_bitslice
  -------------------------------------------------------------------
                         required time                         -2.692    
                         arrival time                           3.302    
  -------------------------------------------------------------------
                         slack                                  0.610    





---------------------------------------------------------------------------------------------------
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       49.565ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             49.565ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.460ns  (logic 0.076ns (16.522%)  route 0.384ns (83.478%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y63                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
    SLICE_X107Y63        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.384     0.460    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
    SLICE_X107Y64        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X107Y64        FDCE (Setup_HFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.460    
  -------------------------------------------------------------------
                         slack                                 49.565    

Slack (MET) :             49.612ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.413ns  (logic 0.079ns (19.128%)  route 0.334ns (80.872%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y62                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/C
    SLICE_X102Y62        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.334     0.413    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[2]
    SLICE_X102Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X102Y62        FDCE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.413    
  -------------------------------------------------------------------
                         slack                                 49.612    

Slack (MET) :             49.632ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.393ns  (logic 0.079ns (20.102%)  route 0.314ns (79.898%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y63                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
    SLICE_X107Y63        FDCE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.314     0.393    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X107Y63        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X107Y63        FDCE (Setup_DFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.393    
  -------------------------------------------------------------------
                         slack                                 49.632    

Slack (MET) :             49.637ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.388ns  (logic 0.076ns (19.588%)  route 0.312ns (80.412%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y63                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/C
    SLICE_X107Y63        FDCE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     0.076 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.312     0.388    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[3]
    SLICE_X107Y63        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X107Y63        FDCE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.388    
  -------------------------------------------------------------------
                         slack                                 49.637    

Slack (MET) :             49.680ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.345ns  (logic 0.081ns (23.478%)  route 0.264ns (76.522%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y63                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/C
    SLICE_X106Y63        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.264     0.345    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[1]
    SLICE_X107Y64        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X107Y64        FDCE (Setup_BFF2_SLICEM_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.345    
  -------------------------------------------------------------------
                         slack                                 49.680    

Slack (MET) :             49.741ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.284ns  (logic 0.079ns (27.817%)  route 0.205ns (72.183%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y62                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
    SLICE_X102Y62        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.205     0.284    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X102Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X102Y62        FDCE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.284    
  -------------------------------------------------------------------
                         slack                                 49.741    

Slack (MET) :             49.793ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.232ns  (logic 0.079ns (34.052%)  route 0.153ns (65.948%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y60                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
    SLICE_X102Y60        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     0.079 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.153     0.232    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
    SLICE_X102Y59        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X102Y59        FDCE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.232    
  -------------------------------------------------------------------
                         slack                                 49.793    

Slack (MET) :             49.796ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            50.000ns  (MaxDelay Path 50.000ns)
  Data Path Delay:        0.229ns  (logic 0.081ns (35.371%)  route 0.148ns (64.629%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 50.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y60                                     0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
    SLICE_X102Y60        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.148     0.229    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X102Y59        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   50.000    50.000    
    SLICE_X102Y59        FDCE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    50.025    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         50.025    
                         arrival time                          -0.229    
  -------------------------------------------------------------------
                         slack                                 49.796    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       10.503ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             10.503ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        1.522ns  (logic 0.079ns (5.191%)  route 1.443ns (94.809%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y67                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
    SLICE_X92Y67         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/Q
                         net (fo=1, routed)           1.443     1.522    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[6]
    SLICE_X95Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y70         FDRE (Setup_GFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -1.522    
  -------------------------------------------------------------------
                         slack                                 10.503    

Slack (MET) :             11.044ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.981ns  (logic 0.079ns (8.053%)  route 0.902ns (91.947%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y93                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
    SLICE_X96Y93         FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/Q
                         net (fo=2, routed)           0.902     0.981    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/D[0]
    SLICE_X96Y72         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X96Y72         FDRE (Setup_FFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.981    
  -------------------------------------------------------------------
                         slack                                 11.044    

Slack (MET) :             11.303ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.722ns  (logic 0.079ns (10.942%)  route 0.643ns (89.058%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y67                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
    SLICE_X92Y67         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/Q
                         net (fo=1, routed)           0.643     0.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[0]
    SLICE_X92Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X92Y67         FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.722    
  -------------------------------------------------------------------
                         slack                                 11.303    

Slack (MET) :             11.579ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.446ns  (logic 0.081ns (18.161%)  route 0.365ns (81.839%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y67                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
    SLICE_X92Y67         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/Q
                         net (fo=1, routed)           0.365     0.446    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[3]
    SLICE_X92Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X92Y67         FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.446    
  -------------------------------------------------------------------
                         slack                                 11.579    

Slack (MET) :             11.598ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.427ns  (logic 0.080ns (18.735%)  route 0.347ns (81.265%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y69                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
    SLICE_X92Y69         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/Q
                         net (fo=1, routed)           0.347     0.427    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[5]
    SLICE_X94Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X94Y69         FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.427    
  -------------------------------------------------------------------
                         slack                                 11.598    

Slack (MET) :             11.618ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.407ns  (logic 0.079ns (19.410%)  route 0.328ns (80.590%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y67                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
    SLICE_X92Y67         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/Q
                         net (fo=1, routed)           0.328     0.407    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[2]
    SLICE_X95Y65         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y65         FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.407    
  -------------------------------------------------------------------
                         slack                                 11.618    

Slack (MET) :             11.627ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.398ns  (logic 0.080ns (20.101%)  route 0.318ns (79.899%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y69                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
    SLICE_X92Y69         FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/Q
                         net (fo=1, routed)           0.318     0.398    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[7]
    SLICE_X95Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y70         FDRE (Setup_DFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.398    
  -------------------------------------------------------------------
                         slack                                 11.627    

Slack (MET) :             11.636ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.389ns  (logic 0.081ns (20.823%)  route 0.308ns (79.177%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y67                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
    SLICE_X92Y67         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/Q
                         net (fo=1, routed)           0.308     0.389    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[1]
    SLICE_X95Y68         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y68         FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.389    
  -------------------------------------------------------------------
                         slack                                 11.636    

Slack (MET) :             11.651ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.374ns  (logic 0.081ns (21.658%)  route 0.293ns (78.342%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y67                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
    SLICE_X92Y67         FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/Q
                         net (fo=1, routed)           0.293     0.374    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[8]
    SLICE_X95Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X95Y67         FDRE (Setup_CFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.374    
  -------------------------------------------------------------------
                         slack                                 11.651    

Slack (MET) :             11.657ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             mmcm_clkout5
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.000ns  (MaxDelay Path 12.000ns)
  Data Path Delay:        0.368ns  (logic 0.081ns (22.011%)  route 0.287ns (77.989%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 12.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y69                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
    SLICE_X92Y69         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     0.081 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/Q
                         net (fo=1, routed)           0.287     0.368    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[4]
    SLICE_X92Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                   12.000    12.000    
    SLICE_X92Y69         FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025    12.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         12.025    
                         arrival time                          -0.368    
  -------------------------------------------------------------------
                         slack                                 11.657    





---------------------------------------------------------------------------------------------------
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout6

Setup :            0  Failing Endpoints,  Worst Slack        1.259ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.316ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.259ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            3.001ns  (mmcm_clkout6 rise@6.001ns - mmcm_clkout0 rise@3.001ns)
  Data Path Delay:        1.367ns  (logic 0.078ns (5.706%)  route 1.289ns (94.294%))
  Logic Levels:           0  
  Clock Path Skew:        -0.211ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.933ns = ( 8.935 - 6.001 ) 
    Source Clock Delay      (SCD):    2.547ns = ( 5.547 - 3.001 ) 
    Clock Pessimism Removal (CPR):    -0.598ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      1.430ns (routing 0.415ns, distribution 1.015ns)
  Clock Net Delay (Destination): 1.240ns (routing 0.379ns, distribution 0.861ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      3.001     3.001 r  
    AR20                                              0.000     3.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     3.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     3.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     3.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     3.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     3.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     3.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     4.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.430     5.547    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X94Y30         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y30         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     5.625 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/Q
                         net (fo=1, routed)           1.289     6.914    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts
    SLICE_X89Y30         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      6.001     6.001 r  
    AR20                                              0.000     6.001 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     6.001    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     6.424 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     6.464    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     6.464 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     6.813    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     7.443 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     7.671    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.695 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.240     8.935    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X89Y30         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/C
                         clock pessimism             -0.598     8.337    
                         clock uncertainty           -0.188     8.148    
    SLICE_X89Y30         FDRE (Setup_BFF_SLICEM_C_D)
                                                      0.025     8.173    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg
  -------------------------------------------------------------------
                         required time                          8.173    
                         arrival time                          -6.914    
  -------------------------------------------------------------------
                         slack                                  1.259    

Slack (MET) :             4.199ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[12].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.826ns  (logic 0.079ns (9.564%)  route 0.747ns (90.436%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y33                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[12]/C
    SLICE_X93Y33         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[12]/Q
                         net (fo=1, routed)           0.747     0.826    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[12]
    SLICE_X93Y36         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[12].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X93Y36         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[12].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.826    
  -------------------------------------------------------------------
                         slack                                  4.199    

Slack (MET) :             4.278ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[9].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.747ns  (logic 0.078ns (10.442%)  route 0.669ns (89.558%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y36                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[9]/C
    SLICE_X90Y36         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[9]/Q
                         net (fo=1, routed)           0.669     0.747    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[9]
    SLICE_X90Y36         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[9].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X90Y36         FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[9].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.747    
  -------------------------------------------------------------------
                         slack                                  4.278    

Slack (MET) :             4.290ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[13].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.735ns  (logic 0.078ns (10.612%)  route 0.657ns (89.388%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y33                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[13]/C
    SLICE_X93Y33         FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[13]/Q
                         net (fo=1, routed)           0.657     0.735    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[13]
    SLICE_X89Y33         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[13].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X89Y33         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[13].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.735    
  -------------------------------------------------------------------
                         slack                                  4.290    

Slack (MET) :             4.300ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[21]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[21].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.725ns  (logic 0.079ns (10.897%)  route 0.646ns (89.103%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y36                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[21]/C
    SLICE_X95Y36         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[21]/Q
                         net (fo=1, routed)           0.646     0.725    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[21]
    SLICE_X93Y36         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[21].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X93Y36         FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[21].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.725    
  -------------------------------------------------------------------
                         slack                                  4.300    

Slack (MET) :             4.370ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[24]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[24].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.655ns  (logic 0.078ns (11.908%)  route 0.577ns (88.092%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y38                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[24]/C
    SLICE_X96Y38         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[24]/Q
                         net (fo=1, routed)           0.577     0.655    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[24]
    SLICE_X89Y30         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[24].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X89Y30         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[24].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.655    
  -------------------------------------------------------------------
                         slack                                  4.370    

Slack (MET) :             4.407ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[25].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.618ns  (logic 0.079ns (12.783%)  route 0.539ns (87.217%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y37                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[25]/C
    SLICE_X92Y37         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     0.079 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[25]/Q
                         net (fo=1, routed)           0.539     0.618    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[25]
    SLICE_X90Y37         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[25].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X90Y37         FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[25].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.618    
  -------------------------------------------------------------------
                         slack                                  4.407    

Slack (MET) :             4.447ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[17]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[17].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.578ns  (logic 0.078ns (13.495%)  route 0.500ns (86.505%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y34                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[17]/C
    SLICE_X93Y34         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[17]/Q
                         net (fo=1, routed)           0.500     0.578    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[17]
    SLICE_X91Y34         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[17].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X91Y34         FDRE (Setup_HFF2_SLICEL_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[17].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.578    
  -------------------------------------------------------------------
                         slack                                  4.447    

Slack (MET) :             4.463ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.562ns  (logic 0.078ns (13.879%)  route 0.484ns (86.121%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y39                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[5]/C
    SLICE_X89Y39         FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     0.078 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[5]/Q
                         net (fo=1, routed)           0.484     0.562    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[5]
    SLICE_X90Y39         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X90Y39         FDRE (Setup_DFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[5].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.562    
  -------------------------------------------------------------------
                         slack                                  4.463    

Slack (MET) :             4.497ns  (required time - arrival time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            5.000ns  (MaxDelay Path 5.000ns)
  Data Path Delay:        0.528ns  (logic 0.080ns (15.152%)  route 0.448ns (84.848%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 5.000ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y38                                      0.000     0.000 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[6]/C
    SLICE_X91Y38         FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.080     0.080 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[6]/Q
                         net (fo=1, routed)           0.448     0.528    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[6]
    SLICE_X89Y33         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    5.000     5.000    
    SLICE_X89Y33         FDRE (Setup_CFF2_SLICEM_C_D)
                                                      0.025     5.025    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[6].sync_reg_reg[0]
  -------------------------------------------------------------------
                         required time                          5.025    
                         arrival time                          -0.528    
  -------------------------------------------------------------------
                         slack                                  4.497    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.316ns  (arrival time - required time)
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             mmcm_clkout6
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout6 rise@0.000ns - mmcm_clkout0 rise@0.000ns)
  Data Path Delay:        0.685ns  (logic 0.039ns (5.693%)  route 0.646ns (94.307%))
  Logic Levels:           0  
  Clock Path Skew:        0.134ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.466ns
    Source Clock Delay      (SCD):    1.717ns
    Clock Pessimism Removal (CPR):    -0.386ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.791ns (routing 0.230ns, distribution 0.561ns)
  Clock Net Delay (Destination): 0.892ns (routing 0.255ns, distribution 0.637ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.791     1.717    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X94Y30         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y30         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.756 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/sample_gts_reg/Q
                         net (fo=1, routed)           0.646     2.402    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts
    SLICE_X89Y30         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.892     1.466    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X89Y30         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg/C
                         clock pessimism              0.386     1.851    
                         clock uncertainty            0.188     2.040    
    SLICE_X89Y30         FDRE (Hold_BFF_SLICEM_C_D)
                                                      0.046     2.086    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/sample_gts_riu_reg
  -------------------------------------------------------------------
                         required time                         -2.086    
                         arrival time                           2.402    
  -------------------------------------------------------------------
                         slack                                  0.316    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_out1_d_1_clk_core_0

Setup :            0  Failing Endpoints,  Worst Slack        1.755ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        1.423ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.755ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.938ns  (logic 0.104ns (3.540%)  route 2.834ns (96.460%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.179ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.495ns = ( 9.495 - 5.000 ) 
    Source Clock Delay      (SCD):    4.329ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.864ns (routing 0.947ns, distribution 0.917ns)
  Clock Net Delay (Destination): 1.560ns (routing 0.863ns, distribution 0.697ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.864     4.329    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.405 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.394     5.799    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.827 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        1.440     7.267    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X42Y208        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.560     9.495    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X42Y208        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]/C
                         clock pessimism             -0.345     9.150    
                         clock uncertainty           -0.062     9.088    
    SLICE_X42Y208        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066     9.022    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[6]
  -------------------------------------------------------------------
                         required time                          9.022    
                         arrival time                          -7.267    
  -------------------------------------------------------------------
                         slack                                  1.755    

Slack (MET) :             1.755ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.938ns  (logic 0.104ns (3.540%)  route 2.834ns (96.460%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.179ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.495ns = ( 9.495 - 5.000 ) 
    Source Clock Delay      (SCD):    4.329ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.864ns (routing 0.947ns, distribution 0.917ns)
  Clock Net Delay (Destination): 1.560ns (routing 0.863ns, distribution 0.697ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.864     4.329    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.405 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.394     5.799    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.827 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        1.440     7.267    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X42Y208        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.560     9.495    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X42Y208        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]/C
                         clock pessimism             -0.345     9.150    
                         clock uncertainty           -0.062     9.088    
    SLICE_X42Y208        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066     9.022    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[6]
  -------------------------------------------------------------------
                         required time                          9.022    
                         arrival time                          -7.267    
  -------------------------------------------------------------------
                         slack                                  1.755    

Slack (MET) :             1.755ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.938ns  (logic 0.104ns (3.540%)  route 2.834ns (96.460%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.179ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.495ns = ( 9.495 - 5.000 ) 
    Source Clock Delay      (SCD):    4.329ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.864ns (routing 0.947ns, distribution 0.917ns)
  Clock Net Delay (Destination): 1.560ns (routing 0.863ns, distribution 0.697ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.864     4.329    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.405 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.394     5.799    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.827 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        1.440     7.267    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X42Y208        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.560     9.495    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X42Y208        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]/C
                         clock pessimism             -0.345     9.150    
                         clock uncertainty           -0.062     9.088    
    SLICE_X42Y208        FDCE (Recov_BFF_SLICEM_C_CLR)
                                                     -0.066     9.022    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[7]
  -------------------------------------------------------------------
                         required time                          9.022    
                         arrival time                          -7.267    
  -------------------------------------------------------------------
                         slack                                  1.755    

Slack (MET) :             1.755ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.938ns  (logic 0.104ns (3.540%)  route 2.834ns (96.460%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.179ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.495ns = ( 9.495 - 5.000 ) 
    Source Clock Delay      (SCD):    4.329ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.864ns (routing 0.947ns, distribution 0.917ns)
  Clock Net Delay (Destination): 1.560ns (routing 0.863ns, distribution 0.697ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.864     4.329    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.405 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.394     5.799    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.827 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        1.440     7.267    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X42Y208        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.560     9.495    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X42Y208        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]/C
                         clock pessimism             -0.345     9.150    
                         clock uncertainty           -0.062     9.088    
    SLICE_X42Y208        FDCE (Recov_AFF_SLICEM_C_CLR)
                                                     -0.066     9.022    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[8]
  -------------------------------------------------------------------
                         required time                          9.022    
                         arrival time                          -7.267    
  -------------------------------------------------------------------
                         slack                                  1.755    

Slack (MET) :             1.757ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.935ns  (logic 0.104ns (3.543%)  route 2.831ns (96.457%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.180ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.494ns = ( 9.494 - 5.000 ) 
    Source Clock Delay      (SCD):    4.329ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.864ns (routing 0.947ns, distribution 0.917ns)
  Clock Net Delay (Destination): 1.559ns (routing 0.863ns, distribution 0.696ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.864     4.329    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.405 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.394     5.799    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.827 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        1.437     7.264    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X42Y208        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.559     9.494    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X42Y208        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
                         clock pessimism             -0.345     9.149    
                         clock uncertainty           -0.062     9.087    
    SLICE_X42Y208        FDCE (Recov_HFF_SLICEM_C_CLR)
                                                     -0.066     9.021    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]
  -------------------------------------------------------------------
                         required time                          9.021    
                         arrival time                          -7.264    
  -------------------------------------------------------------------
                         slack                                  1.757    

Slack (MET) :             1.757ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.935ns  (logic 0.104ns (3.543%)  route 2.831ns (96.457%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.180ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.494ns = ( 9.494 - 5.000 ) 
    Source Clock Delay      (SCD):    4.329ns
    Clock Pessimism Removal (CPR):    -0.345ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.864ns (routing 0.947ns, distribution 0.917ns)
  Clock Net Delay (Destination): 1.559ns (routing 0.863ns, distribution 0.696ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.864     4.329    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.405 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.394     5.799    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.827 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        1.437     7.264    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X42Y208        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.559     9.494    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X42Y208        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
                         clock pessimism             -0.345     9.149    
                         clock uncertainty           -0.062     9.087    
    SLICE_X42Y208        FDCE (Recov_GFF_SLICEM_C_CLR)
                                                     -0.066     9.021    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]
  -------------------------------------------------------------------
                         required time                          9.021    
                         arrival time                          -7.264    
  -------------------------------------------------------------------
                         slack                                  1.757    

Slack (MET) :             1.760ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.991ns  (logic 0.104ns (3.477%)  route 2.887ns (96.523%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.121ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.551ns = ( 9.551 - 5.000 ) 
    Source Clock Delay      (SCD):    4.329ns
    Clock Pessimism Removal (CPR):    -0.343ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.864ns (routing 0.947ns, distribution 0.917ns)
  Clock Net Delay (Destination): 1.616ns (routing 0.863ns, distribution 0.753ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.864     4.329    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.405 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.394     5.799    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.827 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        1.493     7.320    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X35Y212        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.616     9.551    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                         clock pessimism             -0.343     9.208    
                         clock uncertainty           -0.062     9.146    
    SLICE_X35Y212        FDCE (Recov_DFF2_SLICEM_C_CLR)
                                                     -0.066     9.080    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]
  -------------------------------------------------------------------
                         required time                          9.080    
                         arrival time                          -7.320    
  -------------------------------------------------------------------
                         slack                                  1.760    

Slack (MET) :             1.762ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.988ns  (logic 0.104ns (3.481%)  route 2.884ns (96.519%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.122ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.550ns = ( 9.550 - 5.000 ) 
    Source Clock Delay      (SCD):    4.329ns
    Clock Pessimism Removal (CPR):    -0.343ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.864ns (routing 0.947ns, distribution 0.917ns)
  Clock Net Delay (Destination): 1.615ns (routing 0.863ns, distribution 0.752ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.864     4.329    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.405 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.394     5.799    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.827 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        1.490     7.317    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X35Y212        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.615     9.550    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
                         clock pessimism             -0.343     9.207    
                         clock uncertainty           -0.062     9.145    
    SLICE_X35Y212        FDCE (Recov_HFF_SLICEM_C_CLR)
                                                     -0.066     9.079    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]
  -------------------------------------------------------------------
                         required time                          9.079    
                         arrival time                          -7.317    
  -------------------------------------------------------------------
                         slack                                  1.762    

Slack (MET) :             1.762ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/PRE
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.988ns  (logic 0.104ns (3.481%)  route 2.884ns (96.519%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.122ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.550ns = ( 9.550 - 5.000 ) 
    Source Clock Delay      (SCD):    4.329ns
    Clock Pessimism Removal (CPR):    -0.343ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.864ns (routing 0.947ns, distribution 0.917ns)
  Clock Net Delay (Destination): 1.615ns (routing 0.863ns, distribution 0.752ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.864     4.329    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.405 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.394     5.799    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.827 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        1.490     7.317    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X35Y212        FDPE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.615     9.550    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDPE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/C
                         clock pessimism             -0.343     9.207    
                         clock uncertainty           -0.062     9.145    
    SLICE_X35Y212        FDPE (Recov_HFF2_SLICEM_C_PRE)
                                                     -0.066     9.079    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]
  -------------------------------------------------------------------
                         required time                          9.079    
                         arrival time                          -7.317    
  -------------------------------------------------------------------
                         slack                                  1.762    

Slack (MET) :             1.762ns  (required time - arrival time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/CLR
                            (recovery check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            5.000ns  (clk_out1_d_1_clk_core_0 rise@5.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        2.988ns  (logic 0.104ns (3.481%)  route 2.884ns (96.519%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.122ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.550ns = ( 9.550 - 5.000 ) 
    Source Clock Delay      (SCD):    4.329ns
    Clock Pessimism Removal (CPR):    -0.343ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.102ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.864ns (routing 0.947ns, distribution 0.917ns)
  Clock Net Delay (Destination): 1.615ns (routing 0.863ns, distribution 0.752ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.864     4.329    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     4.405 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.394     5.799    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.827 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        1.490     7.317    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X35Y212        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      5.000     5.000 r  
    PS8_X0Y0             PS8                          0.000     5.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     5.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     5.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     7.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     7.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     7.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     7.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.615     9.550    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                         clock pessimism             -0.343     9.207    
                         clock uncertainty           -0.062     9.145    
    SLICE_X35Y212        FDCE (Recov_GFF2_SLICEM_C_CLR)
                                                     -0.066     9.079    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]
  -------------------------------------------------------------------
                         required time                          9.079    
                         arrival time                          -7.317    
  -------------------------------------------------------------------
                         slack                                  1.762    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.423ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.464ns  (logic 0.055ns (3.758%)  route 1.409ns (96.242%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.061ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.463ns
    Source Clock Delay      (SCD):    2.689ns
    Clock Pessimism Removal (CPR):    -0.287ns
  Clock Net Delay (Source):      1.029ns (routing 0.518ns, distribution 0.511ns)
  Clock Net Delay (Destination): 1.146ns (routing 0.574ns, distribution 0.572ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.029     2.689    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.727 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.720     3.447    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.464 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        0.689     4.153    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X58Y262        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.146     2.463    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y262        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                         clock pessimism              0.287     2.750    
    SLICE_X58Y262        FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                     -0.020     2.730    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.730    
                         arrival time                           4.153    
  -------------------------------------------------------------------
                         slack                                  1.423    

Slack (MET) :             1.423ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/PRE
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.464ns  (logic 0.055ns (3.758%)  route 1.409ns (96.242%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.061ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.463ns
    Source Clock Delay      (SCD):    2.689ns
    Clock Pessimism Removal (CPR):    -0.287ns
  Clock Net Delay (Source):      1.029ns (routing 0.518ns, distribution 0.511ns)
  Clock Net Delay (Destination): 1.146ns (routing 0.574ns, distribution 0.572ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.029     2.689    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.727 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.720     3.447    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.464 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        0.689     4.153    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X58Y262        FDPE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.146     2.463    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y262        FDPE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]/C
                         clock pessimism              0.287     2.750    
    SLICE_X58Y262        FDPE (Remov_GFF2_SLICEL_C_PRE)
                                                     -0.020     2.730    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.730    
                         arrival time                           4.153    
  -------------------------------------------------------------------
                         slack                                  1.423    

Slack (MET) :             1.423ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.464ns  (logic 0.055ns (3.758%)  route 1.409ns (96.242%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.061ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.463ns
    Source Clock Delay      (SCD):    2.689ns
    Clock Pessimism Removal (CPR):    -0.287ns
  Clock Net Delay (Source):      1.029ns (routing 0.518ns, distribution 0.511ns)
  Clock Net Delay (Destination): 1.146ns (routing 0.574ns, distribution 0.572ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.029     2.689    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.727 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.720     3.447    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.464 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        0.689     4.153    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X58Y262        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.146     2.463    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y262        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                         clock pessimism              0.287     2.750    
    SLICE_X58Y262        FDCE (Remov_FFF2_SLICEL_C_CLR)
                                                     -0.020     2.730    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.730    
                         arrival time                           4.153    
  -------------------------------------------------------------------
                         slack                                  1.423    

Slack (MET) :             1.423ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[2]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.464ns  (logic 0.055ns (3.758%)  route 1.409ns (96.242%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.061ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.463ns
    Source Clock Delay      (SCD):    2.689ns
    Clock Pessimism Removal (CPR):    -0.287ns
  Clock Net Delay (Source):      1.029ns (routing 0.518ns, distribution 0.511ns)
  Clock Net Delay (Destination): 1.146ns (routing 0.574ns, distribution 0.572ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.029     2.689    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.727 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.720     3.447    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.464 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        0.689     4.153    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X58Y262        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.146     2.463    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y262        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[2]/C
                         clock pessimism              0.287     2.750    
    SLICE_X58Y262        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     2.730    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.730    
                         arrival time                           4.153    
  -------------------------------------------------------------------
                         slack                                  1.423    

Slack (MET) :             1.427ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.464ns  (logic 0.055ns (3.758%)  route 1.409ns (96.242%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.459ns
    Source Clock Delay      (SCD):    2.689ns
    Clock Pessimism Removal (CPR):    -0.287ns
  Clock Net Delay (Source):      1.029ns (routing 0.518ns, distribution 0.511ns)
  Clock Net Delay (Destination): 1.142ns (routing 0.574ns, distribution 0.568ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.029     2.689    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.727 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.720     3.447    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.464 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        0.689     4.153    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X58Y262        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.142     2.459    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y262        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
                         clock pessimism              0.287     2.746    
    SLICE_X58Y262        FDCE (Remov_DFF_SLICEL_C_CLR)
                                                     -0.020     2.726    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.726    
                         arrival time                           4.153    
  -------------------------------------------------------------------
                         slack                                  1.427    

Slack (MET) :             1.427ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.464ns  (logic 0.055ns (3.758%)  route 1.409ns (96.242%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.459ns
    Source Clock Delay      (SCD):    2.689ns
    Clock Pessimism Removal (CPR):    -0.287ns
  Clock Net Delay (Source):      1.029ns (routing 0.518ns, distribution 0.511ns)
  Clock Net Delay (Destination): 1.142ns (routing 0.574ns, distribution 0.568ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.029     2.689    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.727 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.720     3.447    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.464 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        0.689     4.153    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X58Y262        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.142     2.459    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y262        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
                         clock pessimism              0.287     2.746    
    SLICE_X58Y262        FDCE (Remov_CFF_SLICEL_C_CLR)
                                                     -0.020     2.726    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]
  -------------------------------------------------------------------
                         required time                         -2.726    
                         arrival time                           4.153    
  -------------------------------------------------------------------
                         slack                                  1.427    

Slack (MET) :             1.427ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.464ns  (logic 0.055ns (3.758%)  route 1.409ns (96.242%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.057ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.459ns
    Source Clock Delay      (SCD):    2.689ns
    Clock Pessimism Removal (CPR):    -0.287ns
  Clock Net Delay (Source):      1.029ns (routing 0.518ns, distribution 0.511ns)
  Clock Net Delay (Destination): 1.142ns (routing 0.574ns, distribution 0.568ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.029     2.689    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.727 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.720     3.447    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.464 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        0.689     4.153    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X58Y262        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.142     2.459    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X58Y262        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]/C
                         clock pessimism              0.287     2.746    
    SLICE_X58Y262        FDCE (Remov_BFF_SLICEL_C_CLR)
                                                     -0.020     2.726    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[4]
  -------------------------------------------------------------------
                         required time                         -2.726    
                         arrival time                           4.153    
  -------------------------------------------------------------------
                         slack                                  1.427    

Slack (MET) :             1.431ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.467ns  (logic 0.055ns (3.749%)  route 1.412ns (96.251%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.458ns
    Source Clock Delay      (SCD):    2.689ns
    Clock Pessimism Removal (CPR):    -0.287ns
  Clock Net Delay (Source):      1.029ns (routing 0.518ns, distribution 0.511ns)
  Clock Net Delay (Destination): 1.141ns (routing 0.574ns, distribution 0.567ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.029     2.689    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.727 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.720     3.447    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.464 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        0.692     4.156    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X59Y261        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.141     2.458    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X59Y261        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]/C
                         clock pessimism              0.287     2.745    
    SLICE_X59Y261        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     2.725    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.725    
                         arrival time                           4.156    
  -------------------------------------------------------------------
                         slack                                  1.431    

Slack (MET) :             1.431ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.467ns  (logic 0.055ns (3.749%)  route 1.412ns (96.251%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.458ns
    Source Clock Delay      (SCD):    2.689ns
    Clock Pessimism Removal (CPR):    -0.287ns
  Clock Net Delay (Source):      1.029ns (routing 0.518ns, distribution 0.511ns)
  Clock Net Delay (Destination): 1.141ns (routing 0.574ns, distribution 0.567ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.029     2.689    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.727 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.720     3.447    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.464 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        0.692     4.156    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X59Y261        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.141     2.458    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X59Y261        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]/C
                         clock pessimism              0.287     2.745    
    SLICE_X59Y261        FDCE (Remov_GFF_SLICEL_C_CLR)
                                                     -0.020     2.725    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[5]
  -------------------------------------------------------------------
                         required time                         -2.725    
                         arrival time                           4.156    
  -------------------------------------------------------------------
                         slack                                  1.431    

Slack (MET) :             1.431ns  (arrival time - required time)
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]/CLR
                            (removal check against rising-edge clock clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_out1_d_1_clk_core_0 rise@0.000ns - clk_out1_d_1_clk_core_0 rise@0.000ns)
  Data Path Delay:        1.467ns  (logic 0.055ns (3.749%)  route 1.412ns (96.251%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.458ns
    Source Clock Delay      (SCD):    2.689ns
    Clock Pessimism Removal (CPR):    -0.287ns
  Clock Net Delay (Source):      1.029ns (routing 0.518ns, distribution 0.511ns)
  Clock Net Delay (Destination): 1.141ns (routing 0.574ns, distribution 0.567ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.029     2.689    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y222        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y222        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.727 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.720     3.447    d_1_i/rst_core/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y99         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     3.464 r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=1968, routed)        0.692     4.156    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]_0
    SLICE_X59Y261        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.141     2.458    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X59Y261        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]/C
                         clock pessimism              0.287     2.745    
    SLICE_X59Y261        FDCE (Remov_FFF_SLICEL_C_CLR)
                                                     -0.020     2.725    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_wr_ptr/count_gray_r_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.725    
                         arrival time                           4.156    
  -------------------------------------------------------------------
                         slack                                  1.431    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Setup :            0  Failing Endpoints,  Worst Slack        6.960ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.153ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             6.960ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[14]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.425ns  (logic 0.107ns (4.412%)  route 2.318ns (95.588%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.419ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.982ns = ( 11.982 - 10.000 ) 
    Source Clock Delay      (SCD):    2.513ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.287ns (routing 0.670ns, distribution 1.617ns)
  Clock Net Delay (Destination): 1.800ns (routing 0.606ns, distribution 1.194ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.287     2.513    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y157        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y157        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.592 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.052     3.644    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y92         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.672 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=18133, routed)       1.266     4.938    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X50Y197        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[14]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.800    11.982    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X50Y197        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[14]/C
                         clock pessimism              0.112    12.094    
                         clock uncertainty           -0.130    11.964    
    SLICE_X50Y197        FDCE (Recov_CFF_SLICEL_C_CLR)
                                                     -0.066    11.898    d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[14]
  -------------------------------------------------------------------
                         required time                         11.898    
                         arrival time                          -4.938    
  -------------------------------------------------------------------
                         slack                                  6.960    

Slack (MET) :             6.960ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[15]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.425ns  (logic 0.107ns (4.412%)  route 2.318ns (95.588%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.419ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.982ns = ( 11.982 - 10.000 ) 
    Source Clock Delay      (SCD):    2.513ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.287ns (routing 0.670ns, distribution 1.617ns)
  Clock Net Delay (Destination): 1.800ns (routing 0.606ns, distribution 1.194ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.287     2.513    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y157        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y157        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.592 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.052     3.644    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y92         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.672 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=18133, routed)       1.266     4.938    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X50Y197        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[15]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.800    11.982    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X50Y197        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[15]/C
                         clock pessimism              0.112    12.094    
                         clock uncertainty           -0.130    11.964    
    SLICE_X50Y197        FDCE (Recov_BFF_SLICEL_C_CLR)
                                                     -0.066    11.898    d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[15]
  -------------------------------------------------------------------
                         required time                         11.898    
                         arrival time                          -4.938    
  -------------------------------------------------------------------
                         slack                                  6.960    

Slack (MET) :             6.960ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[23]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.426ns  (logic 0.107ns (4.411%)  route 2.319ns (95.589%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.418ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.983ns = ( 11.983 - 10.000 ) 
    Source Clock Delay      (SCD):    2.513ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.287ns (routing 0.670ns, distribution 1.617ns)
  Clock Net Delay (Destination): 1.801ns (routing 0.606ns, distribution 1.195ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.287     2.513    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y157        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y157        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.592 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.052     3.644    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y92         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.672 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=18133, routed)       1.267     4.939    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X51Y196        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[23]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.801    11.983    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X51Y196        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[23]/C
                         clock pessimism              0.112    12.095    
                         clock uncertainty           -0.130    11.965    
    SLICE_X51Y196        FDCE (Recov_DFF_SLICEL_C_CLR)
                                                     -0.066    11.899    d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[23]
  -------------------------------------------------------------------
                         required time                         11.899    
                         arrival time                          -4.939    
  -------------------------------------------------------------------
                         slack                                  6.960    

Slack (MET) :             6.960ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[24]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.425ns  (logic 0.107ns (4.412%)  route 2.318ns (95.588%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.419ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.982ns = ( 11.982 - 10.000 ) 
    Source Clock Delay      (SCD):    2.513ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.287ns (routing 0.670ns, distribution 1.617ns)
  Clock Net Delay (Destination): 1.800ns (routing 0.606ns, distribution 1.194ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.287     2.513    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y157        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y157        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.592 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.052     3.644    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y92         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.672 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=18133, routed)       1.266     4.938    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X50Y197        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[24]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.800    11.982    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X50Y197        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[24]/C
                         clock pessimism              0.112    12.094    
                         clock uncertainty           -0.130    11.964    
    SLICE_X50Y197        FDCE (Recov_DFF2_SLICEL_C_CLR)
                                                     -0.066    11.898    d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[24]
  -------------------------------------------------------------------
                         required time                         11.898    
                         arrival time                          -4.938    
  -------------------------------------------------------------------
                         slack                                  6.960    

Slack (MET) :             6.962ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[4]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.427ns  (logic 0.107ns (4.409%)  route 2.320ns (95.591%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.415ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.986ns = ( 11.986 - 10.000 ) 
    Source Clock Delay      (SCD):    2.513ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.287ns (routing 0.670ns, distribution 1.617ns)
  Clock Net Delay (Destination): 1.804ns (routing 0.606ns, distribution 1.198ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.287     2.513    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y157        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y157        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.592 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.052     3.644    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y92         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.672 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=18133, routed)       1.268     4.940    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X51Y194        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[4]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.804    11.986    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X51Y194        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[4]/C
                         clock pessimism              0.112    12.098    
                         clock uncertainty           -0.130    11.968    
    SLICE_X51Y194        FDCE (Recov_HFF_SLICEL_C_CLR)
                                                     -0.066    11.902    d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[4]
  -------------------------------------------------------------------
                         required time                         11.902    
                         arrival time                          -4.940    
  -------------------------------------------------------------------
                         slack                                  6.962    

Slack (MET) :             6.962ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[6]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.427ns  (logic 0.107ns (4.409%)  route 2.320ns (95.591%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.415ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.986ns = ( 11.986 - 10.000 ) 
    Source Clock Delay      (SCD):    2.513ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.287ns (routing 0.670ns, distribution 1.617ns)
  Clock Net Delay (Destination): 1.804ns (routing 0.606ns, distribution 1.198ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.287     2.513    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y157        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y157        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.592 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.052     3.644    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y92         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.672 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=18133, routed)       1.268     4.940    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X51Y194        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.804    11.986    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X51Y194        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[6]/C
                         clock pessimism              0.112    12.098    
                         clock uncertainty           -0.130    11.968    
    SLICE_X51Y194        FDCE (Recov_GFF_SLICEL_C_CLR)
                                                     -0.066    11.902    d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[6]
  -------------------------------------------------------------------
                         required time                         11.902    
                         arrival time                          -4.940    
  -------------------------------------------------------------------
                         slack                                  6.962    

Slack (MET) :             6.962ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_STATUS_reg[0]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.427ns  (logic 0.107ns (4.409%)  route 2.320ns (95.591%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.415ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.986ns = ( 11.986 - 10.000 ) 
    Source Clock Delay      (SCD):    2.513ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.287ns (routing 0.670ns, distribution 1.617ns)
  Clock Net Delay (Destination): 1.804ns (routing 0.606ns, distribution 1.198ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.287     2.513    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y157        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y157        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.592 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.052     3.644    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y92         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.672 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=18133, routed)       1.268     4.940    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X51Y194        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_STATUS_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.804    11.986    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X51Y194        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_STATUS_reg[0]/C
                         clock pessimism              0.112    12.098    
                         clock uncertainty           -0.130    11.968    
    SLICE_X51Y194        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066    11.902    d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_STATUS_reg[0]
  -------------------------------------------------------------------
                         required time                         11.902    
                         arrival time                          -4.940    
  -------------------------------------------------------------------
                         slack                                  6.962    

Slack (MET) :             6.962ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_STATUS_reg[1]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.427ns  (logic 0.107ns (4.409%)  route 2.320ns (95.591%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.415ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.986ns = ( 11.986 - 10.000 ) 
    Source Clock Delay      (SCD):    2.513ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.287ns (routing 0.670ns, distribution 1.617ns)
  Clock Net Delay (Destination): 1.804ns (routing 0.606ns, distribution 1.198ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.287     2.513    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y157        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y157        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.592 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.052     3.644    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y92         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.672 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=18133, routed)       1.268     4.940    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X51Y194        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_STATUS_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.804    11.986    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X51Y194        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_STATUS_reg[1]/C
                         clock pessimism              0.112    12.098    
                         clock uncertainty           -0.130    11.968    
    SLICE_X51Y194        FDCE (Recov_EFF2_SLICEL_C_CLR)
                                                     -0.066    11.902    d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_STATUS_reg[1]
  -------------------------------------------------------------------
                         required time                         11.902    
                         arrival time                          -4.940    
  -------------------------------------------------------------------
                         slack                                  6.962    

Slack (MET) :             6.962ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_STATUS_reg[2]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.427ns  (logic 0.107ns (4.409%)  route 2.320ns (95.591%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.415ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.986ns = ( 11.986 - 10.000 ) 
    Source Clock Delay      (SCD):    2.513ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.287ns (routing 0.670ns, distribution 1.617ns)
  Clock Net Delay (Destination): 1.804ns (routing 0.606ns, distribution 1.198ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.287     2.513    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y157        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y157        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.592 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.052     3.644    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y92         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.672 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=18133, routed)       1.268     4.940    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X51Y194        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_STATUS_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.804    11.986    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X51Y194        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_STATUS_reg[2]/C
                         clock pessimism              0.112    12.098    
                         clock uncertainty           -0.130    11.968    
    SLICE_X51Y194        FDCE (Recov_FFF_SLICEL_C_CLR)
                                                     -0.066    11.902    d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_STATUS_reg[2]
  -------------------------------------------------------------------
                         required time                         11.902    
                         arrival time                          -4.940    
  -------------------------------------------------------------------
                         slack                                  6.962    

Slack (MET) :             6.963ns  (required time - arrival time)
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[28]/CLR
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk_pl_0 rise@10.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        2.409ns  (logic 0.107ns (4.442%)  route 2.302ns (95.558%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.432ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.969ns = ( 11.969 - 10.000 ) 
    Source Clock Delay      (SCD):    2.513ns
    Clock Pessimism Removal (CPR):    0.112ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.287ns (routing 0.670ns, distribution 1.617ns)
  Clock Net Delay (Destination): 1.787ns (routing 0.606ns, distribution 1.181ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.287     2.513    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y157        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y157        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.592 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.052     3.644    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y92         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.672 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=18133, routed)       1.250     4.922    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL_n_1
    SLICE_X51Y209        FDCE                                         f  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[28]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                     10.000    10.000 r  
    PS8_X0Y0             PS8                          0.000    10.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157    10.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025    10.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.787    11.969    d_1_i/qick_processor_0/inst/QPROC/ps_clk_i
    SLICE_X51Y209        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[28]/C
                         clock pessimism              0.112    12.081    
                         clock uncertainty           -0.130    11.951    
    SLICE_X51Y209        FDCE (Recov_HFF_SLICEL_C_CLR)
                                                     -0.066    11.885    d_1_i/qick_processor_0/inst/QPROC/AXI_DB.xreg_TPROC_DEBUG_reg[28]
  -------------------------------------------------------------------
                         required time                         11.885    
                         arrival time                          -4.922    
  -------------------------------------------------------------------
                         slack                                  6.963    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.153ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.181ns  (logic 0.060ns (33.111%)  route 0.121ns (66.889%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.457ns
    Source Clock Delay      (SCD):    1.288ns
    Clock Pessimism Removal (CPR):    0.122ns
  Clock Net Delay (Source):      1.168ns (routing 0.363ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.310ns (routing 0.408ns, distribution 0.902ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.168     1.288    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X27Y187        FDRE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y187        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.326 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.028     1.354    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X27Y187        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.022     1.376 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.093     1.469    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X26Y187        FDPE                                         f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.310     1.457    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X26Y187        FDPE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg/C
                         clock pessimism             -0.122     1.335    
    SLICE_X26Y187        FDPE (Remov_EFF_SLICEL_C_PRE)
                                                     -0.020     1.315    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_fb_i_reg
  -------------------------------------------------------------------
                         required time                         -1.315    
                         arrival time                           1.469    
  -------------------------------------------------------------------
                         slack                                  0.153    

Slack (MET) :             0.153ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.181ns  (logic 0.060ns (33.111%)  route 0.121ns (66.889%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.457ns
    Source Clock Delay      (SCD):    1.288ns
    Clock Pessimism Removal (CPR):    0.122ns
  Clock Net Delay (Source):      1.168ns (routing 0.363ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.310ns (routing 0.408ns, distribution 0.902ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.168     1.288    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X27Y187        FDRE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y187        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.326 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.028     1.354    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X27Y187        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.022     1.376 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.093     1.469    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X26Y187        FDPE                                         f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.310     1.457    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X26Y187        FDPE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg/C
                         clock pessimism             -0.122     1.335    
    SLICE_X26Y187        FDPE (Remov_EFF2_SLICEL_C_PRE)
                                                     -0.020     1.315    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/aempty_fwft_i_reg
  -------------------------------------------------------------------
                         required time                         -1.315    
                         arrival time                           1.469    
  -------------------------------------------------------------------
                         slack                                  0.153    

Slack (MET) :             0.153ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.181ns  (logic 0.060ns (33.111%)  route 0.121ns (66.889%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.457ns
    Source Clock Delay      (SCD):    1.288ns
    Clock Pessimism Removal (CPR):    0.122ns
  Clock Net Delay (Source):      1.168ns (routing 0.363ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.310ns (routing 0.408ns, distribution 0.902ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.168     1.288    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X27Y187        FDRE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y187        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.326 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.028     1.354    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X27Y187        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.022     1.376 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.093     1.469    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X26Y187        FDPE                                         f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.310     1.457    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X26Y187        FDPE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg/C
                         clock pessimism             -0.122     1.335    
    SLICE_X26Y187        FDPE (Remov_FFF_SLICEL_C_PRE)
                                                     -0.020     1.315    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_i_reg
  -------------------------------------------------------------------
                         required time                         -1.315    
                         arrival time                           1.469    
  -------------------------------------------------------------------
                         slack                                  0.153    

Slack (MET) :             0.153ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.181ns  (logic 0.060ns (33.111%)  route 0.121ns (66.889%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.048ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.457ns
    Source Clock Delay      (SCD):    1.288ns
    Clock Pessimism Removal (CPR):    0.122ns
  Clock Net Delay (Source):      1.168ns (routing 0.363ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.310ns (routing 0.408ns, distribution 0.902ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.168     1.288    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X27Y187        FDRE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y187        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.326 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.028     1.354    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X27Y187        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.022     1.376 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.093     1.469    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X26Y187        FDPE                                         f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.310     1.457    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X26Y187        FDPE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg/C
                         clock pessimism             -0.122     1.335    
    SLICE_X26Y187        FDPE (Remov_FFF2_SLICEL_C_PRE)
                                                     -0.020     1.315    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_i_reg
  -------------------------------------------------------------------
                         required time                         -1.315    
                         arrival time                           1.469    
  -------------------------------------------------------------------
                         slack                                  0.153    

Slack (MET) :             0.157ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.181ns  (logic 0.060ns (33.111%)  route 0.121ns (66.889%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.044ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.453ns
    Source Clock Delay      (SCD):    1.288ns
    Clock Pessimism Removal (CPR):    0.122ns
  Clock Net Delay (Source):      1.168ns (routing 0.363ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.306ns (routing 0.408ns, distribution 0.898ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.168     1.288    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X27Y187        FDRE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y187        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.326 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.028     1.354    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X27Y187        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.022     1.376 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.093     1.469    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X26Y187        FDPE                                         f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.306     1.453    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X26Y187        FDPE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg/C
                         clock pessimism             -0.122     1.331    
    SLICE_X26Y187        FDPE (Remov_DFF2_SLICEL_C_PRE)
                                                     -0.020     1.311    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/empty_fwft_fb_o_i_reg
  -------------------------------------------------------------------
                         required time                         -1.311    
                         arrival time                           1.469    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.157ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.181ns  (logic 0.060ns (33.111%)  route 0.121ns (66.889%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.044ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.453ns
    Source Clock Delay      (SCD):    1.288ns
    Clock Pessimism Removal (CPR):    0.122ns
  Clock Net Delay (Source):      1.168ns (routing 0.363ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.306ns (routing 0.408ns, distribution 0.898ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.168     1.288    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X27Y187        FDRE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y187        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.326 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.028     1.354    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X27Y187        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.022     1.376 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.093     1.469    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X26Y187        FDCE                                         f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.306     1.453    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X26Y187        FDCE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]/C
                         clock pessimism             -0.122     1.331    
    SLICE_X26Y187        FDCE (Remov_CFF_SLICEL_C_CLR)
                                                     -0.020     1.311    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.311    
                         arrival time                           1.469    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.157ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.181ns  (logic 0.060ns (33.111%)  route 0.121ns (66.889%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.044ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.453ns
    Source Clock Delay      (SCD):    1.288ns
    Clock Pessimism Removal (CPR):    0.122ns
  Clock Net Delay (Source):      1.168ns (routing 0.363ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.306ns (routing 0.408ns, distribution 0.898ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.168     1.288    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X27Y187        FDRE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y187        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.326 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.028     1.354    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X27Y187        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.022     1.376 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.093     1.469    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X26Y187        FDCE                                         f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.306     1.453    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X26Y187        FDCE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]/C
                         clock pessimism             -0.122     1.331    
    SLICE_X26Y187        FDCE (Remov_CFF2_SLICEL_C_CLR)
                                                     -0.020     1.311    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.curr_fwft_state_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.311    
                         arrival time                           1.469    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.157ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.181ns  (logic 0.060ns (33.111%)  route 0.121ns (66.889%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.044ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.453ns
    Source Clock Delay      (SCD):    1.288ns
    Clock Pessimism Removal (CPR):    0.122ns
  Clock Net Delay (Source):      1.168ns (routing 0.363ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.306ns (routing 0.408ns, distribution 0.898ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.168     1.288    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X27Y187        FDRE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X27Y187        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.326 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.028     1.354    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X27Y187        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.022     1.376 f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.093     1.469    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg_0
    SLICE_X26Y187        FDCE                                         f  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.306     1.453    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/clk
    SLICE_X26Y187        FDCE                                         r  d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg/C
                         clock pessimism             -0.122     1.331    
    SLICE_X26Y187        FDCE (Remov_BFF2_SLICEL_C_CLR)
                                                     -0.020     1.311    d_1_i/ps8_0_axi_periph/m09_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gpregsm1.user_valid_reg
  -------------------------------------------------------------------
                         required time                         -1.311    
                         arrival time                           1.469    
  -------------------------------------------------------------------
                         slack                                  0.157    

Slack (MET) :             0.166ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.204ns  (logic 0.060ns (29.425%)  route 0.144ns (70.575%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.058ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.412ns
    Source Clock Delay      (SCD):    1.236ns
    Clock Pessimism Removal (CPR):    0.118ns
  Clock Net Delay (Source):      1.116ns (routing 0.363ns, distribution 0.753ns)
  Clock Net Delay (Destination): 1.265ns (routing 0.408ns, distribution 0.857ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.116     1.236    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X45Y190        FDRE                                         r  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y190        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.274 f  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.028     1.302    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X45Y190        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.022     1.324 f  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.116     1.439    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X43Y190        FDCE                                         f  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.265     1.412    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X43Y190        FDCE                                         r  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]/C
                         clock pessimism             -0.118     1.294    
    SLICE_X43Y190        FDCE (Remov_EFF_SLICEL_C_CLR)
                                                     -0.020     1.274    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_d1_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.274    
                         arrival time                           1.439    
  -------------------------------------------------------------------
                         slack                                  0.166    

Slack (MET) :             0.166ns  (arrival time - required time)
  Source:                 d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/CLR
                            (removal check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk_pl_0 rise@0.000ns - clk_pl_0 rise@0.000ns)
  Data Path Delay:        0.204ns  (logic 0.060ns (29.425%)  route 0.144ns (70.575%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.058ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.412ns
    Source Clock Delay      (SCD):    1.236ns
    Clock Pessimism Removal (CPR):    0.118ns
  Clock Net Delay (Source):      1.116ns (routing 0.363ns, distribution 0.753ns)
  Clock Net Delay (Destination): 1.265ns (routing 0.408ns, distribution 0.857ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.116     1.236    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/clk
    SLICE_X45Y190        FDRE                                         r  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y190        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.274 f  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc_reg[0]/Q
                         net (fo=3, routed)           0.028     1.302    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.gcc_rst.sckt_wr_rst_cc[0]
    SLICE_X45Y190        LUT3 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.022     1.324 f  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/gpregsm1.curr_fwft_state[1]_i_2/O
                         net (fo=32, routed)          0.116     1.439    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/AR[0]
    SLICE_X43Y190        FDCE                                         f  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.265     1.412    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/clk
    SLICE_X43Y190        FDCE                                         r  d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]/C
                         clock pessimism             -0.118     1.294    
    SLICE_X43Y190        FDCE (Remov_FFF2_SLICEL_C_CLR)
                                                     -0.020     1.274    d_1_i/ps8_0_axi_periph/m08_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gcc0.gc0.count_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.274    
                         arrival time                           1.439    
  -------------------------------------------------------------------
                         slack                                  0.166    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Setup :            0  Failing Endpoints,  Worst Slack       48.923ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.113ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             48.923ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.945ns  (logic 0.269ns (28.475%)  route 0.676ns (71.525%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.188ns = ( 53.188 - 50.000 ) 
    Source Clock Delay      (SCD):    7.690ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.940ns (routing 1.068ns, distribution 0.872ns)
  Clock Net Delay (Destination): 1.717ns (routing 0.968ns, distribution 0.749ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.940     7.690    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y80        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.771 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.227     7.998    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X106Y80        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.123     8.121 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.050     8.171    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X106Y80        LUT4 (Prop_H5LUT_SLICEL_I3_O)
                                                      0.065     8.236 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.399     8.635    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X106Y75        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982    51.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.717    53.188    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X106Y75        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]/C
                         clock pessimism              4.472    57.660    
                         clock uncertainty           -0.035    57.624    
    SLICE_X106Y75        FDCE (Recov_AFF_SLICEL_C_CLR)
                                                     -0.066    57.558    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[14]
  -------------------------------------------------------------------
                         required time                         57.558    
                         arrival time                          -8.635    
  -------------------------------------------------------------------
                         slack                                 48.923    

Slack (MET) :             48.923ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.945ns  (logic 0.269ns (28.475%)  route 0.676ns (71.525%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.188ns = ( 53.188 - 50.000 ) 
    Source Clock Delay      (SCD):    7.690ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.940ns (routing 1.068ns, distribution 0.872ns)
  Clock Net Delay (Destination): 1.717ns (routing 0.968ns, distribution 0.749ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.940     7.690    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y80        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.771 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.227     7.998    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X106Y80        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.123     8.121 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.050     8.171    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X106Y80        LUT4 (Prop_H5LUT_SLICEL_I3_O)
                                                      0.065     8.236 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.399     8.635    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X106Y75        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982    51.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.717    53.188    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X106Y75        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]/C
                         clock pessimism              4.472    57.660    
                         clock uncertainty           -0.035    57.624    
    SLICE_X106Y75        FDCE (Recov_AFF2_SLICEL_C_CLR)
                                                     -0.066    57.558    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[15]
  -------------------------------------------------------------------
                         required time                         57.558    
                         arrival time                          -8.635    
  -------------------------------------------------------------------
                         slack                                 48.923    

Slack (MET) :             48.926ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.944ns  (logic 0.269ns (28.505%)  route 0.675ns (71.495%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.190ns = ( 53.190 - 50.000 ) 
    Source Clock Delay      (SCD):    7.690ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.940ns (routing 1.068ns, distribution 0.872ns)
  Clock Net Delay (Destination): 1.719ns (routing 0.968ns, distribution 0.751ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.940     7.690    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y80        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.771 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.227     7.998    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X106Y80        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.123     8.121 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.050     8.171    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X106Y80        LUT4 (Prop_H5LUT_SLICEL_I3_O)
                                                      0.065     8.236 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.398     8.634    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X106Y75        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982    51.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.719    53.190    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X106Y75        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]/C
                         clock pessimism              4.472    57.662    
                         clock uncertainty           -0.035    57.626    
    SLICE_X106Y75        FDCE (Recov_EFF_SLICEL_C_CLR)
                                                     -0.066    57.560    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[10]
  -------------------------------------------------------------------
                         required time                         57.560    
                         arrival time                          -8.634    
  -------------------------------------------------------------------
                         slack                                 48.926    

Slack (MET) :             48.926ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.944ns  (logic 0.269ns (28.505%)  route 0.675ns (71.495%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.190ns = ( 53.190 - 50.000 ) 
    Source Clock Delay      (SCD):    7.690ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.940ns (routing 1.068ns, distribution 0.872ns)
  Clock Net Delay (Destination): 1.719ns (routing 0.968ns, distribution 0.751ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.940     7.690    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y80        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.771 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.227     7.998    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X106Y80        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.123     8.121 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.050     8.171    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X106Y80        LUT4 (Prop_H5LUT_SLICEL_I3_O)
                                                      0.065     8.236 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.398     8.634    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X106Y75        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982    51.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.719    53.190    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X106Y75        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]/C
                         clock pessimism              4.472    57.662    
                         clock uncertainty           -0.035    57.626    
    SLICE_X106Y75        FDCE (Recov_EFF2_SLICEL_C_CLR)
                                                     -0.066    57.560    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[11]
  -------------------------------------------------------------------
                         required time                         57.560    
                         arrival time                          -8.634    
  -------------------------------------------------------------------
                         slack                                 48.926    

Slack (MET) :             48.926ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.944ns  (logic 0.269ns (28.505%)  route 0.675ns (71.495%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.190ns = ( 53.190 - 50.000 ) 
    Source Clock Delay      (SCD):    7.690ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.940ns (routing 1.068ns, distribution 0.872ns)
  Clock Net Delay (Destination): 1.719ns (routing 0.968ns, distribution 0.751ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.940     7.690    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y80        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.771 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.227     7.998    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X106Y80        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.123     8.121 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.050     8.171    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X106Y80        LUT4 (Prop_H5LUT_SLICEL_I3_O)
                                                      0.065     8.236 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.398     8.634    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X106Y75        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982    51.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.719    53.190    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X106Y75        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]/C
                         clock pessimism              4.472    57.662    
                         clock uncertainty           -0.035    57.626    
    SLICE_X106Y75        FDCE (Recov_FFF_SLICEL_C_CLR)
                                                     -0.066    57.560    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[12]
  -------------------------------------------------------------------
                         required time                         57.560    
                         arrival time                          -8.634    
  -------------------------------------------------------------------
                         slack                                 48.926    

Slack (MET) :             48.926ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.944ns  (logic 0.269ns (28.505%)  route 0.675ns (71.495%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.190ns = ( 53.190 - 50.000 ) 
    Source Clock Delay      (SCD):    7.690ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.940ns (routing 1.068ns, distribution 0.872ns)
  Clock Net Delay (Destination): 1.719ns (routing 0.968ns, distribution 0.751ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.940     7.690    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y80        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.771 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.227     7.998    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X106Y80        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.123     8.121 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.050     8.171    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X106Y80        LUT4 (Prop_H5LUT_SLICEL_I3_O)
                                                      0.065     8.236 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.398     8.634    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X106Y75        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982    51.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.719    53.190    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X106Y75        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]/C
                         clock pessimism              4.472    57.662    
                         clock uncertainty           -0.035    57.626    
    SLICE_X106Y75        FDCE (Recov_FFF2_SLICEL_C_CLR)
                                                     -0.066    57.560    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[13]
  -------------------------------------------------------------------
                         required time                         57.560    
                         arrival time                          -8.634    
  -------------------------------------------------------------------
                         slack                                 48.926    

Slack (MET) :             48.926ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.944ns  (logic 0.269ns (28.505%)  route 0.675ns (71.495%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.190ns = ( 53.190 - 50.000 ) 
    Source Clock Delay      (SCD):    7.690ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.940ns (routing 1.068ns, distribution 0.872ns)
  Clock Net Delay (Destination): 1.719ns (routing 0.968ns, distribution 0.751ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.940     7.690    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y80        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.771 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.227     7.998    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X106Y80        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.123     8.121 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.050     8.171    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X106Y80        LUT4 (Prop_H5LUT_SLICEL_I3_O)
                                                      0.065     8.236 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.398     8.634    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X106Y75        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982    51.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.719    53.190    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X106Y75        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]/C
                         clock pessimism              4.472    57.662    
                         clock uncertainty           -0.035    57.626    
    SLICE_X106Y75        FDCE (Recov_GFF_SLICEL_C_CLR)
                                                     -0.066    57.560    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]
  -------------------------------------------------------------------
                         required time                         57.560    
                         arrival time                          -8.634    
  -------------------------------------------------------------------
                         slack                                 48.926    

Slack (MET) :             48.926ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.944ns  (logic 0.269ns (28.505%)  route 0.675ns (71.495%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.190ns = ( 53.190 - 50.000 ) 
    Source Clock Delay      (SCD):    7.690ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.940ns (routing 1.068ns, distribution 0.872ns)
  Clock Net Delay (Destination): 1.719ns (routing 0.968ns, distribution 0.751ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.940     7.690    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y80        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.771 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.227     7.998    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X106Y80        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.123     8.121 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.050     8.171    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X106Y80        LUT4 (Prop_H5LUT_SLICEL_I3_O)
                                                      0.065     8.236 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.398     8.634    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X106Y75        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982    51.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.719    53.190    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X106Y75        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]/C
                         clock pessimism              4.472    57.662    
                         clock uncertainty           -0.035    57.626    
    SLICE_X106Y75        FDCE (Recov_GFF2_SLICEL_C_CLR)
                                                     -0.066    57.560    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[7]
  -------------------------------------------------------------------
                         required time                         57.560    
                         arrival time                          -8.634    
  -------------------------------------------------------------------
                         slack                                 48.926    

Slack (MET) :             48.926ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.944ns  (logic 0.269ns (28.505%)  route 0.675ns (71.495%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.190ns = ( 53.190 - 50.000 ) 
    Source Clock Delay      (SCD):    7.690ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.940ns (routing 1.068ns, distribution 0.872ns)
  Clock Net Delay (Destination): 1.719ns (routing 0.968ns, distribution 0.751ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.940     7.690    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y80        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.771 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.227     7.998    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X106Y80        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.123     8.121 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.050     8.171    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X106Y80        LUT4 (Prop_H5LUT_SLICEL_I3_O)
                                                      0.065     8.236 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.398     8.634    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X106Y75        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982    51.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.719    53.190    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X106Y75        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]/C
                         clock pessimism              4.472    57.662    
                         clock uncertainty           -0.035    57.626    
    SLICE_X106Y75        FDCE (Recov_HFF_SLICEL_C_CLR)
                                                     -0.066    57.560    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[8]
  -------------------------------------------------------------------
                         required time                         57.560    
                         arrival time                          -8.634    
  -------------------------------------------------------------------
                         slack                                 48.926    

Slack (MET) :             48.926ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/CLR
                            (recovery check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            50.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@50.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.944ns  (logic 0.269ns (28.505%)  route 0.675ns (71.495%))
  Logic Levels:           2  (LUT4=1 LUT6=1)
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.190ns = ( 53.190 - 50.000 ) 
    Source Clock Delay      (SCD):    7.690ns
    Clock Pessimism Removal (CPR):    4.472ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.940ns (routing 1.068ns, distribution 0.872ns)
  Clock Net Delay (Destination): 1.719ns (routing 0.968ns, distribution 0.751ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.940     7.690    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y80        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.771 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno_reg[1]/Q
                         net (fo=1, routed)           0.227     7.998    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/portno[1]
    SLICE_X106Y80        LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.123     8.121 f  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1/O
                         net (fo=5, routed)           0.050     8.171    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_drck[0]_INST_0_i_1_n_0
    SLICE_X106Y80        LUT4 (Prop_H5LUT_SLICEL_I3_O)
                                                      0.065     8.236 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/m_bscan_sel[0]_INST_0/O
                         net (fo=11, routed)          0.398     8.634    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[6]_0
    SLICE_X106Y75        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                     50.000    50.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000    50.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465    50.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982    51.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    51.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.719    53.190    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/m_bscan_tck[0]
    SLICE_X106Y75        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]/C
                         clock pessimism              4.472    57.662    
                         clock uncertainty           -0.035    57.626    
    SLICE_X106Y75        FDCE (Recov_HFF2_SLICEL_C_CLR)
                                                     -0.066    57.560    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/U_CMD/iTARGET_reg[9]
  -------------------------------------------------------------------
                         required time                         57.560    
                         arrival time                          -8.634    
  -------------------------------------------------------------------
                         slack                                 48.926    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.113ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.140ns  (logic 0.039ns (27.857%)  route 0.101ns (72.143%))
  Logic Levels:           0  
  Clock Path Skew:        0.047ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.527ns
    Source Clock Delay      (SCD):    2.310ns
    Clock Pessimism Removal (CPR):    4.171ns
  Clock Net Delay (Source):      1.073ns (routing 0.587ns, distribution 0.486ns)
  Clock Net Delay (Destination): 1.216ns (routing 0.658ns, distribution 0.558ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.073     2.310    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X104Y60        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y60        FDPE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.349 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_wr_reg2_reg/Q
                         net (fo=1, routed)           0.101     2.450    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.rst_wr_reg2
    SLICE_X103Y60        FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.216     6.527    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y60        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg/C
                         clock pessimism             -4.171     2.356    
    SLICE_X103Y60        FDPE (Remov_HFF2_SLICEM_C_PRE)
                                                     -0.020     2.336    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
  -------------------------------------------------------------------
                         required time                         -2.336    
                         arrival time                           2.450    
  -------------------------------------------------------------------
                         slack                                  0.113    

Slack (MET) :             0.113ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.136ns  (logic 0.039ns (28.676%)  route 0.097ns (71.324%))
  Logic Levels:           0  
  Clock Path Skew:        0.043ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.496ns
    Source Clock Delay      (SCD):    2.309ns
    Clock Pessimism Removal (CPR):    4.145ns
  Clock Net Delay (Source):      1.072ns (routing 0.587ns, distribution 0.485ns)
  Clock Net Delay (Destination): 1.185ns (routing 0.658ns, distribution 0.527ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.072     2.309    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X104Y60        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y60        FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.348 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rst_rd_reg2_reg/Q
                         net (fo=1, routed)           0.097     2.445    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rst_rd_reg2
    SLICE_X104Y59        FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.185     6.496    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X104Y59        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg/C
                         clock pessimism             -4.145     2.351    
    SLICE_X104Y59        FDPE (Remov_HFF2_SLICEM_C_PRE)
                                                     -0.020     2.331    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
  -------------------------------------------------------------------
                         required time                         -2.331    
                         arrival time                           2.445    
  -------------------------------------------------------------------
                         slack                                  0.113    

Slack (MET) :             0.128ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[3]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.148ns  (logic 0.038ns (25.602%)  route 0.110ns (74.398%))
  Logic Levels:           0  
  Clock Path Skew:        0.041ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.518ns
    Source Clock Delay      (SCD):    2.307ns
    Clock Pessimism Removal (CPR):    4.171ns
  Clock Net Delay (Source):      1.070ns (routing 0.587ns, distribution 0.483ns)
  Clock Net Delay (Destination): 1.207ns (routing 0.658ns, distribution 0.549ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.070     2.307    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y61        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y61        FDPE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.345 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=18, routed)          0.110     2.455    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/AR[0]
    SLICE_X102Y61        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[3]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.207     6.518    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X102Y61        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[3]/C
                         clock pessimism             -4.171     2.347    
    SLICE_X102Y61        FDCE (Remov_AFF_SLICEL_C_CLR)
                                                     -0.020     2.327    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_bin_reg[3]
  -------------------------------------------------------------------
                         required time                         -2.327    
                         arrival time                           2.455    
  -------------------------------------------------------------------
                         slack                                  0.128    

Slack (MET) :             0.128ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.148ns  (logic 0.038ns (25.602%)  route 0.110ns (74.398%))
  Logic Levels:           0  
  Clock Path Skew:        0.041ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.518ns
    Source Clock Delay      (SCD):    2.307ns
    Clock Pessimism Removal (CPR):    4.171ns
  Clock Net Delay (Source):      1.070ns (routing 0.587ns, distribution 0.483ns)
  Clock Net Delay (Destination): 1.207ns (routing 0.658ns, distribution 0.549ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.070     2.307    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y61        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y61        FDPE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.345 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=18, routed)          0.110     2.455    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg_2[0]
    SLICE_X102Y61        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.207     6.518    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/wr_clk
    SLICE_X102Y61        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg/C
                         clock pessimism             -4.171     2.347    
    SLICE_X102Y61        FDCE (Remov_AFF2_SLICEL_C_CLR)
                                                     -0.020     2.327    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg
  -------------------------------------------------------------------
                         required time                         -2.327    
                         arrival time                           2.455    
  -------------------------------------------------------------------
                         slack                                  0.128    

Slack (MET) :             0.128ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.148ns  (logic 0.038ns (25.602%)  route 0.110ns (74.398%))
  Logic Levels:           0  
  Clock Path Skew:        0.041ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.518ns
    Source Clock Delay      (SCD):    2.307ns
    Clock Pessimism Removal (CPR):    4.171ns
  Clock Net Delay (Source):      1.070ns (routing 0.587ns, distribution 0.483ns)
  Clock Net Delay (Destination): 1.207ns (routing 0.658ns, distribution 0.549ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.070     2.307    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y61        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y61        FDPE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.345 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=18, routed)          0.110     2.455    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_fb_i_reg_2[0]
    SLICE_X102Y61        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.207     6.518    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/wr_clk
    SLICE_X102Y61        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg/C
                         clock pessimism             -4.171     2.347    
    SLICE_X102Y61        FDCE (Remov_BFF_SLICEL_C_CLR)
                                                     -0.020     2.327    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/ram_full_i_reg
  -------------------------------------------------------------------
                         required time                         -2.327    
                         arrival time                           2.455    
  -------------------------------------------------------------------
                         slack                                  0.128    

Slack (MET) :             0.136ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.161ns  (logic 0.039ns (24.215%)  route 0.122ns (75.786%))
  Logic Levels:           0  
  Clock Path Skew:        0.045ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.522ns
    Source Clock Delay      (SCD):    2.307ns
    Clock Pessimism Removal (CPR):    4.171ns
  Clock Net Delay (Source):      1.070ns (routing 0.587ns, distribution 0.483ns)
  Clock Net Delay (Destination): 1.211ns (routing 0.658ns, distribution 0.553ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.070     2.307    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y61        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y61        FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.346 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.122     2.468    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X102Y60        FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.211     6.522    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X102Y60        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/C
                         clock pessimism             -4.171     2.351    
    SLICE_X102Y60        FDPE (Remov_EFF_SLICEL_C_PRE)
                                                     -0.020     2.331    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.331    
                         arrival time                           2.468    
  -------------------------------------------------------------------
                         slack                                  0.136    

Slack (MET) :             0.136ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.161ns  (logic 0.039ns (24.215%)  route 0.122ns (75.786%))
  Logic Levels:           0  
  Clock Path Skew:        0.045ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.522ns
    Source Clock Delay      (SCD):    2.307ns
    Clock Pessimism Removal (CPR):    4.171ns
  Clock Net Delay (Source):      1.070ns (routing 0.587ns, distribution 0.483ns)
  Clock Net Delay (Destination): 1.211ns (routing 0.658ns, distribution 0.553ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.070     2.307    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y61        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y61        FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.346 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.122     2.468    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X102Y60        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.211     6.522    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X102Y60        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/C
                         clock pessimism             -4.171     2.351    
    SLICE_X102Y60        FDCE (Remov_EFF2_SLICEL_C_CLR)
                                                     -0.020     2.331    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.331    
                         arrival time                           2.468    
  -------------------------------------------------------------------
                         slack                                  0.136    

Slack (MET) :             0.136ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.161ns  (logic 0.039ns (24.215%)  route 0.122ns (75.786%))
  Logic Levels:           0  
  Clock Path Skew:        0.045ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.522ns
    Source Clock Delay      (SCD):    2.307ns
    Clock Pessimism Removal (CPR):    4.171ns
  Clock Net Delay (Source):      1.070ns (routing 0.587ns, distribution 0.483ns)
  Clock Net Delay (Destination): 1.211ns (routing 0.658ns, distribution 0.553ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.070     2.307    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y61        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y61        FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.346 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.122     2.468    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X102Y60        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.211     6.522    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X102Y60        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]/C
                         clock pessimism             -4.171     2.351    
    SLICE_X102Y60        FDCE (Remov_FFF_SLICEL_C_CLR)
                                                     -0.020     2.331    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[1]
  -------------------------------------------------------------------
                         required time                         -2.331    
                         arrival time                           2.468    
  -------------------------------------------------------------------
                         slack                                  0.136    

Slack (MET) :             0.136ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.161ns  (logic 0.039ns (24.215%)  route 0.122ns (75.786%))
  Logic Levels:           0  
  Clock Path Skew:        0.045ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.522ns
    Source Clock Delay      (SCD):    2.307ns
    Clock Pessimism Removal (CPR):    4.171ns
  Clock Net Delay (Source):      1.070ns (routing 0.587ns, distribution 0.483ns)
  Clock Net Delay (Destination): 1.211ns (routing 0.658ns, distribution 0.553ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.070     2.307    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y61        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y61        FDPE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.346 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.122     2.468    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X102Y60        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.211     6.522    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X102Y60        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/C
                         clock pessimism             -4.171     2.351    
    SLICE_X102Y60        FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                     -0.020     2.331    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.331    
                         arrival time                           2.468    
  -------------------------------------------------------------------
                         slack                                  0.136    

Slack (MET) :             0.147ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
                            (rising edge-triggered cell FDPE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/CLR
                            (removal check against rising-edge clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns - dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise@0.000ns)
  Data Path Delay:        0.167ns  (logic 0.038ns (22.705%)  route 0.129ns (77.295%))
  Logic Levels:           0  
  Clock Path Skew:        0.041ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.518ns
    Source Clock Delay      (SCD):    2.307ns
    Clock Pessimism Removal (CPR):    4.171ns
  Clock Net Delay (Source):      1.070ns (routing 0.587ns, distribution 0.483ns)
  Clock Net Delay (Destination): 1.207ns (routing 0.658ns, distribution 0.549ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.070     2.307    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X103Y61        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y61        FDPE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.345 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]/Q
                         net (fo=18, routed)          0.129     2.474    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/AR[0]
    SLICE_X102Y60        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.207     6.518    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X102Y60        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                         clock pessimism             -4.171     2.347    
    SLICE_X102Y60        FDCE (Remov_DFF_SLICEL_C_CLR)
                                                     -0.020     2.327    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]
  -------------------------------------------------------------------
                         required time                         -2.327    
                         arrival time                           2.474    
  -------------------------------------------------------------------
                         slack                                  0.147    





---------------------------------------------------------------------------------------------------
Path Group:  **async_default**
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout5

Setup :            0  Failing Endpoints,  Worst Slack       10.805ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.105ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             10.805ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.018ns  (logic 0.079ns (7.761%)  route 0.939ns (92.239%))
  Logic Levels:           0  
  Clock Path Skew:        -0.038ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.782ns = ( 14.784 - 12.002 ) 
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    -0.437ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.111ns (routing 0.155ns, distribution 0.956ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.939     3.401    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y68        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.111    14.784    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y68        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]/C
                         clock pessimism             -0.437    14.347    
                         clock uncertainty           -0.076    14.272    
    SLICE_X104Y68        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    14.206    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[14]
  -------------------------------------------------------------------
                         required time                         14.206    
                         arrival time                          -3.401    
  -------------------------------------------------------------------
                         slack                                 10.805    

Slack (MET) :             10.805ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.018ns  (logic 0.079ns (7.761%)  route 0.939ns (92.239%))
  Logic Levels:           0  
  Clock Path Skew:        -0.038ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.782ns = ( 14.784 - 12.002 ) 
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    -0.437ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.111ns (routing 0.155ns, distribution 0.956ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.939     3.401    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y68        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.111    14.784    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y68        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]/C
                         clock pessimism             -0.437    14.347    
                         clock uncertainty           -0.076    14.272    
    SLICE_X104Y68        FDCE (Recov_AFF_SLICEM_C_CLR)
                                                     -0.066    14.206    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[15]
  -------------------------------------------------------------------
                         required time                         14.206    
                         arrival time                          -3.401    
  -------------------------------------------------------------------
                         slack                                 10.805    

Slack (MET) :             10.805ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.018ns  (logic 0.079ns (7.761%)  route 0.939ns (92.239%))
  Logic Levels:           0  
  Clock Path Skew:        -0.038ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.782ns = ( 14.784 - 12.002 ) 
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    -0.437ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.111ns (routing 0.155ns, distribution 0.956ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.939     3.401    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y68        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.111    14.784    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y68        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]/C
                         clock pessimism             -0.437    14.347    
                         clock uncertainty           -0.076    14.272    
    SLICE_X104Y68        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    14.206    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[16]
  -------------------------------------------------------------------
                         required time                         14.206    
                         arrival time                          -3.401    
  -------------------------------------------------------------------
                         slack                                 10.805    

Slack (MET) :             10.805ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[18]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        1.018ns  (logic 0.079ns (7.761%)  route 0.939ns (92.239%))
  Logic Levels:           0  
  Clock Path Skew:        -0.038ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.782ns = ( 14.784 - 12.002 ) 
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    -0.437ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.111ns (routing 0.155ns, distribution 0.956ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.939     3.401    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y68        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[18]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.111    14.784    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y68        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[18]/C
                         clock pessimism             -0.437    14.347    
                         clock uncertainty           -0.076    14.272    
    SLICE_X104Y68        FDCE (Recov_AFF2_SLICEM_C_CLR)
                                                     -0.066    14.206    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[18]
  -------------------------------------------------------------------
                         required time                         14.206    
                         arrival time                          -3.401    
  -------------------------------------------------------------------
                         slack                                 10.805    

Slack (MET) :             10.919ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[5]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.914ns  (logic 0.079ns (8.642%)  route 0.835ns (91.358%))
  Logic Levels:           0  
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.792ns = ( 14.795 - 12.002 ) 
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.121ns (routing 0.155ns, distribution 0.966ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.835     3.297    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y66        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[5]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.121    14.795    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y66        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[5]/C
                         clock pessimism             -0.438    14.357    
                         clock uncertainty           -0.076    14.282    
    SLICE_X104Y66        FDCE (Recov_DFF_SLICEM_C_CLR)
                                                     -0.066    14.216    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[5]
  -------------------------------------------------------------------
                         required time                         14.216    
                         arrival time                          -3.297    
  -------------------------------------------------------------------
                         slack                                 10.919    

Slack (MET) :             10.919ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.914ns  (logic 0.079ns (8.642%)  route 0.835ns (91.358%))
  Logic Levels:           0  
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.792ns = ( 14.795 - 12.002 ) 
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.121ns (routing 0.155ns, distribution 0.966ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.835     3.297    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y66        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.121    14.795    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y66        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]/C
                         clock pessimism             -0.438    14.357    
                         clock uncertainty           -0.076    14.282    
    SLICE_X104Y66        FDCE (Recov_CFF_SLICEM_C_CLR)
                                                     -0.066    14.216    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/active_sl_den_mask_reg[0]
  -------------------------------------------------------------------
                         required time                         14.216    
                         arrival time                          -3.297    
  -------------------------------------------------------------------
                         slack                                 10.919    

Slack (MET) :             10.919ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.914ns  (logic 0.079ns (8.642%)  route 0.835ns (91.358%))
  Logic Levels:           0  
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.792ns = ( 14.795 - 12.002 ) 
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.121ns (routing 0.155ns, distribution 0.966ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.835     3.297    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y66        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.121    14.795    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y66        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]/C
                         clock pessimism             -0.438    14.357    
                         clock uncertainty           -0.076    14.282    
    SLICE_X104Y66        FDCE (Recov_BFF_SLICEM_C_CLR)
                                                     -0.066    14.216    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/sl_berr_r_reg[0]
  -------------------------------------------------------------------
                         required time                         14.216    
                         arrival time                          -3.297    
  -------------------------------------------------------------------
                         slack                                 10.919    

Slack (MET) :             10.919ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/timer_rst_reg/PRE
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.914ns  (logic 0.079ns (8.642%)  route 0.835ns (91.358%))
  Logic Levels:           0  
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.792ns = ( 14.795 - 12.002 ) 
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.121ns (routing 0.155ns, distribution 0.966ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.835     3.297    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y66        FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/timer_rst_reg/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.121    14.795    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y66        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/timer_rst_reg/C
                         clock pessimism             -0.438    14.357    
                         clock uncertainty           -0.076    14.282    
    SLICE_X104Y66        FDPE (Recov_AFF_SLICEM_C_PRE)
                                                     -0.066    14.216    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/timer_rst_reg
  -------------------------------------------------------------------
                         required time                         14.216    
                         arrival time                          -3.297    
  -------------------------------------------------------------------
                         slack                                 10.919    

Slack (MET) :             10.921ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[6]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.911ns  (logic 0.079ns (8.670%)  route 0.832ns (91.330%))
  Logic Levels:           0  
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.791ns = ( 14.794 - 12.002 ) 
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.120ns (routing 0.155ns, distribution 0.965ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.832     3.294    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y66        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[6]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.120    14.794    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y66        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[6]/C
                         clock pessimism             -0.438    14.356    
                         clock uncertainty           -0.076    14.281    
    SLICE_X104Y66        FDCE (Recov_HFF_SLICEM_C_CLR)
                                                     -0.066    14.215    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[6]
  -------------------------------------------------------------------
                         required time                         14.215    
                         arrival time                          -3.294    
  -------------------------------------------------------------------
                         slack                                 10.921    

Slack (MET) :             10.921ns  (required time - arrival time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[7]/CLR
                            (recovery check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Recovery (Max at Slow Process Corner)
  Requirement:            12.002ns  (mmcm_clkout5 rise@12.002ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.911ns  (logic 0.079ns (8.670%)  route 0.832ns (91.330%))
  Logic Levels:           0  
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.791ns = ( 14.794 - 12.002 ) 
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    -0.438ns
  Clock Uncertainty:      0.076ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.120ns (routing 0.155ns, distribution 0.965ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.832     3.294    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/out[0]
    SLICE_X104Y66        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[7]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                     12.002    12.002 r  
    AR20                                              0.000    12.002 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000    12.002    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422    12.425 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040    12.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000    12.465 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349    12.814    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630    13.444 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206    13.650    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024    13.674 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.120    14.794    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/clk
    SLICE_X104Y66        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[7]/C
                         clock pessimism             -0.438    14.356    
                         clock uncertainty           -0.076    14.281    
    SLICE_X104Y66        FDCE (Recov_HFF2_SLICEM_C_CLR)
                                                     -0.066    14.215    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_XSDB_BUS_CONTROLLER/FSM_onehot_current_state_reg[7]
  -------------------------------------------------------------------
                         required time                         14.215    
                         arrival time                          -3.294    
  -------------------------------------------------------------------
                         slack                                 10.921    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.105ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.166ns  (logic 0.039ns (23.484%)  route 0.127ns (76.516%))
  Logic Levels:           0  
  Clock Path Skew:        0.081ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.368ns
    Source Clock Delay      (SCD):    1.639ns
    Clock Pessimism Removal (CPR):    -0.352ns
  Clock Net Delay (Source):      0.721ns (routing 0.096ns, distribution 0.625ns)
  Clock Net Delay (Destination): 0.813ns (routing 0.108ns, distribution 0.705ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.721     1.639    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X104Y61        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y61        FDPE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.678 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.127     1.805    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]_0[0]
    SLICE_X102Y59        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.813     1.368    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X102Y59        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/C
                         clock pessimism              0.352     1.720    
    SLICE_X102Y59        FDCE (Remov_HFF2_SLICEL_C_CLR)
                                                     -0.020     1.700    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.700    
                         arrival time                           1.805    
  -------------------------------------------------------------------
                         slack                                  0.105    

Slack (MET) :             0.105ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.166ns  (logic 0.039ns (23.484%)  route 0.127ns (76.516%))
  Logic Levels:           0  
  Clock Path Skew:        0.081ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.368ns
    Source Clock Delay      (SCD):    1.639ns
    Clock Pessimism Removal (CPR):    -0.352ns
  Clock Net Delay (Source):      0.721ns (routing 0.096ns, distribution 0.625ns)
  Clock Net Delay (Destination): 0.813ns (routing 0.108ns, distribution 0.705ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.721     1.639    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X104Y61        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y61        FDPE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.678 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.127     1.805    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]_0[0]
    SLICE_X102Y59        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.813     1.368    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/rd_clk
    SLICE_X102Y59        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[1]/C
                         clock pessimism              0.352     1.720    
    SLICE_X102Y59        FDCE (Remov_EFF2_SLICEL_C_CLR)
                                                     -0.020     1.700    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.700    
                         arrival time                           1.805    
  -------------------------------------------------------------------
                         slack                                  0.105    

Slack (MET) :             0.109ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.166ns  (logic 0.039ns (23.484%)  route 0.127ns (76.516%))
  Logic Levels:           0  
  Clock Path Skew:        0.077ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.364ns
    Source Clock Delay      (SCD):    1.639ns
    Clock Pessimism Removal (CPR):    -0.352ns
  Clock Net Delay (Source):      0.721ns (routing 0.096ns, distribution 0.625ns)
  Clock Net Delay (Destination): 0.809ns (routing 0.108ns, distribution 0.701ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.721     1.639    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X104Y61        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y61        FDPE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.678 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.127     1.805    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]_0[0]
    SLICE_X102Y59        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.809     1.364    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X102Y59        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/C
                         clock pessimism              0.352     1.716    
    SLICE_X102Y59        FDCE (Remov_CFF2_SLICEL_C_CLR)
                                                     -0.020     1.696    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.696    
                         arrival time                           1.805    
  -------------------------------------------------------------------
                         slack                                  0.109    

Slack (MET) :             0.109ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.166ns  (logic 0.039ns (23.484%)  route 0.127ns (76.516%))
  Logic Levels:           0  
  Clock Path Skew:        0.077ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.364ns
    Source Clock Delay      (SCD):    1.639ns
    Clock Pessimism Removal (CPR):    -0.352ns
  Clock Net Delay (Source):      0.721ns (routing 0.096ns, distribution 0.625ns)
  Clock Net Delay (Destination): 0.809ns (routing 0.108ns, distribution 0.701ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.721     1.639    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X104Y61        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y61        FDPE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.678 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.127     1.805    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]_0[0]
    SLICE_X102Y59        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.809     1.364    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/rd_clk
    SLICE_X102Y59        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]/C
                         clock pessimism              0.352     1.716    
    SLICE_X102Y59        FDCE (Remov_AFF2_SLICEL_C_CLR)
                                                     -0.020     1.696    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[2].rd_stg_inst/Q_reg_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.696    
                         arrival time                           1.805    
  -------------------------------------------------------------------
                         slack                                  0.109    

Slack (MET) :             0.109ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.166ns  (logic 0.039ns (23.484%)  route 0.127ns (76.516%))
  Logic Levels:           0  
  Clock Path Skew:        0.077ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.364ns
    Source Clock Delay      (SCD):    1.639ns
    Clock Pessimism Removal (CPR):    -0.352ns
  Clock Net Delay (Source):      0.721ns (routing 0.096ns, distribution 0.625ns)
  Clock Net Delay (Destination): 0.809ns (routing 0.108ns, distribution 0.701ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.721     1.639    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X104Y61        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y61        FDPE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.678 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.127     1.805    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/Q_reg_reg[0][0]
    SLICE_X102Y59        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.809     1.364    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X102Y59        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[0]/C
                         clock pessimism              0.352     1.716    
    SLICE_X102Y59        FDCE (Remov_DFF_SLICEL_C_CLR)
                                                     -0.020     1.696    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.696    
                         arrival time                           1.805    
  -------------------------------------------------------------------
                         slack                                  0.109    

Slack (MET) :             0.109ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.166ns  (logic 0.039ns (23.484%)  route 0.127ns (76.516%))
  Logic Levels:           0  
  Clock Path Skew:        0.077ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.364ns
    Source Clock Delay      (SCD):    1.639ns
    Clock Pessimism Removal (CPR):    -0.352ns
  Clock Net Delay (Source):      0.721ns (routing 0.096ns, distribution 0.625ns)
  Clock Net Delay (Destination): 0.809ns (routing 0.108ns, distribution 0.701ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.721     1.639    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/rd_clk
    SLICE_X104Y61        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X104Y61        FDPE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.678 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]/Q
                         net (fo=16, routed)          0.127     1.805    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/Q_reg_reg[0][0]
    SLICE_X102Y59        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[1]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.809     1.364    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X102Y59        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[1]/C
                         clock pessimism              0.352     1.716    
    SLICE_X102Y59        FDCE (Remov_DFF2_SLICEL_C_CLR)
                                                     -0.020     1.696    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_bin_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.696    
                         arrival time                           1.805    
  -------------------------------------------------------------------
                         slack                                  0.109    

Slack (MET) :             0.120ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.040ns (24.978%)  route 0.120ns (75.022%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.384ns
    Source Clock Delay      (SCD):    1.635ns
    Clock Pessimism Removal (CPR):    -0.312ns
  Clock Net Delay (Source):      0.717ns (routing 0.096ns, distribution 0.621ns)
  Clock Net Delay (Destination): 0.829ns (routing 0.108ns, distribution 0.721ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.717     1.635    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X105Y64        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y64        FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.675 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.120     1.796    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X106Y64        FDPE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.829     1.384    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X106Y64        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]/C
                         clock pessimism              0.312     1.696    
    SLICE_X106Y64        FDPE (Remov_EFF_SLICEL_C_PRE)
                                                     -0.020     1.676    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d1_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.676    
                         arrival time                           1.796    
  -------------------------------------------------------------------
                         slack                                  0.120    

Slack (MET) :             0.120ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.040ns (24.978%)  route 0.120ns (75.022%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.384ns
    Source Clock Delay      (SCD):    1.635ns
    Clock Pessimism Removal (CPR):    -0.312ns
  Clock Net Delay (Source):      0.717ns (routing 0.096ns, distribution 0.621ns)
  Clock Net Delay (Destination): 0.829ns (routing 0.108ns, distribution 0.721ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.717     1.635    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X105Y64        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y64        FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.675 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.120     1.796    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X106Y64        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.829     1.384    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X106Y64        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]/C
                         clock pessimism              0.312     1.696    
    SLICE_X106Y64        FDCE (Remov_EFF2_SLICEL_C_CLR)
                                                     -0.020     1.676    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_d2_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.676    
                         arrival time                           1.796    
  -------------------------------------------------------------------
                         slack                                  0.120    

Slack (MET) :             0.120ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.040ns (24.978%)  route 0.120ns (75.022%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.384ns
    Source Clock Delay      (SCD):    1.635ns
    Clock Pessimism Removal (CPR):    -0.312ns
  Clock Net Delay (Source):      0.717ns (routing 0.096ns, distribution 0.621ns)
  Clock Net Delay (Destination): 0.829ns (routing 0.108ns, distribution 0.721ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.717     1.635    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X105Y64        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y64        FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.675 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.120     1.796    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X106Y64        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.829     1.384    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X106Y64        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]/C
                         clock pessimism              0.312     1.696    
    SLICE_X106Y64        FDCE (Remov_GFF2_SLICEL_C_CLR)
                                                     -0.020     1.676    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]
  -------------------------------------------------------------------
                         required time                         -1.676    
                         arrival time                           1.796    
  -------------------------------------------------------------------
                         slack                                  0.120    

Slack (MET) :             0.120ns  (arrival time - required time)
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
                            (rising edge-triggered cell FDPE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             **async_default**
  Path Type:              Removal (Min at Fast Process Corner)
  Requirement:            0.000ns  (mmcm_clkout5 rise@0.000ns - mmcm_clkout5 rise@0.000ns)
  Data Path Delay:        0.160ns  (logic 0.040ns (24.978%)  route 0.120ns (75.022%))
  Logic Levels:           0  
  Clock Path Skew:        0.060ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.384ns
    Source Clock Delay      (SCD):    1.635ns
    Clock Pessimism Removal (CPR):    -0.312ns
  Clock Net Delay (Source):      0.717ns (routing 0.096ns, distribution 0.621ns)
  Clock Net Delay (Destination): 0.829ns (routing 0.108ns, distribution 0.721ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.717     1.635    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/wr_clk
    SLICE_X105Y64        FDPE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y64        FDPE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.675 f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]/Q
                         net (fo=12, routed)          0.120     1.796    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[0]_0[0]
    SLICE_X106Y64        FDCE                                         f  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/CLR
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.829     1.384    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/wr_clk
    SLICE_X106Y64        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]/C
                         clock pessimism              0.312     1.696    
    SLICE_X106Y64        FDCE (Remov_HFF_SLICEL_C_CLR)
                                                     -0.020     1.676    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/gic0.gc0.count_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.676    
                         arrival time                           1.796    
  -------------------------------------------------------------------
                         slack                                  0.120    





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC2_CLK
  To Clock:  

Max Delay             4 Endpoints
Min Delay             4 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            SPARE1_1V8
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.686ns  (logic 2.454ns (52.359%)  route 2.232ns (47.641%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.913ns (routing 1.474ns, distribution 1.439ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.913     3.624    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X54Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y220        FDCE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     3.704 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                         net (fo=2, routed)           2.232     5.936    SPARE1_1V8_OBUF
    F15                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      2.374     8.310 r  SPARE1_1V8_OBUF_inst/O
                         net (fo=0)                   0.000     8.310    SPARE1_1V8
    F15                                                               r  SPARE1_1V8 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            SPARE2_1V8
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.552ns  (logic 2.476ns (54.384%)  route 2.076ns (45.616%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.924ns (routing 1.474ns, distribution 1.450ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.924     3.635    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X53Y225        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y225        FDCE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     3.715 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/Q
                         net (fo=2, routed)           2.076     5.791    SPARE2_1V8_OBUF
    B13                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      2.396     8.187 r  SPARE2_1V8_OBUF_inst/O
                         net (fo=0)                   0.000     8.187    SPARE2_1V8
    B13                                                               r  SPARE2_1V8 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            SPARE0_1V8
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.484ns  (logic 2.453ns (54.706%)  route 2.031ns (45.294%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.954ns (routing 1.474ns, distribution 1.480ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.954     3.665    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X48Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y220        FDCE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     3.744 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                         net (fo=2, routed)           2.031     5.775    SPARE0_1V8_OBUF
    E14                  OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      2.374     8.149 r  SPARE0_1V8_OBUF_inst/O
                         net (fo=0)                   0.000     8.149    SPARE0_1V8
    E14                                                               r  SPARE0_1V8 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            SPARE3_1V8
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.517ns  (logic 2.477ns (54.833%)  route 2.040ns (45.167%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.911ns (routing 1.474ns, distribution 1.437ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.911     3.622    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X56Y234        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y234        FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     3.700 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/Q
                         net (fo=2, routed)           2.040     5.740    SPARE3_1V8_OBUF
    B12                  OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      2.399     8.139 r  SPARE3_1V8_OBUF_inst/O
                         net (fo=0)                   0.000     8.139    SPARE3_1V8
    B12                                                               r  SPARE3_1V8 (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            SPARE0_1V8
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.140ns  (logic 1.155ns (53.988%)  route 0.985ns (46.012%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.612ns (routing 0.796ns, distribution 0.816ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.612     1.979    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X48Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y220        FDCE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     2.018 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[2]/Q
                         net (fo=2, routed)           0.985     3.002    SPARE0_1V8_OBUF
    E14                  OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      1.116     4.119 r  SPARE0_1V8_OBUF_inst/O
                         net (fo=0)                   0.000     4.119    SPARE0_1V8
    E14                                                               r  SPARE0_1V8 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            SPARE3_1V8
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.176ns  (logic 1.180ns (54.203%)  route 0.997ns (45.797%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.593ns (routing 0.796ns, distribution 0.797ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.593     1.960    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X56Y234        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y234        FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.999 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[5]/Q
                         net (fo=2, routed)           0.997     2.996    SPARE3_1V8_OBUF
    B12                  OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      1.141     4.136 r  SPARE3_1V8_OBUF_inst/O
                         net (fo=0)                   0.000     4.136    SPARE3_1V8
    B12                                                               r  SPARE3_1V8 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            SPARE2_1V8
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.229ns  (logic 1.179ns (52.870%)  route 1.051ns (47.130%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.598ns (routing 0.796ns, distribution 0.802ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.598     1.965    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X53Y225        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y225        FDCE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     2.006 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[4]/Q
                         net (fo=2, routed)           1.051     3.057    SPARE2_1V8_OBUF
    B13                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      1.138     4.194 r  SPARE2_1V8_OBUF_inst/O
                         net (fo=0)                   0.000     4.194    SPARE2_1V8
    B13                                                               r  SPARE2_1V8 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            SPARE1_1V8
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.309ns  (logic 1.157ns (50.091%)  route 1.153ns (49.909%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.593ns (routing 0.796ns, distribution 0.797ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.593     1.960    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X54Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y220        FDCE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     2.001 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[3]/Q
                         net (fo=2, routed)           1.153     3.154    SPARE1_1V8_OBUF
    F15                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      1.116     4.269 r  SPARE1_1V8_OBUF_inst/O
                         net (fo=0)                   0.000     4.269    SPARE1_1V8
    F15                                                               r  SPARE1_1V8 (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFADC2_CLK

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.660ns  (logic 0.110ns (6.625%)  route 1.550ns (93.375%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.868ns (routing 0.801ns, distribution 1.067ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=3, routed)           1.520     1.520    d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X63Y231        LUT1 (Prop_D5LUT_SLICEM_I0_O)
                                                      0.110     1.630 r  d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.030     1.660    d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X63Y231        FDRE                                         r  d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.868     2.254    d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X63Y231        FDRE                                         r  d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.781ns  (logic 0.042ns (5.375%)  route 0.739ns (94.625%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.303ns (routing 0.544ns, distribution 0.759ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=3, routed)           0.730     0.730    d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X63Y231        LUT1 (Prop_D5LUT_SLICEM_I0_O)
                                                      0.042     0.772 r  d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.009     0.781    d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X63Y231        FDRE                                         r  d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.303     1.654    d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X63Y231        FDRE                                         r  d_1_i/rst_adc2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC2_CLK
  To Clock:  RFADC2_CLK

Max Delay          4685 Endpoints
Min Delay          4685 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__11/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.427ns  (logic 0.158ns (3.569%)  route 4.269ns (96.431%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.329ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.301ns
    Source Clock Delay      (SCD):    2.630ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.104ns (routing 0.888ns, distribution 1.216ns)
  Clock Net Delay (Destination): 1.915ns (routing 0.801ns, distribution 1.114ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.104     2.630    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.709 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.364     4.073    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.101 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        1.175     5.276    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aresetn
    SLICE_X66Y250        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.051     5.327 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/i_/O
                         net (fo=58, routed)          1.730     7.057    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/clear
    SLICE_X78Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__11/R
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.915     2.301    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X78Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__11/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__12/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.427ns  (logic 0.158ns (3.569%)  route 4.269ns (96.431%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.329ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.301ns
    Source Clock Delay      (SCD):    2.630ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.104ns (routing 0.888ns, distribution 1.216ns)
  Clock Net Delay (Destination): 1.915ns (routing 0.801ns, distribution 1.114ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.104     2.630    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.709 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.364     4.073    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.101 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        1.175     5.276    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aresetn
    SLICE_X66Y250        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.051     5.327 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/i_/O
                         net (fo=58, routed)          1.730     7.057    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/clear
    SLICE_X78Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__12/R
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.915     2.301    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X78Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__12/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__13/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.427ns  (logic 0.158ns (3.569%)  route 4.269ns (96.431%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.329ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.301ns
    Source Clock Delay      (SCD):    2.630ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.104ns (routing 0.888ns, distribution 1.216ns)
  Clock Net Delay (Destination): 1.915ns (routing 0.801ns, distribution 1.114ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.104     2.630    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.709 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.364     4.073    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.101 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        1.175     5.276    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aresetn
    SLICE_X66Y250        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.051     5.327 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/i_/O
                         net (fo=58, routed)          1.730     7.057    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/clear
    SLICE_X78Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__13/R
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.915     2.301    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X78Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__13/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__10/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.424ns  (logic 0.158ns (3.571%)  route 4.266ns (96.429%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.330ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.300ns
    Source Clock Delay      (SCD):    2.630ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.104ns (routing 0.888ns, distribution 1.216ns)
  Clock Net Delay (Destination): 1.914ns (routing 0.801ns, distribution 1.113ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.104     2.630    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.709 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.364     4.073    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.101 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        1.175     5.276    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aresetn
    SLICE_X66Y250        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.051     5.327 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/i_/O
                         net (fo=58, routed)          1.727     7.054    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/clear
    SLICE_X78Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__10/R
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.914     2.300    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X78Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__10/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__7/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.424ns  (logic 0.158ns (3.571%)  route 4.266ns (96.429%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.330ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.300ns
    Source Clock Delay      (SCD):    2.630ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.104ns (routing 0.888ns, distribution 1.216ns)
  Clock Net Delay (Destination): 1.914ns (routing 0.801ns, distribution 1.113ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.104     2.630    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.709 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.364     4.073    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.101 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        1.175     5.276    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aresetn
    SLICE_X66Y250        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.051     5.327 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/i_/O
                         net (fo=58, routed)          1.727     7.054    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/clear
    SLICE_X78Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__7/R
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.914     2.300    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X78Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__7/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__8/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.424ns  (logic 0.158ns (3.571%)  route 4.266ns (96.429%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.330ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.300ns
    Source Clock Delay      (SCD):    2.630ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.104ns (routing 0.888ns, distribution 1.216ns)
  Clock Net Delay (Destination): 1.914ns (routing 0.801ns, distribution 1.113ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.104     2.630    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.709 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.364     4.073    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.101 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        1.175     5.276    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aresetn
    SLICE_X66Y250        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.051     5.327 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/i_/O
                         net (fo=58, routed)          1.727     7.054    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/clear
    SLICE_X78Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__8/R
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.914     2.300    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X78Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__8/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__9/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.424ns  (logic 0.158ns (3.571%)  route 4.266ns (96.429%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.330ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.300ns
    Source Clock Delay      (SCD):    2.630ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.104ns (routing 0.888ns, distribution 1.216ns)
  Clock Net Delay (Destination): 1.914ns (routing 0.801ns, distribution 1.113ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.104     2.630    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.709 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.364     4.073    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.101 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        1.175     5.276    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aresetn
    SLICE_X66Y250        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.051     5.327 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/i_/O
                         net (fo=58, routed)          1.727     7.054    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/clear
    SLICE_X78Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__9/R
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.914     2.300    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X78Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__9/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__3/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.382ns  (logic 0.158ns (3.606%)  route 4.224ns (96.394%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.333ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.297ns
    Source Clock Delay      (SCD):    2.630ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.104ns (routing 0.888ns, distribution 1.216ns)
  Clock Net Delay (Destination): 1.911ns (routing 0.801ns, distribution 1.110ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.104     2.630    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.709 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.364     4.073    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.101 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        1.175     5.276    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aresetn
    SLICE_X66Y250        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.051     5.327 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/i_/O
                         net (fo=58, routed)          1.685     7.012    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/clear
    SLICE_X78Y272        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__3/R
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.911     2.297    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X78Y272        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__3/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__4/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.382ns  (logic 0.158ns (3.606%)  route 4.224ns (96.394%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.333ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.297ns
    Source Clock Delay      (SCD):    2.630ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.104ns (routing 0.888ns, distribution 1.216ns)
  Clock Net Delay (Destination): 1.911ns (routing 0.801ns, distribution 1.110ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.104     2.630    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.709 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.364     4.073    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.101 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        1.175     5.276    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aresetn
    SLICE_X66Y250        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.051     5.327 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/i_/O
                         net (fo=58, routed)          1.685     7.012    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/clear
    SLICE_X78Y272        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__4/R
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.911     2.297    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X78Y272        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__4/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__5/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.382ns  (logic 0.158ns (3.606%)  route 4.224ns (96.394%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.333ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.297ns
    Source Clock Delay      (SCD):    2.630ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.104ns (routing 0.888ns, distribution 1.216ns)
  Clock Net Delay (Destination): 1.911ns (routing 0.801ns, distribution 1.110ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.104     2.630    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.709 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.364     4.073    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.101 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        1.175     5.276    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/aresetn
    SLICE_X66Y250        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.051     5.327 r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/i_/O
                         net (fo=58, routed)          1.685     7.012    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/clear
    SLICE_X78Y272        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__5/R
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.911     2.297    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X78Y272        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_Nm_r1_reg__5/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[0]/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.355ns  (logic 0.056ns (4.133%)  route 1.299ns (95.867%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.334ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.753ns
    Source Clock Delay      (SCD):    1.419ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.157ns (routing 0.485ns, distribution 0.672ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.544ns, distribution 0.858ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.157     1.419    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.458 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.717     2.175    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.192 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        0.582     2.774    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aresetn
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[0]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.402     1.753    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[13]/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.355ns  (logic 0.056ns (4.133%)  route 1.299ns (95.867%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.334ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.753ns
    Source Clock Delay      (SCD):    1.419ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.157ns (routing 0.485ns, distribution 0.672ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.544ns, distribution 0.858ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.157     1.419    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.458 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.717     2.175    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.192 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        0.582     2.774    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aresetn
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[13]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.402     1.753    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.355ns  (logic 0.056ns (4.133%)  route 1.299ns (95.867%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.334ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.753ns
    Source Clock Delay      (SCD):    1.419ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.157ns (routing 0.485ns, distribution 0.672ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.544ns, distribution 0.858ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.157     1.419    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.458 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.717     2.175    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.192 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        0.582     2.774    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aresetn
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[3]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.402     1.753    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[5]/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.355ns  (logic 0.056ns (4.133%)  route 1.299ns (95.867%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.334ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.753ns
    Source Clock Delay      (SCD):    1.419ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.157ns (routing 0.485ns, distribution 0.672ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.544ns, distribution 0.858ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.157     1.419    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.458 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.717     2.175    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.192 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        0.582     2.774    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aresetn
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[5]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.402     1.753    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[9]/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.355ns  (logic 0.056ns (4.133%)  route 1.299ns (95.867%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.334ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.753ns
    Source Clock Delay      (SCD):    1.419ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.157ns (routing 0.485ns, distribution 0.672ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.544ns, distribution 0.858ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.157     1.419    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.458 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.717     2.175    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.192 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        0.582     2.774    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aresetn
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[9]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.402     1.753    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r2_reg[3]/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.355ns  (logic 0.056ns (4.133%)  route 1.299ns (95.867%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.334ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.753ns
    Source Clock Delay      (SCD):    1.419ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.157ns (routing 0.485ns, distribution 0.672ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.544ns, distribution 0.858ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.157     1.419    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.458 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.717     2.175    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.192 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        0.582     2.774    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aresetn
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r2_reg[3]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.402     1.753    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r2_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r2_reg[5]/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.355ns  (logic 0.056ns (4.133%)  route 1.299ns (95.867%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.334ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.753ns
    Source Clock Delay      (SCD):    1.419ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.157ns (routing 0.485ns, distribution 0.672ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.544ns, distribution 0.858ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.157     1.419    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.458 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.717     2.175    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.192 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        0.582     2.774    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aresetn
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r2_reg[5]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.402     1.753    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r2_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r2_reg[9]/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.355ns  (logic 0.056ns (4.133%)  route 1.299ns (95.867%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.334ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.753ns
    Source Clock Delay      (SCD):    1.419ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.157ns (routing 0.485ns, distribution 0.672ns)
  Clock Net Delay (Destination): 1.402ns (routing 0.544ns, distribution 0.858ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.157     1.419    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.458 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.717     2.175    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.192 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        0.582     2.774    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aresetn
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r2_reg[9]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.402     1.753    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X92Y271        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r2_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r2_reg[31]/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.356ns  (logic 0.056ns (4.130%)  route 1.300ns (95.870%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.335ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.754ns
    Source Clock Delay      (SCD):    1.419ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.157ns (routing 0.485ns, distribution 0.672ns)
  Clock Net Delay (Destination): 1.403ns (routing 0.544ns, distribution 0.859ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.157     1.419    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.458 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.717     2.175    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.192 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        0.583     2.775    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aresetn
    SLICE_X88Y278        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r2_reg[31]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.403     1.754    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X88Y278        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r2_reg[31]/C

Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[10]/R
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.356ns  (logic 0.056ns (4.130%)  route 1.300ns (95.870%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.336ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.755ns
    Source Clock Delay      (SCD):    1.419ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.157ns (routing 0.485ns, distribution 0.672ns)
  Clock Net Delay (Destination): 1.404ns (routing 0.544ns, distribution 0.860ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.157     1.419    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.458 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.717     2.175    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.192 f  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        0.583     2.775    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aresetn
    SLICE_X92Y273        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[10]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.404     1.755    d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/aclk
    SLICE_X92Y273        FDRE                                         r  d_1_i/axis_dyn_readout_v1_1/inst/readout_top_i/down_conversion_fir_i/down_conversion_i/ctrl_i/pinc_r1_reg[10]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC2_CLK
  To Clock:  RFADC2_CLK

Max Delay           177 Endpoints
Min Delay           177 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.956ns  (logic 0.080ns (8.372%)  route 0.876ns (91.628%))
  Logic Levels:           0  
  Clock Path Skew:        -1.451ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.207ns
    Source Clock Delay      (SCD):    3.658ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.947ns (routing 1.474ns, distribution 1.473ns)
  Clock Net Delay (Destination): 1.821ns (routing 0.801ns, distribution 1.020ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.947     3.658    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X50Y222        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y222        FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     3.738 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                         net (fo=3, routed)           0.876     4.614    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X61Y176        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.821     2.207    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X61Y176        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.845ns  (logic 0.080ns (9.467%)  route 0.765ns (90.533%))
  Logic Levels:           0  
  Clock Path Skew:        -1.373ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.269ns
    Source Clock Delay      (SCD):    3.642ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.931ns (routing 1.474ns, distribution 1.457ns)
  Clock Net Delay (Destination): 1.883ns (routing 0.801ns, distribution 1.082ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.931     3.642    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X54Y229        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y229        FDCE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     3.722 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/Q
                         net (fo=2, routed)           0.765     4.487    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/trigger
    SLICE_X72Y227        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.883     2.269    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X72Y227        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.855ns  (logic 0.080ns (9.356%)  route 0.775ns (90.644%))
  Logic Levels:           0  
  Clock Path Skew:        -1.419ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.207ns
    Source Clock Delay      (SCD):    3.626ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.915ns (routing 1.474ns, distribution 1.441ns)
  Clock Net Delay (Destination): 1.821ns (routing 0.801ns, distribution 1.020ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.915     3.626    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X54Y222        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y222        FDCE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     3.706 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                         net (fo=2, routed)           0.775     4.481    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X61Y176        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.821     2.207    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X61Y176        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMF/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[178]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.886ns  (logic 0.295ns (33.296%)  route 0.591ns (66.704%))
  Logic Levels:           0  
  Clock Path Skew:        -1.384ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.265ns
    Source Clock Delay      (SCD):    3.649ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.938ns (routing 1.474ns, distribution 1.464ns)
  Clock Net Delay (Destination): 1.879ns (routing 0.801ns, distribution 1.078ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.938     3.649    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/WCLK
    SLICE_X60Y231        RAMD32                                       r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMF/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y231        RAMD32 (Prop_F5LUT_SLICEM_CLK_O)
                                                      0.295     3.944 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMF/O
                         net (fo=1, routed)           0.591     4.535    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[178]
    SLICE_X62Y242        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[178]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.879     2.265    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X62Y242        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[178]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[181]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.872ns  (logic 0.295ns (33.830%)  route 0.577ns (66.170%))
  Logic Levels:           0  
  Clock Path Skew:        -1.387ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.262ns
    Source Clock Delay      (SCD):    3.649ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.938ns (routing 1.474ns, distribution 1.464ns)
  Clock Net Delay (Destination): 1.876ns (routing 0.801ns, distribution 1.075ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.938     3.649    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/WCLK
    SLICE_X60Y231        RAMD32                                       r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y231        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.295     3.944 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMG_D1/O
                         net (fo=1, routed)           0.577     4.521    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[181]
    SLICE_X67Y236        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[181]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.876     2.262    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X67Y236        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[181]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[175]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.865ns  (logic 0.301ns (34.798%)  route 0.564ns (65.202%))
  Logic Levels:           0  
  Clock Path Skew:        -1.375ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.274ns
    Source Clock Delay      (SCD):    3.649ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.938ns (routing 1.474ns, distribution 1.464ns)
  Clock Net Delay (Destination): 1.888ns (routing 0.801ns, distribution 1.087ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.938     3.649    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/WCLK
    SLICE_X60Y231        RAMD32                                       r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y231        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.301     3.950 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMD_D1/O
                         net (fo=1, routed)           0.564     4.514    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[175]
    SLICE_X63Y243        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[175]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.888     2.274    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X63Y243        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[175]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMG/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[180]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.842ns  (logic 0.281ns (33.373%)  route 0.561ns (66.627%))
  Logic Levels:           0  
  Clock Path Skew:        -1.384ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.265ns
    Source Clock Delay      (SCD):    3.649ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.938ns (routing 1.474ns, distribution 1.464ns)
  Clock Net Delay (Destination): 1.879ns (routing 0.801ns, distribution 1.078ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.938     3.649    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/WCLK
    SLICE_X60Y231        RAMD32                                       r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMG/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y231        RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.281     3.930 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMG/O
                         net (fo=1, routed)           0.561     4.491    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[180]
    SLICE_X62Y242        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[180]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.879     2.265    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X62Y242        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[180]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[176]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.838ns  (logic 0.288ns (34.368%)  route 0.550ns (65.632%))
  Logic Levels:           0  
  Clock Path Skew:        -1.375ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.274ns
    Source Clock Delay      (SCD):    3.649ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.938ns (routing 1.474ns, distribution 1.464ns)
  Clock Net Delay (Destination): 1.888ns (routing 0.801ns, distribution 1.087ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.938     3.649    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/WCLK
    SLICE_X60Y231        RAMD32                                       r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y231        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     3.937 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAME/O
                         net (fo=1, routed)           0.550     4.487    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[176]
    SLICE_X63Y243        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[176]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.888     2.274    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X63Y243        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[176]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[179]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.825ns  (logic 0.304ns (36.848%)  route 0.521ns (63.152%))
  Logic Levels:           0  
  Clock Path Skew:        -1.384ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.265ns
    Source Clock Delay      (SCD):    3.649ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.938ns (routing 1.474ns, distribution 1.464ns)
  Clock Net Delay (Destination): 1.879ns (routing 0.801ns, distribution 1.078ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.938     3.649    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/WCLK
    SLICE_X60Y231        RAMD32                                       r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y231        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.304     3.953 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAMF_D1/O
                         net (fo=1, routed)           0.521     4.474    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[179]
    SLICE_X62Y242        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[179]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.879     2.265    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X62Y242        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[179]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAME_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[177]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.805ns  (logic 0.302ns (37.516%)  route 0.503ns (62.484%))
  Logic Levels:           0  
  Clock Path Skew:        -1.384ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.265ns
    Source Clock Delay      (SCD):    3.649ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.938ns (routing 1.474ns, distribution 1.464ns)
  Clock Net Delay (Destination): 1.879ns (routing 0.801ns, distribution 1.078ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.938     3.649    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/WCLK
    SLICE_X60Y231        RAMD32                                       r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAME_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y231        RAMD32 (Prop_E6LUT_SLICEM_CLK_O)
                                                      0.302     3.951 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_168_181/RAME_D1/O
                         net (fo=1, routed)           0.503     4.454    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[177]
    SLICE_X62Y242        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[177]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.879     2.265    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X62Y242        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[177]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.409ns  (logic 0.039ns (9.543%)  route 0.370ns (90.457%))
  Logic Levels:           0  
  Clock Path Skew:        -0.305ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.663ns
    Source Clock Delay      (SCD):    1.968ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.601ns (routing 0.796ns, distribution 0.805ns)
  Clock Net Delay (Destination): 1.312ns (routing 0.544ns, distribution 0.768ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.601     1.968    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X54Y229        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y229        FDCE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     2.007 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[6]/Q
                         net (fo=2, routed)           0.370     2.376    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/trigger
    SLICE_X72Y227        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.312     1.663    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/s00_axis_aclk
    SLICE_X72Y227        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.416ns  (logic 0.040ns (9.623%)  route 0.376ns (90.377%))
  Logic Levels:           0  
  Clock Path Skew:        -0.338ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.623ns
    Source Clock Delay      (SCD):    1.961ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.594ns (routing 0.796ns, distribution 0.798ns)
  Clock Net Delay (Destination): 1.272ns (routing 0.544ns, distribution 0.728ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.594     1.961    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X54Y222        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y222        FDCE (Prop_BFF2_SLICEM_C_Q)
                                                      0.040     2.001 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[1]/Q
                         net (fo=2, routed)           0.376     2.377    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X61Y176        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.272     1.623    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X61Y176        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.475ns  (logic 0.039ns (8.204%)  route 0.436ns (91.796%))
  Logic Levels:           0  
  Clock Path Skew:        -0.353ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.623ns
    Source Clock Delay      (SCD):    1.976ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.609ns (routing 0.796ns, distribution 0.813ns)
  Clock Net Delay (Destination): 1.272ns (routing 0.544ns, distribution 0.728ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.609     1.976    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X50Y222        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y222        FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.015 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[0]/Q
                         net (fo=3, routed)           0.436     2.451    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/trigger
    SLICE_X61Y176        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.272     1.623    d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/s_axis_aclk
    SLICE_X61Y176        FDRE                                         r  d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/trigger_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.166ns  (logic 0.078ns (47.016%)  route 0.088ns (52.984%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        -0.274ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.647ns
    Source Clock Delay      (SCD):    1.921ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.554ns (routing 0.796ns, distribution 0.758ns)
  Clock Net Delay (Destination): 1.296ns (routing 0.544ns, distribution 0.752ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.554     1.921    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/s_axis_aclk
    SLICE_X61Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X61Y235        FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     1.960 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/wptr_reg[2]/Q
                         net (fo=296, routed)         0.082     2.042    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][3]_0[2]
    SLICE_X62Y234        LUT2 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.039     2.081 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg[0][2]_i_1/O
                         net (fo=1, routed)           0.006     2.087    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/wptr_g[2]
    SLICE_X62Y234        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.296     1.647    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/m_axis_aclk
    SLICE_X62Y234        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/wptr_g_i/data_int_reg_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_196_209/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[203]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.174ns  (logic 0.111ns (63.793%)  route 0.063ns (36.207%))
  Logic Levels:           0  
  Clock Path Skew:        -0.260ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.670ns
    Source Clock Delay      (SCD):    1.930ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.563ns (routing 0.796ns, distribution 0.767ns)
  Clock Net Delay (Destination): 1.319ns (routing 0.544ns, distribution 0.775ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.563     1.930    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_196_209/WCLK
    SLICE_X66Y245        RAMD32                                       r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_196_209/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y245        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.111     2.041 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_196_209/RAMD_D1/O
                         net (fo=1, routed)           0.063     2.104    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[203]
    SLICE_X65Y245        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[203]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.319     1.670    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X65Y245        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[203]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[223]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.178ns  (logic 0.105ns (58.989%)  route 0.073ns (41.011%))
  Logic Levels:           0  
  Clock Path Skew:        -0.254ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.676ns
    Source Clock Delay      (SCD):    1.930ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.563ns (routing 0.796ns, distribution 0.767ns)
  Clock Net Delay (Destination): 1.325ns (routing 0.544ns, distribution 0.781ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.563     1.930    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/WCLK
    SLICE_X66Y242        RAMD32                                       r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y242        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     2.035 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_210_223/RAMG_D1/O
                         net (fo=1, routed)           0.073     2.108    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[223]
    SLICE_X66Y243        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[223]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.325     1.676    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X66Y243        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[223]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_182_195/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[189]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.184ns  (logic 0.111ns (60.326%)  route 0.073ns (39.674%))
  Logic Levels:           0  
  Clock Path Skew:        -0.251ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.679ns
    Source Clock Delay      (SCD):    1.930ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.563ns (routing 0.796ns, distribution 0.767ns)
  Clock Net Delay (Destination): 1.328ns (routing 0.544ns, distribution 0.784ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.563     1.930    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_182_195/WCLK
    SLICE_X66Y240        RAMD32                                       r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_182_195/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y240        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.111     2.041 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_182_195/RAMD_D1/O
                         net (fo=1, routed)           0.073     2.114    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[189]
    SLICE_X67Y240        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[189]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.328     1.679    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X67Y240        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[189]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_224_237/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[232]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.184ns  (logic 0.108ns (58.696%)  route 0.076ns (41.304%))
  Logic Levels:           0  
  Clock Path Skew:        -0.256ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.675ns
    Source Clock Delay      (SCD):    1.931ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.564ns (routing 0.796ns, distribution 0.768ns)
  Clock Net Delay (Destination): 1.324ns (routing 0.544ns, distribution 0.780ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.564     1.931    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_224_237/WCLK
    SLICE_X63Y242        RAMD32                                       r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_224_237/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y242        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.108     2.039 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_224_237/RAME/O
                         net (fo=1, routed)           0.076     2.115    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[232]
    SLICE_X63Y243        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[232]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.324     1.675    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X63Y243        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[232]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_224_237/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[225]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.187ns  (logic 0.111ns (59.358%)  route 0.076ns (40.642%))
  Logic Levels:           0  
  Clock Path Skew:        -0.255ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.676ns
    Source Clock Delay      (SCD):    1.931ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.564ns (routing 0.796ns, distribution 0.768ns)
  Clock Net Delay (Destination): 1.325ns (routing 0.544ns, distribution 0.781ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.564     1.931    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_224_237/WCLK
    SLICE_X63Y242        RAMD32                                       r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_224_237/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y242        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.111     2.042 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_224_237/RAMA_D1/O
                         net (fo=1, routed)           0.076     2.118    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[225]
    SLICE_X63Y243        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[225]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.325     1.676    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X63Y243        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[225]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_196_209/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[200]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.192ns  (logic 0.112ns (58.333%)  route 0.080ns (41.667%))
  Logic Levels:           0  
  Clock Path Skew:        -0.260ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.670ns
    Source Clock Delay      (SCD):    1.930ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.563ns (routing 0.796ns, distribution 0.767ns)
  Clock Net Delay (Destination): 1.319ns (routing 0.544ns, distribution 0.775ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.563     1.930    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_196_209/WCLK
    SLICE_X66Y245        RAMD32                                       r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_196_209/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y245        RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.112     2.042 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/RAM_reg_0_15_196_209/RAMC/O
                         net (fo=1, routed)           0.080     2.122    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob0[200]
    SLICE_X65Y245        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[200]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.319     1.670    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/m_axis_aclk
    SLICE_X65Y245        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/mem_i/dob_reg[200]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  RFADC2_CLK

Max Delay           154 Endpoints
Min Delay           154 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc2_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.435ns  (logic 0.078ns (17.931%)  route 0.357ns (82.069%))
  Logic Levels:           0  
  Clock Path Skew:        -0.123ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.516ns
    Source Clock Delay      (SCD):    2.638ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.412ns (routing 0.670ns, distribution 1.742ns)
  Clock Net Delay (Destination): 2.130ns (routing 0.801ns, distribution 1.329ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.412     2.638    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X112Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc2_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X112Y198       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.716 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/adc2_done_i_reg/Q
                         net (fo=1, routed)           0.357     3.073    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/src_in
    SLICE_X115Y195       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.130     2.516    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/dest_clk
    SLICE_X115Y195       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc2_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.391ns  (logic 0.078ns (19.924%)  route 0.313ns (80.076%))
  Logic Levels:           0  
  Clock Path Skew:        -0.176ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.359ns
    Source Clock Delay      (SCD):    2.535ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.309ns (routing 0.670ns, distribution 1.639ns)
  Clock Net Delay (Destination): 1.973ns (routing 0.801ns, distribution 1.172ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.309     2.535    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X86Y128        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y128        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     2.613 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.313     2.927    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X88Y131        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.973     2.359    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X88Y131        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.407ns  (logic 0.079ns (19.417%)  route 0.328ns (80.583%))
  Logic Levels:           0  
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.297ns
    Source Clock Delay      (SCD):    2.324ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.098ns (routing 0.670ns, distribution 1.428ns)
  Clock Net Delay (Destination): 1.911ns (routing 0.801ns, distribution 1.110ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.098     2.324    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X49Y76         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y76         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.403 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.328     2.731    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X52Y78         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.911     2.297    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X52Y78         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/slv_reg0_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.877ns  (logic 0.080ns (4.262%)  route 1.797ns (95.738%))
  Logic Levels:           0  
  Clock Path Skew:        0.054ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.365ns
    Source Clock Delay      (SCD):    2.311ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.085ns (routing 0.670ns, distribution 1.415ns)
  Clock Net Delay (Destination): 1.979ns (routing 0.801ns, distribution 1.178ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.085     2.311    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/s00_axi_aclk
    SLICE_X48Y95         FDRE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/slv_reg0_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y95         FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.080     2.391 r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/slv_reg0_reg[0]/Q
                         net (fo=2, routed)           1.797     4.188    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]_0[0]
    SLICE_X92Y121        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.979     2.365    d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/s00_axis_aclk
    SLICE_X92Y121        FDCE                                         r  d_1_i/mr_buffer_et_0/U0/mr_buffer_v1_0_S00_AXI_inst/mr_buffer_i/DW_CAPTURE_REG_resync_i/data_int_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[18]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.312ns  (logic 0.078ns (5.945%)  route 1.234ns (94.055%))
  Logic Levels:           0  
  Clock Path Skew:        -0.168ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    2.510ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.284ns (routing 0.670ns, distribution 1.614ns)
  Clock Net Delay (Destination): 1.956ns (routing 0.801ns, distribution 1.155ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.284     2.510    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X82Y121        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[18]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y121        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.588 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[18]/Q
                         net (fo=2, routed)           1.234     3.822    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[31]_0[18]
    SLICE_X82Y121        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[18]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.956     2.342    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X82Y121        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[18]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.155ns  (logic 0.078ns (6.753%)  route 1.077ns (93.247%))
  Logic Levels:           0  
  Clock Path Skew:        -0.168ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    2.510ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.284ns (routing 0.670ns, distribution 1.614ns)
  Clock Net Delay (Destination): 1.956ns (routing 0.801ns, distribution 1.155ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.284     2.510    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X82Y121        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y121        FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     2.588 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[20]/Q
                         net (fo=2, routed)           1.077     3.665    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[31]_0[20]
    SLICE_X82Y121        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.956     2.342    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X82Y121        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[20]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[24]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[24]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.133ns  (logic 0.079ns (6.972%)  route 1.054ns (93.028%))
  Logic Levels:           0  
  Clock Path Skew:        -0.159ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.335ns
    Source Clock Delay      (SCD):    2.494ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.268ns (routing 0.670ns, distribution 1.598ns)
  Clock Net Delay (Destination): 1.949ns (routing 0.801ns, distribution 1.148ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.268     2.494    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X81Y123        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[24]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y123        FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.573 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[24]/Q
                         net (fo=2, routed)           1.054     3.627    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[31]_0[24]
    SLICE_X81Y123        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[24]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.949     2.335    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X81Y123        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[24]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[26]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.084ns  (logic 0.079ns (7.288%)  route 1.005ns (92.712%))
  Logic Levels:           0  
  Clock Path Skew:        -0.159ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.335ns
    Source Clock Delay      (SCD):    2.494ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.268ns (routing 0.670ns, distribution 1.598ns)
  Clock Net Delay (Destination): 1.949ns (routing 0.801ns, distribution 1.148ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.268     2.494    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X81Y123        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y123        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     2.573 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[26]/Q
                         net (fo=2, routed)           1.005     3.578    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[31]_0[26]
    SLICE_X81Y123        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[26]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.949     2.335    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X81Y123        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[26]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.871ns  (logic 0.078ns (8.951%)  route 0.793ns (91.049%))
  Logic Levels:           0  
  Clock Path Skew:        -0.168ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.342ns
    Source Clock Delay      (SCD):    2.510ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.284ns (routing 0.670ns, distribution 1.614ns)
  Clock Net Delay (Destination): 1.956ns (routing 0.801ns, distribution 1.155ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.284     2.510    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X82Y121        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y121        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.588 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[22]/Q
                         net (fo=2, routed)           0.793     3.381    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[31]_0[22]
    SLICE_X82Y121        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.956     2.342    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X82Y121        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[22]/C

Slack:                    inf
  Source:                 d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.783ns  (logic 0.079ns (10.087%)  route 0.704ns (89.913%))
  Logic Levels:           0  
  Clock Path Skew:        -0.235ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.259ns
    Source Clock Delay      (SCD):    2.494ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.268ns (routing 0.670ns, distribution 1.598ns)
  Clock Net Delay (Destination): 1.873ns (routing 0.801ns, distribution 1.072ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.268     2.494    d_1_i/axis_avg_buffer_1/inst/axi_slv_i/s_axi_aclk
    SLICE_X81Y123        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y123        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     2.573 r  d_1_i/axis_avg_buffer_1/inst/axi_slv_i/slv_reg2_reg[28]/Q
                         net (fo=2, routed)           0.704     3.277    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[31]_0[28]
    SLICE_X79Y123        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.873     2.259    d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/s_axis_aclk
    SLICE_X79Y123        FDRE                                         r  d_1_i/axis_avg_buffer_1/inst/avg_buffer_i/avg_top_i/avg_i/len_r_reg[28]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.039ns (37.500%)  route 0.065ns (62.500%))
  Logic Levels:           0  
  Clock Path Skew:        0.435ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.693ns
    Source Clock Delay      (SCD):    1.258ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.138ns (routing 0.363ns, distribution 0.775ns)
  Clock Net Delay (Destination): 1.342ns (routing 0.544ns, distribution 0.798ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.138     1.258    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X52Y79         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y79         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.297 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/Q
                         net (fo=1, routed)           0.065     1.362    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[0]
    SLICE_X52Y78         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.342     1.693    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X52Y78         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.040ns (31.008%)  route 0.089ns (68.992%))
  Logic Levels:           0  
  Clock Path Skew:        0.427ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.685ns
    Source Clock Delay      (SCD):    1.258ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.138ns (routing 0.363ns, distribution 0.775ns)
  Clock Net Delay (Destination): 1.334ns (routing 0.544ns, distribution 0.790ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.138     1.258    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X52Y79         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y79         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.298 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[4]/Q
                         net (fo=1, routed)           0.089     1.387    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[4]
    SLICE_X52Y79         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.334     1.685    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X52Y79         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.168ns  (logic 0.040ns (23.810%)  route 0.128ns (76.190%))
  Logic Levels:           0  
  Clock Path Skew:        0.427ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.685ns
    Source Clock Delay      (SCD):    1.258ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.138ns (routing 0.363ns, distribution 0.775ns)
  Clock Net Delay (Destination): 1.334ns (routing 0.544ns, distribution 0.790ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.138     1.258    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X52Y79         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y79         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.040     1.298 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/Q
                         net (fo=1, routed)           0.128     1.426    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[3]
    SLICE_X52Y79         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.334     1.685    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X52Y79         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.171ns  (logic 0.039ns (22.807%)  route 0.132ns (77.193%))
  Logic Levels:           0  
  Clock Path Skew:        0.419ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.685ns
    Source Clock Delay      (SCD):    1.266ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.146ns (routing 0.363ns, distribution 0.783ns)
  Clock Net Delay (Destination): 1.334ns (routing 0.544ns, distribution 0.790ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.146     1.266    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X53Y78         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y78         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.305 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/Q
                         net (fo=1, routed)           0.132     1.437    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[1]
    SLICE_X52Y79         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.334     1.685    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X52Y79         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.180ns  (logic 0.039ns (21.665%)  route 0.141ns (78.335%))
  Logic Levels:           0  
  Clock Path Skew:        0.422ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.689ns
    Source Clock Delay      (SCD):    1.268ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.148ns (routing 0.363ns, distribution 0.785ns)
  Clock Net Delay (Destination): 1.338ns (routing 0.544ns, distribution 0.794ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.148     1.268    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X49Y76         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y76         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.307 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.141     1.448    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X52Y78         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.338     1.689    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X52Y78         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.204ns  (logic 0.040ns (19.608%)  route 0.164ns (80.392%))
  Logic Levels:           0  
  Clock Path Skew:        0.427ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.685ns
    Source Clock Delay      (SCD):    1.258ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.138ns (routing 0.363ns, distribution 0.775ns)
  Clock Net Delay (Destination): 1.334ns (routing 0.544ns, distribution 0.790ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.138     1.258    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X52Y79         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y79         FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.298 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[2]/Q
                         net (fo=1, routed)           0.164     1.462    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[2]
    SLICE_X52Y79         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.334     1.685    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X52Y79         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.039ns (30.709%)  route 0.088ns (69.291%))
  Logic Levels:           0  
  Clock Path Skew:        0.339ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.722ns
    Source Clock Delay      (SCD):    1.383ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.263ns (routing 0.363ns, distribution 0.900ns)
  Clock Net Delay (Destination): 1.371ns (routing 0.544ns, distribution 0.827ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.263     1.383    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X91Y132        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y132        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.422 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[3]/Q
                         net (fo=1, routed)           0.088     1.510    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[3]
    SLICE_X91Y132        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.371     1.722    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X91Y132        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.157ns  (logic 0.039ns (24.841%)  route 0.118ns (75.159%))
  Logic Levels:           0  
  Clock Path Skew:        0.339ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.722ns
    Source Clock Delay      (SCD):    1.383ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.263ns (routing 0.363ns, distribution 0.900ns)
  Clock Net Delay (Destination): 1.371ns (routing 0.544ns, distribution 0.827ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.263     1.383    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X91Y132        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y132        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.422 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[0]/Q
                         net (fo=1, routed)           0.118     1.540    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[0]
    SLICE_X91Y132        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.371     1.722    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X91Y132        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.176ns  (logic 0.039ns (22.211%)  route 0.137ns (77.789%))
  Logic Levels:           0  
  Clock Path Skew:        0.336ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.721ns
    Source Clock Delay      (SCD):    1.386ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.266ns (routing 0.363ns, distribution 0.903ns)
  Clock Net Delay (Destination): 1.370ns (routing 0.544ns, distribution 0.826ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.266     1.386    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X86Y128        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X86Y128        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.425 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_sendd_ff_reg/Q
                         net (fo=2, routed)           0.137     1.561    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/src_in
    SLICE_X88Y131        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.370     1.721    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/dest_clk
    SLICE_X88Y131        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_src2dest_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.188ns  (logic 0.039ns (20.745%)  route 0.149ns (79.255%))
  Logic Levels:           0  
  Clock Path Skew:        0.339ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.722ns
    Source Clock Delay      (SCD):    1.383ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.263ns (routing 0.363ns, distribution 0.900ns)
  Clock Net Delay (Destination): 1.371ns (routing 0.544ns, distribution 0.827ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.263     1.383    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_clk
    SLICE_X91Y132        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y132        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.422 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff_reg[1]/Q
                         net (fo=1, routed)           0.149     1.571    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/src_hsdata_ff[1]
    SLICE_X91Y132        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.371     1.722    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X91Y132        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_hsdata_ff_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  RFADC2_CLK

Max Delay             7 Endpoints
Min Delay             7 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.334ns  (logic 0.169ns (12.672%)  route 1.165ns (87.328%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.182ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.427ns
    Source Clock Delay      (SCD):    2.609ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.492ns (routing 0.415ns, distribution 1.077ns)
  Clock Net Delay (Destination): 2.041ns (routing 0.801ns, distribution 1.240ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.492     2.609    d_1_i/rst_ddr4/U0/slowest_sync_clk
    SLICE_X101Y53        FDRE                                         r  d_1_i/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y53        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.688 f  d_1_i/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=445, routed)         0.925     3.612    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X102Y129       LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.090     3.702 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.240     3.942    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X102Y129       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.041     2.427    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X102Y129       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.298ns  (logic 0.079ns (26.466%)  route 0.219ns (73.534%))
  Logic Levels:           0  
  Clock Path Skew:        -0.209ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.422ns
    Source Clock Delay      (SCD):    2.631ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.514ns (routing 0.415ns, distribution 1.099ns)
  Clock Net Delay (Destination): 2.036ns (routing 0.801ns, distribution 1.235ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.514     2.631    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X101Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y128       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.710 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=277, routed)         0.219     2.929    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X100Y127       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.036     2.422    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X100Y127       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.471ns  (logic 0.081ns (17.197%)  route 0.390ns (82.803%))
  Logic Levels:           0  
  Clock Path Skew:        -0.204ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.427ns
    Source Clock Delay      (SCD):    2.631ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.514ns (routing 0.415ns, distribution 1.099ns)
  Clock Net Delay (Destination): 2.041ns (routing 0.801ns, distribution 1.240ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.514     2.631    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X101Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y128       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.712 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.390     3.102    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X102Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.041     2.427    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X102Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.400ns  (logic 0.076ns (19.000%)  route 0.324ns (81.000%))
  Logic Levels:           0  
  Clock Path Skew:        -0.212ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.427ns
    Source Clock Delay      (SCD):    2.639ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.522ns (routing 0.415ns, distribution 1.107ns)
  Clock Net Delay (Destination): 2.041ns (routing 0.801ns, distribution 1.240ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.522     2.639    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X103Y129       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y129       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     2.715 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.324     3.039    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X103Y129       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.041     2.427    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X103Y129       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.281ns  (logic 0.079ns (28.114%)  route 0.202ns (71.886%))
  Logic Levels:           0  
  Clock Path Skew:        -0.206ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    2.629ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.512ns (routing 0.415ns, distribution 1.097ns)
  Clock Net Delay (Destination): 2.037ns (routing 0.801ns, distribution 1.236ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.512     2.629    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X100Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y128       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.708 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.202     2.910    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X100Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.037     2.423    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X100Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.277ns  (logic 0.081ns (29.242%)  route 0.196ns (70.758%))
  Logic Levels:           0  
  Clock Path Skew:        -0.206ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    2.629ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.512ns (routing 0.415ns, distribution 1.097ns)
  Clock Net Delay (Destination): 2.037ns (routing 0.801ns, distribution 1.236ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.512     2.629    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X100Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y128       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.081     2.710 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.196     2.906    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X100Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.037     2.423    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X100Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.227ns  (logic 0.079ns (34.802%)  route 0.148ns (65.198%))
  Logic Levels:           0  
  Clock Path Skew:        -0.204ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.427ns
    Source Clock Delay      (SCD):    2.631ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.514ns (routing 0.415ns, distribution 1.099ns)
  Clock Net Delay (Destination): 2.041ns (routing 0.801ns, distribution 1.240ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.514     2.631    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X101Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y128       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.710 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.148     2.858    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X102Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.122     0.122 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.150     0.272    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.386 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.041     2.427    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X102Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.093ns  (logic 0.039ns (41.935%)  route 0.054ns (58.064%))
  Logic Levels:           0  
  Clock Path Skew:        0.003ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.768ns
    Source Clock Delay      (SCD):    1.765ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.839ns (routing 0.230ns, distribution 0.609ns)
  Clock Net Delay (Destination): 1.417ns (routing 0.544ns, distribution 0.873ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.839     1.765    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X101Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y128       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.804 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.054     1.858    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X102Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.417     1.768    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X102Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.041ns (34.454%)  route 0.078ns (65.546%))
  Logic Levels:           0  
  Clock Path Skew:        0.002ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.766ns
    Source Clock Delay      (SCD):    1.764ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.838ns (routing 0.230ns, distribution 0.608ns)
  Clock Net Delay (Destination): 1.415ns (routing 0.544ns, distribution 0.871ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.838     1.764    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X100Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y128       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.805 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.078     1.883    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X100Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.415     1.766    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X100Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.039ns (32.231%)  route 0.082ns (67.769%))
  Logic Levels:           0  
  Clock Path Skew:        0.002ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.766ns
    Source Clock Delay      (SCD):    1.764ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.838ns (routing 0.230ns, distribution 0.608ns)
  Clock Net Delay (Destination): 1.415ns (routing 0.544ns, distribution 0.871ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.838     1.764    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X100Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y128       FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.803 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.082     1.885    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X100Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.415     1.766    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X100Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.327%)  route 0.090ns (69.673%))
  Logic Levels:           0  
  Clock Path Skew:        -0.003ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.762ns
    Source Clock Delay      (SCD):    1.765ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.839ns (routing 0.230ns, distribution 0.609ns)
  Clock Net Delay (Destination): 1.411ns (routing 0.544ns, distribution 0.867ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.839     1.765    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X101Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y128       FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.804 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=277, routed)         0.090     1.894    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X100Y127       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.411     1.762    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X100Y127       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.158ns  (logic 0.038ns (24.051%)  route 0.120ns (75.949%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.769ns
    Source Clock Delay      (SCD):    1.769ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.843ns (routing 0.230ns, distribution 0.613ns)
  Clock Net Delay (Destination): 1.418ns (routing 0.544ns, distribution 0.874ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.843     1.769    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X103Y129       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y129       FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.807 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.120     1.927    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X103Y129       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.418     1.769    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X103Y129       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.198ns  (logic 0.041ns (20.707%)  route 0.157ns (79.293%))
  Logic Levels:           0  
  Clock Path Skew:        0.003ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.768ns
    Source Clock Delay      (SCD):    1.765ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.839ns (routing 0.230ns, distribution 0.609ns)
  Clock Net Delay (Destination): 1.417ns (routing 0.544ns, distribution 0.873ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.839     1.765    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X101Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y128       FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.806 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.157     1.963    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X102Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.417     1.768    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X102Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.614ns  (logic 0.074ns (12.051%)  route 0.540ns (87.949%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        0.010ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.768ns
    Source Clock Delay      (SCD):    1.758ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.832ns (routing 0.230ns, distribution 0.602ns)
  Clock Net Delay (Destination): 1.417ns (routing 0.544ns, distribution 0.873ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.832     1.758    d_1_i/rst_ddr4/U0/slowest_sync_clk
    SLICE_X101Y53        FDRE                                         r  d_1_i/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X101Y53        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.797 f  d_1_i/rst_ddr4/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=445, routed)         0.461     2.259    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/m_axis_aresetn
    SLICE_X102Y129       LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.035     2.294 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.079     2.373    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X102Y129       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.100     0.100 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.169     0.269    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.351 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.417     1.768    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X102Y129       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  RFDAC2_CLK

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.971ns  (logic 0.101ns (5.123%)  route 1.870ns (94.877%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.595ns (routing 1.336ns, distribution 1.259ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=3, routed)           1.465     1.465    d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X60Y232        LUT1 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.101     1.566 r  d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.405     1.971    d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X60Y240        FDRE                                         r  d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.595     3.139    d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X60Y240        FDRE                                         r  d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                            (internal pin)
  Destination:            d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.920ns  (logic 0.041ns (4.454%)  route 0.879ns (95.546%))
  Logic Levels:           1  (LUT1=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.775ns (routing 0.892ns, distribution 0.883ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PS8_X0Y0             PS8                          0.000     0.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/EMIOGPIOO[95]
                         net (fo=3, routed)           0.700     0.700    d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/ext_reset_in
    SLICE_X60Y232        LUT1 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.041     0.741 r  d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.179     0.920    d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/exr_d1
    SLICE_X60Y240        FDRE                                         r  d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.775     2.250    d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/slowest_sync_clk
    SLICE_X60Y240        FDRE                                         r  d_1_i/rst_dac2/U0/EXT_LPF/ACTIVE_LOW_EXT.ACT_LO_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC2_CLK
  To Clock:  RFDAC2_CLK

Max Delay             4 Endpoints
Min Delay             4 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.722ns  (logic 0.215ns (29.774%)  route 0.507ns (70.226%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.461ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.146ns
    Source Clock Delay      (SCD):    2.685ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.159ns (routing 0.888ns, distribution 1.271ns)
  Clock Net Delay (Destination): 2.602ns (routing 1.336ns, distribution 1.266ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.159     2.685    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y235        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     2.765 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/Q
                         net (fo=258, routed)         0.200     2.965    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[2]
    SLICE_X60Y235        LUT2 (Prop_D5LUT_SLICEM_I1_O)
                                                      0.135     3.100 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][1]_i_1__0/O
                         net (fo=1, routed)           0.307     3.407    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[1]
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.602     3.146    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.637ns  (logic 0.176ns (27.642%)  route 0.461ns (72.358%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.461ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.146ns
    Source Clock Delay      (SCD):    2.685ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.159ns (routing 0.888ns, distribution 1.271ns)
  Clock Net Delay (Destination): 2.602ns (routing 1.336ns, distribution 1.266ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.159     2.685    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y235        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.762 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/Q
                         net (fo=258, routed)         0.169     2.931    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[1]
    SLICE_X60Y235        LUT2 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.099     3.030 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][0]_i_1__0/O
                         net (fo=2, routed)           0.291     3.322    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/D[0]
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.602     3.146    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.404ns  (logic 0.078ns (19.319%)  route 0.326ns (80.681%))
  Logic Levels:           0  
  Clock Path Skew:        0.461ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.146ns
    Source Clock Delay      (SCD):    2.685ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.159ns (routing 0.888ns, distribution 1.271ns)
  Clock Net Delay (Destination): 2.602ns (routing 1.336ns, distribution 1.266ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.159     2.685    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y235        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.763 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/Q
                         net (fo=259, routed)         0.326     3.089    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[3]
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.602     3.146    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.348ns  (logic 0.213ns (61.249%)  route 0.135ns (38.751%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.468ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.153ns
    Source Clock Delay      (SCD):    2.685ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.159ns (routing 0.888ns, distribution 1.271ns)
  Clock Net Delay (Destination): 2.609ns (routing 1.336ns, distribution 1.273ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.159     2.685    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y235        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     2.765 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[2]/Q
                         net (fo=258, routed)         0.120     2.885    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[2]
    SLICE_X59Y235        LUT2 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.133     3.018 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][2]_i_1__0/O
                         net (fo=1, routed)           0.015     3.033    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[2]
    SLICE_X59Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.609     3.153    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X59Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.140ns  (logic 0.071ns (50.799%)  route 0.069ns (49.201%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.810ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.262ns
    Source Clock Delay      (SCD):    1.452ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.190ns (routing 0.485ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.787ns (routing 0.892ns, distribution 0.895ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.190     1.452    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y235        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     1.490 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/Q
                         net (fo=259, routed)         0.063     1.553    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[3]
    SLICE_X59Y235        LUT2 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.033     1.586 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][2]_i_1__0/O
                         net (fo=1, routed)           0.006     1.592    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[2]
    SLICE_X59Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.787     2.262    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X59Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.176ns  (logic 0.038ns (21.541%)  route 0.138ns (78.459%))
  Logic Levels:           0  
  Clock Path Skew:        0.807ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.259ns
    Source Clock Delay      (SCD):    1.452ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.190ns (routing 0.485ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.784ns (routing 0.892ns, distribution 0.892ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.190     1.452    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y235        FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     1.490 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[3]/Q
                         net (fo=259, routed)         0.138     1.628    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[3]
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.784     2.259    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.290ns  (logic 0.074ns (25.510%)  route 0.216ns (74.490%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.843ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.259ns
    Source Clock Delay      (SCD):    1.416ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.154ns (routing 0.485ns, distribution 0.669ns)
  Clock Net Delay (Destination): 1.784ns (routing 0.892ns, distribution 0.892ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.154     1.416    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X62Y234        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X62Y234        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.455 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[0]/Q
                         net (fo=258, routed)         0.116     1.571    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[0]
    SLICE_X60Y235        LUT2 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.035     1.606 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][0]_i_1__0/O
                         net (fo=2, routed)           0.100     1.706    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/D[0]
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.784     2.259    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.292ns  (logic 0.080ns (27.400%)  route 0.212ns (72.600%))
  Logic Levels:           1  (LUT2=1)
  Clock Path Skew:        0.807ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.259ns
    Source Clock Delay      (SCD):    1.452ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.190ns (routing 0.485ns, distribution 0.705ns)
  Clock Net Delay (Destination): 1.784ns (routing 0.892ns, distribution 0.892ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.190     1.452    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/m_axis_aclk
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X60Y235        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.490 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_reg[1]/Q
                         net (fo=258, routed)         0.086     1.576    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/Q[1]
    SLICE_X60Y235        LUT2 (Prop_D5LUT_SLICEM_I0_O)
                                                      0.042     1.618 r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg[0][1]_i_1__0/O
                         net (fo=1, routed)           0.126     1.744    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/rptr_g[1]
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.784     2.259    d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/s_axis_aclk
    SLICE_X60Y235        FDRE                                         r  d_1_i/axis_cdcsync_v1_1/inst/cdcsync_i/fifo_i/fifo_i/rptr_g_i/data_int_reg_reg[0][1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC2_CLK
  To Clock:  RFDAC2_CLK

Max Delay         28926 Endpoints
Min Delay         28926 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__2/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.450ns  (logic 0.192ns (5.564%)  route 3.258ns (94.436%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.417ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.108ns
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.814ns (routing 1.474ns, distribution 1.340ns)
  Clock Net Delay (Destination): 2.564ns (routing 1.336ns, distribution 1.228ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.814     3.525    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.601 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.068     4.669    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.697 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       1.425     6.122    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X69Y168        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.088     6.210 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1/O
                         net (fo=56, routed)          0.765     6.976    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1_n_0
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__2/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.564     3.108    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__2/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__3/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.450ns  (logic 0.192ns (5.564%)  route 3.258ns (94.436%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.417ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.108ns
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.814ns (routing 1.474ns, distribution 1.340ns)
  Clock Net Delay (Destination): 2.564ns (routing 1.336ns, distribution 1.228ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.814     3.525    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.601 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.068     4.669    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.697 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       1.425     6.122    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X69Y168        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.088     6.210 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1/O
                         net (fo=56, routed)          0.765     6.976    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1_n_0
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__3/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.564     3.108    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__3/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__4/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.450ns  (logic 0.192ns (5.564%)  route 3.258ns (94.436%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.417ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.108ns
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.814ns (routing 1.474ns, distribution 1.340ns)
  Clock Net Delay (Destination): 2.564ns (routing 1.336ns, distribution 1.228ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.814     3.525    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.601 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.068     4.669    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.697 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       1.425     6.122    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X69Y168        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.088     6.210 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1/O
                         net (fo=56, routed)          0.765     6.976    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1_n_0
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__4/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.564     3.108    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__4/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__5/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.450ns  (logic 0.192ns (5.564%)  route 3.258ns (94.436%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.417ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.108ns
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.814ns (routing 1.474ns, distribution 1.340ns)
  Clock Net Delay (Destination): 2.564ns (routing 1.336ns, distribution 1.228ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.814     3.525    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.601 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.068     4.669    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.697 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       1.425     6.122    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X69Y168        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.088     6.210 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1/O
                         net (fo=56, routed)          0.765     6.976    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1_n_0
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__5/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.564     3.108    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__5/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/cnt_n_reg__13/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.447ns  (logic 0.192ns (5.569%)  route 3.255ns (94.431%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.418ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.107ns
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.814ns (routing 1.474ns, distribution 1.340ns)
  Clock Net Delay (Destination): 2.563ns (routing 1.336ns, distribution 1.227ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.814     3.525    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.601 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.068     4.669    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.697 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       1.425     6.122    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X69Y168        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.088     6.210 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1/O
                         net (fo=56, routed)          0.762     6.973    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1_n_0
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/cnt_n_reg__13/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.563     3.107    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/cnt_n_reg__13/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/cnt_n_reg__14/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.447ns  (logic 0.192ns (5.569%)  route 3.255ns (94.431%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.418ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.107ns
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.814ns (routing 1.474ns, distribution 1.340ns)
  Clock Net Delay (Destination): 2.563ns (routing 1.336ns, distribution 1.227ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.814     3.525    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.601 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.068     4.669    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.697 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       1.425     6.122    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X69Y168        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.088     6.210 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1/O
                         net (fo=56, routed)          0.762     6.973    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1_n_0
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/cnt_n_reg__14/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.563     3.107    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/cnt_n_reg__14/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__0/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.447ns  (logic 0.192ns (5.569%)  route 3.255ns (94.431%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.418ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.107ns
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.814ns (routing 1.474ns, distribution 1.340ns)
  Clock Net Delay (Destination): 2.563ns (routing 1.336ns, distribution 1.227ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.814     3.525    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.601 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.068     4.669    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.697 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       1.425     6.122    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X69Y168        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.088     6.210 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1/O
                         net (fo=56, routed)          0.762     6.973    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1_n_0
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__0/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.563     3.107    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__0/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__1/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.447ns  (logic 0.192ns (5.569%)  route 3.255ns (94.431%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.418ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.107ns
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.814ns (routing 1.474ns, distribution 1.340ns)
  Clock Net Delay (Destination): 2.563ns (routing 1.336ns, distribution 1.227ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.814     3.525    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.601 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.068     4.669    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.697 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       1.425     6.122    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X69Y168        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.088     6.210 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1/O
                         net (fo=56, routed)          0.762     6.973    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1_n_0
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__1/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.563     3.107    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X70Y145        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1_reg__1/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/cnt_n_reg__10/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.409ns  (logic 0.192ns (5.633%)  route 3.217ns (94.368%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.418ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.107ns
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.814ns (routing 1.474ns, distribution 1.340ns)
  Clock Net Delay (Destination): 2.563ns (routing 1.336ns, distribution 1.227ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.814     3.525    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.601 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.068     4.669    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.697 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       1.425     6.122    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X69Y168        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.088     6.210 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1/O
                         net (fo=56, routed)          0.724     6.934    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1_n_0
    SLICE_X70Y146        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/cnt_n_reg__10/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.563     3.107    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X70Y146        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/cnt_n_reg__10/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/cnt_n_reg__11/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.409ns  (logic 0.192ns (5.633%)  route 3.217ns (94.368%))
  Logic Levels:           2  (BUFGCE=1 LUT3=1)
  Clock Path Skew:        -0.418ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.107ns
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.814ns (routing 1.474ns, distribution 1.340ns)
  Clock Net Delay (Destination): 2.563ns (routing 1.336ns, distribution 1.227ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.814     3.525    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.601 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.068     4.669    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.697 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       1.425     6.122    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aresetn
    SLICE_X69Y168        LUT3 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.088     6.210 r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1/O
                         net (fo=56, routed)          0.724     6.934    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/pinc_Nm_r1__0_i_1_n_0
    SLICE_X70Y146        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/cnt_n_reg__11/R
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.563     3.107    d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/aclk
    SLICE_X70Y146        FDRE                                         r  d_1_i/axis_signal_gen_v6_0/inst/signal_gen_top_i/signal_gen_i/ctrl_i/cnt_n_reg__11/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1113]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.189ns  (logic 0.055ns (4.626%)  route 1.134ns (95.374%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.362ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.264ns
    Source Clock Delay      (SCD):    1.903ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.536ns (routing 0.796ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.789ns (routing 0.892ns, distribution 0.897ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.536     1.903    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.941 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.569     2.510    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.527 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       0.565     3.092    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X81Y272        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1113]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.789     2.264    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X81Y272        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1113]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1124]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.189ns  (logic 0.055ns (4.626%)  route 1.134ns (95.374%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.362ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.265ns
    Source Clock Delay      (SCD):    1.903ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.536ns (routing 0.796ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.790ns (routing 0.892ns, distribution 0.898ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.536     1.903    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.941 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.569     2.510    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.527 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       0.565     3.092    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X81Y273        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1124]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.790     2.265    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X81Y273        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1124]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[322]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.189ns  (logic 0.055ns (4.626%)  route 1.134ns (95.374%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.362ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.264ns
    Source Clock Delay      (SCD):    1.903ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.536ns (routing 0.796ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.789ns (routing 0.892ns, distribution 0.897ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.536     1.903    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.941 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.569     2.510    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.527 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       0.565     3.092    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X81Y272        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[322]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.789     2.264    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X81Y272        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[322]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[327]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.189ns  (logic 0.055ns (4.626%)  route 1.134ns (95.374%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.362ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.264ns
    Source Clock Delay      (SCD):    1.903ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.536ns (routing 0.796ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.789ns (routing 0.892ns, distribution 0.897ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.536     1.903    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.941 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.569     2.510    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.527 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       0.565     3.092    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X81Y272        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[327]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.789     2.264    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X81Y272        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[327]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[337]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.189ns  (logic 0.055ns (4.626%)  route 1.134ns (95.374%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.362ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.265ns
    Source Clock Delay      (SCD):    1.903ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.536ns (routing 0.796ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.790ns (routing 0.892ns, distribution 0.898ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.536     1.903    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.941 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.569     2.510    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.527 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       0.565     3.092    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X81Y273        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[337]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.790     2.265    d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X81Y273        FDRE                                         r  d_1_i/axis_signal_gen_v6_7/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[337]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1118]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.190ns  (logic 0.055ns (4.622%)  route 1.135ns (95.378%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.363ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.265ns
    Source Clock Delay      (SCD):    1.903ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.536ns (routing 0.796ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.790ns (routing 0.892ns, distribution 0.898ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.536     1.903    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.941 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.569     2.510    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.527 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       0.566     3.093    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X81Y268        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1118]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.790     2.265    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X81Y268        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1118]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1123]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.190ns  (logic 0.055ns (4.622%)  route 1.135ns (95.378%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.363ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.265ns
    Source Clock Delay      (SCD):    1.903ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.536ns (routing 0.796ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.790ns (routing 0.892ns, distribution 0.898ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.536     1.903    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.941 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.569     2.510    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.527 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       0.566     3.093    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X81Y268        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1123]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.790     2.265    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X81Y268        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1123]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1128]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.190ns  (logic 0.055ns (4.622%)  route 1.135ns (95.378%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.363ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.265ns
    Source Clock Delay      (SCD):    1.903ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.536ns (routing 0.796ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.790ns (routing 0.892ns, distribution 0.898ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.536     1.903    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.941 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.569     2.510    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.527 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       0.566     3.093    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X81Y268        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1128]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.790     2.265    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X81Y268        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1128]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1129]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.190ns  (logic 0.055ns (4.622%)  route 1.135ns (95.378%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.363ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.265ns
    Source Clock Delay      (SCD):    1.903ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.536ns (routing 0.796ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.790ns (routing 0.892ns, distribution 0.898ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.536     1.903    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.941 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.569     2.510    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.527 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       0.566     3.093    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X81Y268        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1129]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.790     2.265    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X81Y268        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1129]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1138]/R
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.190ns  (logic 0.055ns (4.622%)  route 1.135ns (95.378%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        0.363ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.265ns
    Source Clock Delay      (SCD):    1.903ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.536ns (routing 0.796ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.790ns (routing 0.892ns, distribution 0.898ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.536     1.903    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.941 f  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.569     2.510    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.527 f  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       0.566     3.093    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/clear
    SLICE_X81Y268        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1138]/R  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.790     2.265    d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/aclk
    SLICE_X81Y268        FDRE                                         r  d_1_i/axis_signal_gen_v6_5/inst/signal_gen_top_i/signal_gen_i/dds_ctrl_int_r_reg[1138]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  RFDAC2_CLK

Max Delay           590 Endpoints
Min Delay           590 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.972ns  (logic 0.768ns (19.334%)  route 3.204ns (80.666%))
  Logic Levels:           7  (LUT4=2 LUT5=2 LUT6=3)
  Clock Path Skew:        -1.161ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.140ns
    Source Clock Delay      (SCD):    4.301ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.836ns (routing 0.947ns, distribution 0.889ns)
  Clock Net Delay (Destination): 2.596ns (routing 1.336ns, distribution 1.260ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.836     4.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y212        FDCE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     4.380 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/Q
                         net (fo=10, routed)          0.223     4.603    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[1]
    SLICE_X35Y212        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     4.701 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1/O
                         net (fo=3, routed)           0.600     5.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1_n_0
    SLICE_X39Y215        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.401 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/AXI_DB.xreg_TPROC_DEBUG[4]_i_6/O
                         net (fo=2, routed)           0.295     5.696    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4
    SLICE_X45Y216        LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.796 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_11/O
                         net (fo=2, routed)           0.342     6.138    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_0
    SLICE_X53Y217        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.052     6.190 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=5, routed)           0.149     6.339    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/some_fifo_full
    SLICE_X53Y221        LUT4 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.100     6.439 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=540, routed)         0.346     6.785    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/D[0]
    SLICE_X51Y221        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     6.875 f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.462     7.337    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc_reg[4]_0
    SLICE_X51Y198        LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.149     7.486 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[4]_i_1/O
                         net (fo=1, routed)           0.787     8.273    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[4]
    SLICE_X57Y240        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.596     3.140    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X57Y240        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.731ns  (logic 0.803ns (21.521%)  route 2.928ns (78.479%))
  Logic Levels:           8  (LUT3=2 LUT4=2 LUT5=2 LUT6=2)
  Clock Path Skew:        -1.159ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.142ns
    Source Clock Delay      (SCD):    4.301ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.836ns (routing 0.947ns, distribution 0.889ns)
  Clock Net Delay (Destination): 2.598ns (routing 1.336ns, distribution 1.262ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.836     4.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X35Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y212        FDCE (Prop_GFF2_SLICEM_C_Q)
                                                      0.079     4.380 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r_reg[1]/Q
                         net (fo=10, routed)          0.223     4.603    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/wr_gptr_p1[1]
    SLICE_X35Y212        LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.098     4.701 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1/O
                         net (fo=3, routed)           0.600     5.301    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/count_gray_r[8]_i_5__1_n_0
    SLICE_X39Y215        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.401 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_wr_ptr/AXI_DB.xreg_TPROC_DEBUG[4]_i_6/O
                         net (fo=2, routed)           0.295     5.696    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4
    SLICE_X45Y216        LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.100     5.796 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_11/O
                         net (fo=2, routed)           0.342     6.138    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_fifo_wave_push_r_reg[0]_0
    SLICE_X53Y217        LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.052     6.190 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_4/O
                         net (fo=5, routed)           0.149     6.339    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/some_fifo_full
    SLICE_X53Y221        LUT4 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.100     6.439 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/reg_A[0][31]_i_1/O
                         net (fo=540, routed)         0.346     6.785    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/D[0]
    SLICE_X51Y221        LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     6.875 f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[4]_i_3/O
                         net (fo=4, routed)           0.098     6.973    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/x1_ctrl_reg[usr_ctrl][6]_1
    SLICE_X51Y221        LUT3 (Prop_D5LUT_SLICEL_I0_O)
                                                      0.133     7.106 f  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_CPU/data_cdc[3]_i_2/O
                         net (fo=33, routed)          0.153     7.259    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc_reg[3]
    SLICE_X51Y218        LUT3 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.051     7.310 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/data_cdc[3]_i_1/O
                         net (fo=33, routed)          0.722     8.032    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[6]_0[3]
    SLICE_X59Y240        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.598     3.142    d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/t_clk_i
    SLICE_X59Y240        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/sync_ctrl_ps_t/data_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[0]/CE
                            (rising edge-triggered cell FDPE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.808ns  (logic 0.434ns (24.001%)  route 1.374ns (75.999%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.056ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.252ns
    Source Clock Delay      (SCD):    4.308ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.843ns (routing 0.947ns, distribution 0.896ns)
  Clock Net Delay (Destination): 2.708ns (routing 1.336ns, distribution 1.372ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.843     4.308    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/c_clk_i
    SLICE_X36Y217        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y217        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.387 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.630     5.018    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg_n_0
    SLICE_X38Y220        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     5.164 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/t_fifo_trig_empty_inferred_i_6/O
                         net (fo=2, routed)           0.040     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X38Y220        LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     5.239 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[2]_i_2/O
                         net (fo=1, routed)           0.040     5.279    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r_reg[2]_0
    SLICE_X38Y220        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     5.329 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r[2]_i_1/O
                         net (fo=2, routed)           0.048     5.377    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop49_out
    SLICE_X38Y220        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.124     5.501 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__21/O
                         net (fo=18, routed)          0.615     6.116    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X36Y218        FDPE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.708     3.252    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X36Y218        FDPE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[1]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.808ns  (logic 0.434ns (24.001%)  route 1.374ns (75.999%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.056ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.252ns
    Source Clock Delay      (SCD):    4.308ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.843ns (routing 0.947ns, distribution 0.896ns)
  Clock Net Delay (Destination): 2.708ns (routing 1.336ns, distribution 1.372ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.843     4.308    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/c_clk_i
    SLICE_X36Y217        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y217        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.387 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.630     5.018    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg_n_0
    SLICE_X38Y220        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     5.164 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/t_fifo_trig_empty_inferred_i_6/O
                         net (fo=2, routed)           0.040     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X38Y220        LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     5.239 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[2]_i_2/O
                         net (fo=1, routed)           0.040     5.279    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r_reg[2]_0
    SLICE_X38Y220        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     5.329 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r[2]_i_1/O
                         net (fo=2, routed)           0.048     5.377    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop49_out
    SLICE_X38Y220        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.124     5.501 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__21/O
                         net (fo=18, routed)          0.615     6.116    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X36Y218        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.708     3.252    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X36Y218        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_r_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.806ns  (logic 0.434ns (24.028%)  route 1.372ns (75.972%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.056ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.252ns
    Source Clock Delay      (SCD):    4.308ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.843ns (routing 0.947ns, distribution 0.896ns)
  Clock Net Delay (Destination): 2.708ns (routing 1.336ns, distribution 1.372ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.843     4.308    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/c_clk_i
    SLICE_X36Y217        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y217        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.387 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.630     5.018    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg_n_0
    SLICE_X38Y220        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     5.164 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/t_fifo_trig_empty_inferred_i_6/O
                         net (fo=2, routed)           0.040     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X38Y220        LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     5.239 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[2]_i_2/O
                         net (fo=1, routed)           0.040     5.279    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r_reg[2]_0
    SLICE_X38Y220        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     5.329 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r[2]_i_1/O
                         net (fo=2, routed)           0.048     5.377    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop49_out
    SLICE_X38Y220        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.124     5.501 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__21/O
                         net (fo=18, routed)          0.613     6.114    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X36Y218        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.708     3.252    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X36Y218        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.788ns  (logic 0.434ns (24.279%)  route 1.354ns (75.721%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.058ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.250ns
    Source Clock Delay      (SCD):    4.308ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.843ns (routing 0.947ns, distribution 0.896ns)
  Clock Net Delay (Destination): 2.706ns (routing 1.336ns, distribution 1.370ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.843     4.308    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/c_clk_i
    SLICE_X36Y217        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y217        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.387 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.630     5.018    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg_n_0
    SLICE_X38Y220        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     5.164 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/t_fifo_trig_empty_inferred_i_6/O
                         net (fo=2, routed)           0.040     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X38Y220        LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     5.239 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[2]_i_2/O
                         net (fo=1, routed)           0.040     5.279    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r_reg[2]_0
    SLICE_X38Y220        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     5.329 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r[2]_i_1/O
                         net (fo=2, routed)           0.048     5.377    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop49_out
    SLICE_X38Y220        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.124     5.501 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__21/O
                         net (fo=18, routed)          0.595     6.096    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X36Y218        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.706     3.250    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X36Y218        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.788ns  (logic 0.434ns (24.279%)  route 1.354ns (75.721%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.058ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.250ns
    Source Clock Delay      (SCD):    4.308ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.843ns (routing 0.947ns, distribution 0.896ns)
  Clock Net Delay (Destination): 2.706ns (routing 1.336ns, distribution 1.370ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.843     4.308    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/c_clk_i
    SLICE_X36Y217        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y217        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.387 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.630     5.018    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg_n_0
    SLICE_X38Y220        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     5.164 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/t_fifo_trig_empty_inferred_i_6/O
                         net (fo=2, routed)           0.040     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X38Y220        LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     5.239 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[2]_i_2/O
                         net (fo=1, routed)           0.040     5.279    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r_reg[2]_0
    SLICE_X38Y220        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     5.329 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r[2]_i_1/O
                         net (fo=2, routed)           0.048     5.377    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop49_out
    SLICE_X38Y220        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.124     5.501 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__21/O
                         net (fo=18, routed)          0.595     6.096    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X36Y218        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.706     3.250    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X36Y218        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.788ns  (logic 0.434ns (24.279%)  route 1.354ns (75.721%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.058ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.250ns
    Source Clock Delay      (SCD):    4.308ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.843ns (routing 0.947ns, distribution 0.896ns)
  Clock Net Delay (Destination): 2.706ns (routing 1.336ns, distribution 1.370ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.843     4.308    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/c_clk_i
    SLICE_X36Y217        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y217        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.387 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.630     5.018    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg_n_0
    SLICE_X38Y220        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     5.164 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/t_fifo_trig_empty_inferred_i_6/O
                         net (fo=2, routed)           0.040     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X38Y220        LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     5.239 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[2]_i_2/O
                         net (fo=1, routed)           0.040     5.279    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r_reg[2]_0
    SLICE_X38Y220        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     5.329 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r[2]_i_1/O
                         net (fo=2, routed)           0.048     5.377    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop49_out
    SLICE_X38Y220        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.124     5.501 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__21/O
                         net (fo=18, routed)          0.595     6.096    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X36Y218        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.706     3.250    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X36Y218        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.788ns  (logic 0.434ns (24.279%)  route 1.354ns (75.721%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.058ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.250ns
    Source Clock Delay      (SCD):    4.308ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.843ns (routing 0.947ns, distribution 0.896ns)
  Clock Net Delay (Destination): 2.706ns (routing 1.336ns, distribution 1.370ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.843     4.308    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/c_clk_i
    SLICE_X36Y217        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y217        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.387 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.630     5.018    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg_n_0
    SLICE_X38Y220        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     5.164 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/t_fifo_trig_empty_inferred_i_6/O
                         net (fo=2, routed)           0.040     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X38Y220        LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     5.239 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[2]_i_2/O
                         net (fo=1, routed)           0.040     5.279    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r_reg[2]_0
    SLICE_X38Y220        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     5.329 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r[2]_i_1/O
                         net (fo=2, routed)           0.048     5.377    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop49_out
    SLICE_X38Y220        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.124     5.501 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__21/O
                         net (fo=18, routed)          0.595     6.096    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X36Y218        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.706     3.250    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X36Y218        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/CE
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.763ns  (logic 0.434ns (24.616%)  route 1.329ns (75.384%))
  Logic Levels:           4  (LUT3=1 LUT5=3)
  Clock Path Skew:        -1.057ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.251ns
    Source Clock Delay      (SCD):    4.308ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.843ns (routing 0.947ns, distribution 0.896ns)
  Clock Net Delay (Destination): 2.707ns (routing 1.336ns, distribution 1.371ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.843     4.308    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/c_clk_i
    SLICE_X36Y217        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X36Y217        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     4.387 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg/Q
                         net (fo=4, routed)           0.630     5.018    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/clr_fifo_ack_reg_n_0
    SLICE_X38Y220        LUT3 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.146     5.164 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/t_fifo_trig_empty_inferred_i_6/O
                         net (fo=2, routed)           0.040     5.204    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/D[0]
    SLICE_X38Y220        LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     5.239 f  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop_r[2]_i_2/O
                         net (fo=1, routed)           0.040     5.279    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r_reg[2]_0
    SLICE_X38Y220        LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     5.329 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].ADDSUB_MACRO_inst/trig_pop_r[2]_i_1/O
                         net (fo=2, routed)           0.048     5.377    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/trig_pop49_out
    SLICE_X38Y220        LUT5 (Prop_A6LUT_SLICEL_I4_O)
                                                      0.124     5.501 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_r[8]_i_1__21/O
                         net (fo=18, routed)          0.570     6.071    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_bin_2r
    SLICE_X37Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/CE
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.707     3.251    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X37Y220        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[2].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.338%)  route 0.058ns (59.662%))
  Logic Levels:           0  
  Clock Path Skew:        -0.349ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.281ns
    Source Clock Delay      (SCD):    2.630ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.970ns (routing 0.518ns, distribution 0.452ns)
  Clock Net Delay (Destination): 1.806ns (routing 0.892ns, distribution 0.914ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.970     2.630    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X42Y212        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X42Y212        FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.669 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/Q
                         net (fo=2, routed)           0.058     2.727    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr[0]
    SLICE_X43Y212        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.806     2.281    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/t_clk_i
    SLICE_X43Y212        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/DATA_FIFO[0].data_fifo_inst/wr_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr_cdc_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.521%)  route 0.060ns (60.480%))
  Logic Levels:           0  
  Clock Path Skew:        -0.346ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.284ns
    Source Clock Delay      (SCD):    2.631ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.971ns (routing 0.518ns, distribution 0.453ns)
  Clock Net Delay (Destination): 1.809ns (routing 0.892ns, distribution 0.917ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.971     2.631    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X44Y204        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y204        FDCE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.670 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[8]/Q
                         net (fo=2, routed)           0.060     2.729    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr[8]
    SLICE_X44Y205        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr_cdc_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.809     2.284    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/t_clk_i
    SLICE_X44Y205        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr_cdc_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.039ns (38.735%)  route 0.062ns (61.265%))
  Logic Levels:           0  
  Clock Path Skew:        -0.345ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.287ns
    Source Clock Delay      (SCD):    2.632ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.972ns (routing 0.518ns, distribution 0.454ns)
  Clock Net Delay (Destination): 1.812ns (routing 0.892ns, distribution 0.920ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.972     2.632    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X44Y203        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y203        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.671 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/Q
                         net (fo=2, routed)           0.062     2.733    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr[2]
    SLICE_X44Y201        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.812     2.287    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/t_clk_i
    SLICE_X44Y201        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.041ns (40.321%)  route 0.061ns (59.679%))
  Logic Levels:           0  
  Clock Path Skew:        -0.341ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.291ns
    Source Clock Delay      (SCD):    2.632ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.972ns (routing 0.518ns, distribution 0.454ns)
  Clock Net Delay (Destination): 1.816ns (routing 0.892ns, distribution 0.924ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.972     2.632    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X44Y203        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X44Y203        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     2.673 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/Q
                         net (fo=2, routed)           0.061     2.734    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr[0]
    SLICE_X44Y202        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.816     2.291    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/t_clk_i
    SLICE_X44Y202        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/wr_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/a_pulse_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/pulse_req_cdc_reg/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.099ns  (logic 0.039ns (39.521%)  route 0.060ns (60.480%))
  Logic Levels:           0  
  Clock Path Skew:        -0.355ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.280ns
    Source Clock Delay      (SCD):    2.636ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.976ns (routing 0.518ns, distribution 0.458ns)
  Clock Net Delay (Destination): 1.805ns (routing 0.892ns, distribution 0.913ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.976     2.636    d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/c_clk_i
    SLICE_X48Y202        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/a_pulse_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y202        FDCE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     2.675 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/a_pulse_req_reg/Q
                         net (fo=2, routed)           0.060     2.734    d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/a_pulse_req
    SLICE_X49Y202        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/pulse_req_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.805     2.280    d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/t_clk_i
    SLICE_X49Y202        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.sync_ab_en_inst/pulse_req_cdc_reg/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.076%)  route 0.058ns (59.924%))
  Logic Levels:           0  
  Clock Path Skew:        -0.344ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.293ns
    Source Clock Delay      (SCD):    2.638ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.978ns (routing 0.518ns, distribution 0.460ns)
  Clock Net Delay (Destination): 1.818ns (routing 0.892ns, distribution 0.926ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.978     2.638    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X43Y217        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y217        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     2.677 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[1]/Q
                         net (fo=2, routed)           0.058     2.735    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr[1]
    SLICE_X43Y218        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.818     2.293    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/t_clk_i
    SLICE_X43Y218        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.039ns (38.735%)  route 0.062ns (61.265%))
  Logic Levels:           0  
  Clock Path Skew:        -0.345ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.289ns
    Source Clock Delay      (SCD):    2.635ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.975ns (routing 0.518ns, distribution 0.457ns)
  Clock Net Delay (Destination): 1.814ns (routing 0.892ns, distribution 0.922ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.975     2.635    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X43Y217        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y217        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.674 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[2]/Q
                         net (fo=2, routed)           0.062     2.735    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr[2]
    SLICE_X43Y218        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.814     2.289    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/t_clk_i
    SLICE_X43Y218        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[3].trig_fifo_inst/wr_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/wr_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.039ns (38.735%)  route 0.062ns (61.265%))
  Logic Levels:           0  
  Clock Path Skew:        -0.345ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.290ns
    Source Clock Delay      (SCD):    2.636ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.976ns (routing 0.518ns, distribution 0.458ns)
  Clock Net Delay (Destination): 1.815ns (routing 0.892ns, distribution 0.923ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.976     2.636    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X43Y208        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y208        FDCE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.675 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[0]/Q
                         net (fo=2, routed)           0.062     2.736    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/wr_gptr[0]
    SLICE_X43Y209        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/wr_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.815     2.290    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/t_clk_i
    SLICE_X43Y209        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/wr_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/wr_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.107ns  (logic 0.039ns (36.557%)  route 0.068ns (63.443%))
  Logic Levels:           0  
  Clock Path Skew:        -0.336ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.298ns
    Source Clock Delay      (SCD):    2.635ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.975ns (routing 0.518ns, distribution 0.457ns)
  Clock Net Delay (Destination): 1.823ns (routing 0.892ns, distribution 0.931ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.975     2.635    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/c_clk_i
    SLICE_X42Y208        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X42Y208        FDCE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.674 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/gcc_wr_ptr/count_gray_2r_reg[7]/Q
                         net (fo=2, routed)           0.068     2.741    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/wr_gptr[7]
    SLICE_X42Y209        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/wr_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.823     2.298    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/t_clk_i
    SLICE_X42Y209        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/wr_gptr_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/clr_fifo_req_reg/C
                            (rising edge-triggered cell FDCE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.108ns  (logic 0.039ns (35.975%)  route 0.069ns (64.025%))
  Logic Levels:           0  
  Clock Path Skew:        -0.323ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.310ns
    Source Clock Delay      (SCD):    2.633ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.973ns (routing 0.518ns, distribution 0.455ns)
  Clock Net Delay (Destination): 1.835ns (routing 0.892ns, distribution 0.943ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.973     2.633    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/c_clk_i
    SLICE_X40Y230        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/clr_fifo_req_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y230        FDCE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     2.672 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/clr_fifo_req_reg/Q
                         net (fo=5, routed)           0.069     2.741    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_rd_ptr/clr_fifo_req
    SLICE_X39Y230        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.835     2.310    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X39Y230        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_rd_ptr/clear_cdc_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  RFDAC2_CLK

Max Delay             3 Endpoints
Min Delay             3 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac2_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.068ns  (logic 0.079ns (7.397%)  route 0.989ns (92.603%))
  Logic Levels:           0  
  Clock Path Skew:        0.754ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.375ns
    Source Clock Delay      (SCD):    2.621ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.395ns (routing 0.670ns, distribution 1.725ns)
  Clock Net Delay (Destination): 2.831ns (routing 1.336ns, distribution 1.495ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.395     2.621    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X108Y220       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac2_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y220       FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     2.700 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac2_done_i_reg/Q
                         net (fo=1, routed)           0.989     3.689    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/src_in
    SLICE_X111Y301       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.831     3.375    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/dest_clk
    SLICE_X111Y301       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.767ns  (logic 0.078ns (10.169%)  route 0.689ns (89.830%))
  Logic Levels:           0  
  Clock Path Skew:        0.683ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.312ns
    Source Clock Delay      (SCD):    2.629ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.403ns (routing 0.670ns, distribution 1.733ns)
  Clock Net Delay (Destination): 2.768ns (routing 1.336ns, distribution 1.432ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.403     2.629    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X109Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y224       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.707 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/Q
                         net (fo=1, routed)           0.689     3.396    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/src_in
    SLICE_X110Y278       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.768     3.312    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/dest_clk
    SLICE_X110Y278       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.718ns  (logic 0.078ns (10.864%)  route 0.640ns (89.136%))
  Logic Levels:           0  
  Clock Path Skew:        0.694ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.330ns
    Source Clock Delay      (SCD):    2.636ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.410ns (routing 0.670ns, distribution 1.740ns)
  Clock Net Delay (Destination): 2.786ns (routing 1.336ns, distribution 1.450ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.410     2.636    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X110Y210       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y210       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.714 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/Q
                         net (fo=1, routed)           0.640     3.354    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/src_in
    SLICE_X117Y242       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.281     0.281 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.149     0.430    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.114     0.544 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.786     3.330    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/dest_clk
    SLICE_X117Y242       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.348ns  (logic 0.039ns (11.207%)  route 0.309ns (88.793%))
  Logic Levels:           0  
  Clock Path Skew:        0.933ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.370ns
    Source Clock Delay      (SCD):    1.437ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.317ns (routing 0.363ns, distribution 0.954ns)
  Clock Net Delay (Destination): 1.895ns (routing 0.892ns, distribution 1.003ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.317     1.437    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X110Y210       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X110Y210       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.476 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac0_done_i_reg/Q
                         net (fo=1, routed)           0.309     1.785    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/src_in
    SLICE_X117Y242       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.895     2.370    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/dest_clk
    SLICE_X117Y242       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac0_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.371ns  (logic 0.039ns (10.512%)  route 0.332ns (89.488%))
  Logic Levels:           0  
  Clock Path Skew:        0.921ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.359ns
    Source Clock Delay      (SCD):    1.438ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.318ns (routing 0.363ns, distribution 0.955ns)
  Clock Net Delay (Destination): 1.884ns (routing 0.892ns, distribution 0.992ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.318     1.438    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X109Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X109Y224       FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.477 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac1_done_i_reg/Q
                         net (fo=1, routed)           0.332     1.809    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/src_in
    SLICE_X110Y278       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.884     2.359    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/dest_clk
    SLICE_X110Y278       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac1_done_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac2_done_i_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.505ns  (logic 0.039ns (7.723%)  route 0.466ns (92.277%))
  Logic Levels:           0  
  Clock Path Skew:        0.965ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.399ns
    Source Clock Delay      (SCD):    1.435ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.315ns (routing 0.363ns, distribution 0.952ns)
  Clock Net Delay (Destination): 1.924ns (routing 0.892ns, distribution 1.032ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.315     1.435    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    SLICE_X108Y220       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac2_done_i_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X108Y220       FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.474 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/dac2_done_i_reg/Q
                         net (fo=1, routed)           0.466     1.940    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/src_in
    SLICE_X111Y301       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.224     0.224 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.169     0.393    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.082     0.475 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.924     2.399    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/dest_clk
    SLICE_X111Y301       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac2_done_i/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC2_CLK
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay           242 Endpoints
Min Delay           242 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/async_empty_r_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_trig_empty_cdc_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.389ns  (logic 0.146ns (10.511%)  route 1.243ns (89.489%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.779ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.486ns
    Source Clock Delay      (SCD):    3.707ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.996ns (routing 1.474ns, distribution 1.522ns)
  Clock Net Delay (Destination): 1.551ns (routing 0.863ns, distribution 0.688ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.996     3.707    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/t_clk_i
    SLICE_X40Y230        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/async_empty_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y230        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.786 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/async_empty_r_reg/Q
                         net (fo=1, routed)           0.041     3.827    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/async_empty_r_reg_n_0
    SLICE_X40Y230        LUT3 (Prop_G5LUT_SLICEL_I2_O)
                                                      0.067     3.894 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/t_fifo_trig_empty_inferred_i_3/O
                         net (fo=2, routed)           1.202     5.096    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_fifo_trig_empty[5]
    SLICE_X42Y219        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_trig_empty_cdc_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.551     4.486    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X42Y219        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_trig_empty_cdc_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/async_empty_r_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_trig_empty_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.163ns  (logic 0.147ns (12.639%)  route 1.016ns (87.361%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.735ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.491ns
    Source Clock Delay      (SCD):    3.756ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      3.045ns (routing 1.474ns, distribution 1.571ns)
  Clock Net Delay (Destination): 1.556ns (routing 0.863ns, distribution 0.693ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       3.045     3.756    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_clk_i
    SLICE_X33Y221        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/async_empty_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y221        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.835 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/async_empty_r_reg/Q
                         net (fo=1, routed)           0.200     4.035    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/async_empty_r
    SLICE_X35Y222        LUT3 (Prop_C5LUT_SLICEM_I2_O)
                                                      0.068     4.103 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[0].trig_fifo_inst/t_fifo_trig_empty_inferred_i_8/O
                         net (fo=2, routed)           0.816     4.919    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_fifo_trig_empty[0]
    SLICE_X38Y220        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_trig_empty_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.556     4.491    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X38Y220        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_trig_empty_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/async_empty_r_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_trig_empty_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.922ns  (logic 0.177ns (19.197%)  route 0.745ns (80.803%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.810ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.498ns
    Source Clock Delay      (SCD):    3.688ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.977ns (routing 1.474ns, distribution 1.503ns)
  Clock Net Delay (Destination): 1.563ns (routing 0.863ns, distribution 0.700ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.977     3.688    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/t_clk_i
    SLICE_X41Y232        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/async_empty_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y232        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.766 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/async_empty_r_reg/Q
                         net (fo=1, routed)           0.047     3.813    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/async_empty_r_reg_n_0
    SLICE_X41Y232        LUT3 (Prop_C5LUT_SLICEM_I2_O)
                                                      0.099     3.912 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[4].trig_fifo_inst/t_fifo_trig_empty_inferred_i_4/O
                         net (fo=2, routed)           0.698     4.610    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_fifo_trig_empty[4]
    SLICE_X50Y229        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_trig_empty_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.563     4.498    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X50Y229        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_trig_empty_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/async_empty_r_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_wave_empty_cdc_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.924ns  (logic 0.147ns (15.916%)  route 0.777ns (84.084%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.853ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.511ns
    Source Clock Delay      (SCD):    3.658ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.947ns (routing 1.474ns, distribution 1.473ns)
  Clock Net Delay (Destination): 1.576ns (routing 0.863ns, distribution 0.713ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.947     3.658    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/t_clk_i
    SLICE_X51Y242        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/async_empty_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y242        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.737 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/async_empty_r_reg/Q
                         net (fo=1, routed)           0.261     3.998    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/async_empty_r_reg_n_0
    SLICE_X52Y250        LUT3 (Prop_C5LUT_SLICEL_I2_O)
                                                      0.068     4.066 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[3].wave_fifo_inst/t_fifo_wave_empty_inferred_i_7/O
                         net (fo=2, routed)           0.516     4.581    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_fifo_wave_empty[3]
    SLICE_X53Y235        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_wave_empty_cdc_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.576     4.511    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X53Y235        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_wave_empty_cdc_reg[3]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/async_empty_r_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_trig_empty_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.889ns  (logic 0.177ns (19.910%)  route 0.712ns (80.090%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.812ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.484ns
    Source Clock Delay      (SCD):    3.672ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.961ns (routing 1.474ns, distribution 1.487ns)
  Clock Net Delay (Destination): 1.549ns (routing 0.863ns, distribution 0.686ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.961     3.672    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/t_clk_i
    SLICE_X42Y206        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/async_empty_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X42Y206        FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.750 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/async_empty_r_reg/Q
                         net (fo=1, routed)           0.047     3.797    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/async_empty_r_reg_n_0
    SLICE_X42Y206        LUT3 (Prop_C5LUT_SLICEM_I2_O)
                                                      0.099     3.896 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[7].trig_fifo_inst/t_fifo_trig_empty_inferred_i_1/O
                         net (fo=2, routed)           0.665     4.561    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_fifo_trig_empty[7]
    SLICE_X46Y215        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_trig_empty_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.549     4.484    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X46Y215        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_trig_empty_cdc_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr_cdc_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.883ns  (logic 0.079ns (8.948%)  route 0.804ns (91.052%))
  Logic Levels:           0  
  Clock Path Skew:        0.867ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.538ns
    Source Clock Delay      (SCD):    3.671ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.960ns (routing 1.474ns, distribution 1.486ns)
  Clock Net Delay (Destination): 1.603ns (routing 0.863ns, distribution 0.740ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.960     3.671    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X38Y215        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y215        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.750 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[4]/Q
                         net (fo=3, routed)           0.804     4.554    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr[4]
    SLICE_X37Y212        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr_cdc_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.603     4.538    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/c_clk_i
    SLICE_X37Y212        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr_cdc_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.840ns  (logic 0.076ns (9.049%)  route 0.764ns (90.951%))
  Logic Levels:           0  
  Clock Path Skew:        0.806ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.505ns
    Source Clock Delay      (SCD):    3.699ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.988ns (routing 1.474ns, distribution 1.514ns)
  Clock Net Delay (Destination): 1.570ns (routing 0.863ns, distribution 0.707ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.988     3.699    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X46Y227        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y227        FDCE (Prop_FFF_SLICEM_C_Q)
                                                      0.076     3.775 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/Q
                         net (fo=5, routed)           0.764     4.539    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr[8]
    SLICE_X52Y227        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.570     4.505    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/c_clk_i
    SLICE_X52Y227        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[0].wave_fifo_inst/rd_gptr_cdc_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.833ns  (logic 0.079ns (9.479%)  route 0.754ns (90.521%))
  Logic Levels:           0  
  Clock Path Skew:        0.858ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.540ns
    Source Clock Delay      (SCD):    3.681ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.970ns (routing 1.474ns, distribution 1.496ns)
  Clock Net Delay (Destination): 1.605ns (routing 0.863ns, distribution 0.742ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.970     3.681    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X38Y214        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y214        FDCE (Prop_HFF_SLICEL_C_Q)
                                                      0.079     3.760 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[2]/Q
                         net (fo=3, routed)           0.754     4.515    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr[2]
    SLICE_X35Y211        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr_cdc_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.605     4.540    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/c_clk_i
    SLICE_X35Y211        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[1].trig_fifo_inst/rd_gptr_cdc_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/rd_gptr_cdc_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.847ns  (logic 0.078ns (9.211%)  route 0.769ns (90.789%))
  Logic Levels:           0  
  Clock Path Skew:        0.900ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.558ns
    Source Clock Delay      (SCD):    3.658ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.947ns (routing 1.474ns, distribution 1.473ns)
  Clock Net Delay (Destination): 1.623ns (routing 0.863ns, distribution 0.760ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.947     3.658    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X56Y238        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y238        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     3.736 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[5]/Q
                         net (fo=5, routed)           0.769     4.505    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/rd_gptr[5]
    SLICE_X55Y245        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/rd_gptr_cdc_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.623     4.558    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/c_clk_i
    SLICE_X55Y245        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[5].wave_fifo_inst/rd_gptr_cdc_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/async_empty_r_reg/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_wave_empty_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.883ns  (logic 0.237ns (26.835%)  route 0.646ns (73.165%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.938ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.554ns
    Source Clock Delay      (SCD):    3.616ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.905ns (routing 1.474ns, distribution 1.431ns)
  Clock Net Delay (Destination): 1.619ns (routing 0.863ns, distribution 0.756ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.905     3.616    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/t_clk_i
    SLICE_X57Y259        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/async_empty_r_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y259        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     3.695 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/async_empty_r_reg/Q
                         net (fo=1, routed)           0.057     3.752    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/async_empty_r_reg_n_0
    SLICE_X57Y259        LUT3 (Prop_C5LUT_SLICEL_I2_O)
                                                      0.158     3.910 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/t_fifo_wave_empty_inferred_i_9/O
                         net (fo=2, routed)           0.589     4.499    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_fifo_wave_empty[1]
    SLICE_X54Y250        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_wave_empty_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.619     4.554    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/c_clk_i
    SLICE_X54Y250        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/fifo_wave_empty_cdc_reg[1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[19]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.039ns (37.500%)  route 0.065ns (62.500%))
  Logic Levels:           0  
  Clock Path Skew:        0.449ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.422ns
    Source Clock Delay      (SCD):    1.974ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.607ns (routing 0.796ns, distribution 0.811ns)
  Clock Net Delay (Destination): 1.105ns (routing 0.574ns, distribution 0.531ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.607     1.974    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X50Y200        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[19]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y200        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     2.013 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[19]/Q
                         net (fo=1, routed)           0.065     2.078    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[19]
    SLICE_X50Y200        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.105     2.422    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X50Y200        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[19]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr_cdc_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.136ns  (logic 0.041ns (30.079%)  route 0.095ns (69.921%))
  Logic Levels:           0  
  Clock Path Skew:        0.517ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.463ns
    Source Clock Delay      (SCD):    1.946ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.579ns (routing 0.796ns, distribution 0.783ns)
  Clock Net Delay (Destination): 1.146ns (routing 0.574ns, distribution 0.572ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.579     1.946    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X57Y260        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y260        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.987 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[0]/Q
                         net (fo=5, routed)           0.095     2.082    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr[0]
    SLICE_X59Y262        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr_cdc_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.146     2.463    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/c_clk_i
    SLICE_X59Y262        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr_cdc_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr_cdc_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.142ns  (logic 0.039ns (27.494%)  route 0.103ns (72.506%))
  Logic Levels:           0  
  Clock Path Skew:        0.512ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.459ns
    Source Clock Delay      (SCD):    1.947ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.580ns (routing 0.796ns, distribution 0.784ns)
  Clock Net Delay (Destination): 1.142ns (routing 0.574ns, distribution 0.568ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.580     1.947    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X57Y258        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y258        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.986 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[1]/Q
                         net (fo=5, routed)           0.103     2.088    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr[1]
    SLICE_X59Y262        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr_cdc_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.142     2.459    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/c_clk_i
    SLICE_X59Y262        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/WAVE_FIFO[1].wave_fifo_inst/rd_gptr_cdc_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.040ns (33.898%)  route 0.078ns (66.102%))
  Logic Levels:           0  
  Clock Path Skew:        0.449ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.421ns
    Source Clock Delay      (SCD):    1.973ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.606ns (routing 0.796ns, distribution 0.810ns)
  Clock Net Delay (Destination): 1.104ns (routing 0.574ns, distribution 0.530ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.606     1.973    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X51Y202        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y202        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.013 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[11]/Q
                         net (fo=1, routed)           0.078     2.091    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[11]
    SLICE_X51Y202        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.104     2.421    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X51Y202        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.115ns  (logic 0.039ns (33.913%)  route 0.076ns (66.087%))
  Logic Levels:           0  
  Clock Path Skew:        0.442ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.418ns
    Source Clock Delay      (SCD):    1.977ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.610ns (routing 0.796ns, distribution 0.814ns)
  Clock Net Delay (Destination): 1.101ns (routing 0.574ns, distribution 0.527ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.610     1.977    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X51Y200        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y200        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.016 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[7]/Q
                         net (fo=1, routed)           0.076     2.092    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[7]
    SLICE_X51Y200        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.101     2.418    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X51Y200        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[18]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.040ns (32.258%)  route 0.084ns (67.742%))
  Logic Levels:           0  
  Clock Path Skew:        0.448ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.417ns
    Source Clock Delay      (SCD):    1.969ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.602ns (routing 0.796ns, distribution 0.806ns)
  Clock Net Delay (Destination): 1.100ns (routing 0.574ns, distribution 0.526ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.602     1.969    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X50Y201        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[18]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y201        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.009 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[18]/Q
                         net (fo=1, routed)           0.084     2.093    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[18]
    SLICE_X50Y201        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[18]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.100     2.417    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X50Y201        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[18]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[28]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.040ns (33.058%)  route 0.081ns (66.942%))
  Logic Levels:           0  
  Clock Path Skew:        0.449ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.421ns
    Source Clock Delay      (SCD):    1.973ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.606ns (routing 0.796ns, distribution 0.810ns)
  Clock Net Delay (Destination): 1.104ns (routing 0.574ns, distribution 0.530ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.606     1.973    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X51Y202        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[28]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y202        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     2.013 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[28]/Q
                         net (fo=1, routed)           0.081     2.094    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[28]
    SLICE_X51Y202        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.104     2.421    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X51Y202        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[28]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/rd_gptr_cdc_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.039ns (38.319%)  route 0.063ns (61.681%))
  Logic Levels:           0  
  Clock Path Skew:        0.431ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.423ns
    Source Clock Delay      (SCD):    1.993ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.626ns (routing 0.796ns, distribution 0.830ns)
  Clock Net Delay (Destination): 1.106ns (routing 0.574ns, distribution 0.532ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.626     1.993    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X38Y230        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X38Y230        FDCE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     2.032 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[8]/Q
                         net (fo=3, routed)           0.063     2.094    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/rd_gptr[8]
    SLICE_X38Y228        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/rd_gptr_cdc_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.106     2.423    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/c_clk_i
    SLICE_X38Y228        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[5].trig_fifo_inst/rd_gptr_cdc_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.041ns (32.800%)  route 0.084ns (67.200%))
  Logic Levels:           0  
  Clock Path Skew:        0.449ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.421ns
    Source Clock Delay      (SCD):    1.973ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.606ns (routing 0.796ns, distribution 0.810ns)
  Clock Net Delay (Destination): 1.104ns (routing 0.574ns, distribution 0.530ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.606     1.973    d_1_i/qick_processor_0/inst/QPROC/t_clk_i
    SLICE_X51Y202        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y202        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     2.014 r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.t_time_abs_cdc_reg[9]/Q
                         net (fo=1, routed)           0.084     2.098    d_1_i/qick_processor_0/inst/QPROC/t_time_abs_cdc[9]
    SLICE_X51Y202        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.104     2.421    d_1_i/qick_processor_0/inst/QPROC/c_clk_i
    SLICE_X51Y202        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPER_TIME_READ.c_time_abs_r_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr_cdc_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.039ns (33.083%)  route 0.079ns (66.917%))
  Logic Levels:           0  
  Clock Path Skew:        0.436ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.416ns
    Source Clock Delay      (SCD):    1.981ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.149ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.614ns (routing 0.796ns, distribution 0.818ns)
  Clock Net Delay (Destination): 1.099ns (routing 0.574ns, distribution 0.525ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.614     1.981    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/t_clk_i
    SLICE_X46Y204        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y204        FDCE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     2.020 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/gcc_rd_ptr/count_gray_2r_reg[7]/Q
                         net (fo=3, routed)           0.079     2.098    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr[7]
    SLICE_X45Y204        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr_cdc_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.099     2.416    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/c_clk_i
    SLICE_X45Y204        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/TRIG_FIFO[6].trig_fifo_inst/rd_gptr_cdc_reg[7]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay           336 Endpoints
Min Delay           336 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/PR_OUT_DFF[0].FDRE_PER/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/rst_core/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.578ns  (logic 0.080ns (5.070%)  route 1.498ns (94.930%))
  Logic Levels:           0  
  Clock Path Skew:        2.119ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.618ns
    Source Clock Delay      (SCD):    2.499ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.273ns (routing 0.670ns, distribution 1.603ns)
  Clock Net Delay (Destination): 1.683ns (routing 0.863ns, distribution 0.820ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.273     2.499    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X81Y171        FDRE                                         r  d_1_i/rst_100/U0/PR_OUT_DFF[0].FDRE_PER/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y171        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.080     2.579 r  d_1_i/rst_100/U0/PR_OUT_DFF[0].FDRE_PER/Q
                         net (fo=2, routed)           1.498     4.077    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X75Y222        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.683     4.618    d_1_i/rst_core/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X75Y222        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMD/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[48]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.903ns  (logic 0.287ns (31.783%)  route 0.616ns (68.217%))
  Logic Levels:           0  
  Clock Path Skew:        2.197ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.586ns
    Source Clock Delay      (SCD):    2.389ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.163ns (routing 0.670ns, distribution 1.493ns)
  Clock Net Delay (Destination): 1.651ns (routing 0.863ns, distribution 0.788ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.163     2.389    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X66Y182        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMD/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y182        RAMD32 (Prop_D5LUT_SLICEM_CLK_O)
                                                      0.287     2.676 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMD/O
                         net (fo=1, routed)           0.616     3.292    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[48]
    SLICE_X64Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[48]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.651     4.586    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X64Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[48]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[38]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.895ns  (logic 0.295ns (32.961%)  route 0.600ns (67.039%))
  Logic Levels:           0  
  Clock Path Skew:        2.197ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.586ns
    Source Clock Delay      (SCD):    2.389ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.163ns (routing 0.670ns, distribution 1.493ns)
  Clock Net Delay (Destination): 1.651ns (routing 0.863ns, distribution 0.788ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.163     2.389    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X66Y181        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y181        RAMD32 (Prop_F5LUT_SLICEM_CLK_O)
                                                      0.295     2.684 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF/O
                         net (fo=1, routed)           0.600     3.284    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[38]
    SLICE_X64Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[38]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.651     4.586    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X64Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[38]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.894ns  (logic 0.289ns (32.327%)  route 0.605ns (67.673%))
  Logic Levels:           0  
  Clock Path Skew:        2.190ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.579ns
    Source Clock Delay      (SCD):    2.389ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.163ns (routing 0.670ns, distribution 1.493ns)
  Clock Net Delay (Destination): 1.644ns (routing 0.863ns, distribution 0.781ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.163     2.389    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X66Y181        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y181        RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.289     2.678 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA/O
                         net (fo=1, routed)           0.605     3.283    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[28]
    SLICE_X62Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.644     4.579    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X62Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[28]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[30]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.849ns  (logic 0.292ns (34.393%)  route 0.557ns (65.607%))
  Logic Levels:           0  
  Clock Path Skew:        2.194ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.583ns
    Source Clock Delay      (SCD):    2.389ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.163ns (routing 0.670ns, distribution 1.493ns)
  Clock Net Delay (Destination): 1.648ns (routing 0.863ns, distribution 0.785ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.163     2.389    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X66Y181        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y181        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     2.681 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMB/O
                         net (fo=1, routed)           0.557     3.238    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[30]
    SLICE_X61Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[30]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.648     4.583    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X61Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[30]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.864ns  (logic 0.304ns (35.185%)  route 0.560ns (64.815%))
  Logic Levels:           0  
  Clock Path Skew:        2.212ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.583ns
    Source Clock Delay      (SCD):    2.371ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.145ns (routing 0.670ns, distribution 1.475ns)
  Clock Net Delay (Destination): 1.648ns (routing 0.863ns, distribution 0.785ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.145     2.371    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X63Y181        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y181        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.304     2.675 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMF_D1/O
                         net (fo=1, routed)           0.560     3.235    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[11]
    SLICE_X63Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.648     4.583    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X63Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[44]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.785ns  (logic 0.292ns (37.197%)  route 0.493ns (62.803%))
  Logic Levels:           0  
  Clock Path Skew:        2.199ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.588ns
    Source Clock Delay      (SCD):    2.389ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.163ns (routing 0.670ns, distribution 1.493ns)
  Clock Net Delay (Destination): 1.653ns (routing 0.863ns, distribution 0.790ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.163     2.389    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X66Y182        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y182        RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     2.681 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMB/O
                         net (fo=1, routed)           0.493     3.174    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[44]
    SLICE_X63Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[44]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.653     4.588    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X63Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[44]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMG/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.785ns  (logic 0.281ns (35.796%)  route 0.504ns (64.204%))
  Logic Levels:           0  
  Clock Path Skew:        2.208ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.579ns
    Source Clock Delay      (SCD):    2.371ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.145ns (routing 0.670ns, distribution 1.475ns)
  Clock Net Delay (Destination): 1.644ns (routing 0.863ns, distribution 0.781ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.145     2.371    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X63Y181        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMG/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X63Y181        RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.281     2.652 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMG/O
                         net (fo=1, routed)           0.504     3.156    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[12]
    SLICE_X62Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.644     4.579    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X62Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[50]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.762ns  (logic 0.288ns (37.795%)  route 0.474ns (62.205%))
  Logic Levels:           0  
  Clock Path Skew:        2.194ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.583ns
    Source Clock Delay      (SCD):    2.389ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.163ns (routing 0.670ns, distribution 1.493ns)
  Clock Net Delay (Destination): 1.648ns (routing 0.863ns, distribution 0.785ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.163     2.389    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X66Y182        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y182        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     2.677 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAME/O
                         net (fo=1, routed)           0.474     3.151    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[50]
    SLICE_X63Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[50]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.648     4.583    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X63Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[50]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[37]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.761ns  (logic 0.302ns (39.685%)  route 0.459ns (60.315%))
  Logic Levels:           0  
  Clock Path Skew:        2.197ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.586ns
    Source Clock Delay      (SCD):    2.389ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      2.163ns (routing 0.670ns, distribution 1.493ns)
  Clock Net Delay (Destination): 1.651ns (routing 0.863ns, distribution 0.788ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.163     2.389    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X66Y181        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y181        RAMD32 (Prop_E6LUT_SLICEM_CLK_O)
                                                      0.302     2.691 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAME_D1/O
                         net (fo=1, routed)           0.459     3.150    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[37]
    SLICE_X64Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[37]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.651     4.586    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X64Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[37]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.116ns  (logic 0.039ns (33.621%)  route 0.077ns (66.379%))
  Logic Levels:           0  
  Clock Path Skew:        1.185ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.422ns
    Source Clock Delay      (SCD):    1.237ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.117ns (routing 0.363ns, distribution 0.754ns)
  Clock Net Delay (Destination): 1.105ns (routing 0.574ns, distribution 0.531ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.117     1.237    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X52Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y182        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.276 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.077     1.353    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1]
    SLICE_X52Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.105     2.422    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X52Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.151ns  (logic 0.039ns (25.857%)  route 0.112ns (74.143%))
  Logic Levels:           0  
  Clock Path Skew:        1.188ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.424ns
    Source Clock Delay      (SCD):    1.236ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.116ns (routing 0.363ns, distribution 0.753ns)
  Clock Net Delay (Destination): 1.107ns (routing 0.574ns, distribution 0.533ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.116     1.236    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X50Y181        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y181        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.275 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.112     1.386    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X50Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.107     2.424    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X50Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.039ns (37.981%)  route 0.064ns (62.019%))
  Logic Levels:           0  
  Clock Path Skew:        1.195ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.487ns
    Source Clock Delay      (SCD):    1.293ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.173ns (routing 0.363ns, distribution 0.810ns)
  Clock Net Delay (Destination): 1.170ns (routing 0.574ns, distribution 0.596ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.173     1.293    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X68Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y184        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.332 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.064     1.395    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X68Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.170     2.487    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X68Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.166ns  (logic 0.039ns (23.494%)  route 0.127ns (76.506%))
  Logic Levels:           0  
  Clock Path Skew:        1.183ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.424ns
    Source Clock Delay      (SCD):    1.241ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.121ns (routing 0.363ns, distribution 0.758ns)
  Clock Net Delay (Destination): 1.107ns (routing 0.574ns, distribution 0.533ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.121     1.241    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X49Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y184        FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.280 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.127     1.407    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2]
    SLICE_X48Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.107     2.424    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X48Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.039ns (32.500%)  route 0.081ns (67.500%))
  Logic Levels:           0  
  Clock Path Skew:        1.202ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.491ns
    Source Clock Delay      (SCD):    1.290ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.170ns (routing 0.363ns, distribution 0.807ns)
  Clock Net Delay (Destination): 1.174ns (routing 0.574ns, distribution 0.600ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.170     1.290    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X68Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y182        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.329 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.081     1.410    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[2]
    SLICE_X68Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.174     2.491    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X68Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.038ns (29.921%)  route 0.089ns (70.079%))
  Logic Levels:           0  
  Clock Path Skew:        1.201ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.492ns
    Source Clock Delay      (SCD):    1.291ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.171ns (routing 0.363ns, distribution 0.808ns)
  Clock Net Delay (Destination): 1.175ns (routing 0.574ns, distribution 0.601ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.171     1.291    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X67Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y183        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.329 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.089     1.418    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[4]
    SLICE_X67Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.175     2.492    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X67Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.136ns  (logic 0.041ns (30.147%)  route 0.095ns (69.853%))
  Logic Levels:           0  
  Clock Path Skew:        1.198ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.487ns
    Source Clock Delay      (SCD):    1.290ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.170ns (routing 0.363ns, distribution 0.807ns)
  Clock Net Delay (Destination): 1.170ns (routing 0.574ns, distribution 0.596ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.170     1.290    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X68Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y182        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.331 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.095     1.426    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X68Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.170     2.487    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X68Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[47]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.167ns  (logic 0.110ns (65.868%)  route 0.057ns (34.132%))
  Logic Levels:           0  
  Clock Path Skew:        1.163ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.422ns
    Source Clock Delay      (SCD):    1.259ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.139ns (routing 0.363ns, distribution 0.776ns)
  Clock Net Delay (Destination): 1.105ns (routing 0.574ns, distribution 0.531ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.139     1.259    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X53Y180        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y180        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.110     1.369 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMC_D1/O
                         net (fo=1, routed)           0.057     1.426    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[47]
    SLICE_X52Y180        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[47]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.105     2.422    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X52Y180        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[47]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.166ns  (logic 0.105ns (63.253%)  route 0.061ns (36.747%))
  Logic Levels:           0  
  Clock Path Skew:        1.174ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.436ns
    Source Clock Delay      (SCD):    1.262ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.142ns (routing 0.363ns, distribution 0.779ns)
  Clock Net Delay (Destination): 1.119ns (routing 0.574ns, distribution 0.545ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.142     1.262    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/WCLK
    SLICE_X48Y187        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y187        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     1.367 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_13/RAMG_D1/O
                         net (fo=1, routed)           0.061     1.428    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[13]
    SLICE_X50Y187        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.119     2.436    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X50Y187        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMG_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[55]/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.183ns  (logic 0.105ns (57.377%)  route 0.078ns (42.623%))
  Logic Levels:           0  
  Clock Path Skew:        1.163ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.422ns
    Source Clock Delay      (SCD):    1.259ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.153ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.111ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.139ns (routing 0.363ns, distribution 0.776ns)
  Clock Net Delay (Destination): 1.105ns (routing 0.574ns, distribution 0.531ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.139     1.259    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X53Y180        RAMD32                                       r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMG_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y180        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.105     1.364 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMG_D1/O
                         net (fo=1, routed)           0.078     1.442    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[55]
    SLICE_X52Y180        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[55]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.105     2.422    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X52Y180        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[55]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay           143 Endpoints
Min Delay           143 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC3[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.747ns  (logic 0.000ns (0.000%)  route 2.747ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.102ns (routing 0.606ns, distribution 1.496ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC3[14]
                         net (fo=1, routed)           2.747     2.747    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_data_irq/src_in
    SLICE_X101Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.102     2.284    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_data_irq/dest_clk
    SLICE_X101Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC0[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac30_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.709ns  (logic 0.000ns (0.000%)  route 2.709ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.142ns (routing 0.606ns, distribution 1.536ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC0[14]
                         net (fo=1, routed)           2.709     2.709    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac30_data_irq/src_in
    SLICE_X108Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac30_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.142     2.324    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac30_data_irq/dest_clk
    SLICE_X108Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac30_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC2[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.671ns  (logic 0.000ns (0.000%)  route 2.671ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.119ns (routing 0.606ns, distribution 1.513ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC2[14]
                         net (fo=1, routed)           2.671     2.671    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_data_irq/src_in
    SLICE_X104Y229       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.119     2.301    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_data_irq/dest_clk
    SLICE_X104Y229       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac3_supplies_up_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.629ns  (logic 0.000ns (0.000%)  route 2.629ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.152ns (routing 0.606ns, distribution 1.546ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[1]
                         net (fo=2, routed)           2.629     2.629    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac3_supplies_up_i/src_in
    SLICE_X114Y221       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac3_supplies_up_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.152     2.334    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac3_supplies_up_i/dest_clk
    SLICE_X114Y221       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_dac3_supplies_up_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC2[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.627ns  (logic 0.000ns (0.000%)  route 2.627ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.100ns (routing 0.606ns, distribution 1.494ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC2[15]
                         net (fo=1, routed)           2.627     2.627    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_fifo_irq/src_in
    SLICE_X100Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.100     2.282    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_fifo_irq/dest_clk
    SLICE_X100Y222       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac32_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC1[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.494ns  (logic 0.000ns (0.000%)  route 2.494ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.106ns (routing 0.606ns, distribution 1.500ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC1[14]
                         net (fo=1, routed)           2.494     2.494    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_data_irq/src_in
    SLICE_X103Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.106     2.288    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_data_irq/dest_clk
    SLICE_X103Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC3[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.481ns  (logic 0.000ns (0.000%)  route 2.481ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.104ns (routing 0.606ns, distribution 1.498ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC3[15]
                         net (fo=1, routed)           2.481     2.481    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_fifo_irq/src_in
    SLICE_X102Y234       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.104     2.286    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_fifo_irq/dest_clk
    SLICE_X102Y234       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac33_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC0[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac30_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.453ns  (logic 0.000ns (0.000%)  route 2.453ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.105ns (routing 0.606ns, distribution 1.499ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC0[15]
                         net (fo=1, routed)           2.453     2.453    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac30_fifo_irq/src_in
    SLICE_X103Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac30_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.105     2.287    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac30_fifo_irq/dest_clk
    SLICE_X103Y223       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac30_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_DAC3[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac23_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.376ns  (logic 0.000ns (0.000%)  route 2.376ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.119ns (routing 0.606ns, distribution 1.513ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_DAC3[15]
                         net (fo=1, routed)           2.376     2.376    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac23_fifo_irq/src_in
    SLICE_X106Y221       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac23_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.119     2.301    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac23_fifo_irq/dest_clk
    SLICE_X106Y221       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac23_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC1[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.359ns  (logic 0.000ns (0.000%)  route 2.359ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.114ns (routing 0.606ns, distribution 1.508ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_DAC1[15]
                         net (fo=1, routed)           2.359     2.359    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_fifo_irq/src_in
    SLICE_X105Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.114     2.296    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_fifo_irq/dest_clk
    SLICE_X105Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_dac31_fifo_irq/syncstages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc3_status_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.194ns  (logic 0.000ns (0.000%)  route 0.194ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.500ns (routing 0.408ns, distribution 1.092ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[0]
                         net (fo=1, routed)           0.194     0.194    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc3_status_i/src_in
    SLICE_X116Y170       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc3_status_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.500     1.647    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc3_status_i/dest_clk
    SLICE_X116Y170       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc3_status_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.222ns  (logic 0.000ns (0.000%)  route 0.222ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.484ns (routing 0.408ns, distribution 1.076ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[15]
                         net (fo=1, routed)           0.222     0.222    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_fifo_irq/src_in
    SLICE_X117Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.484     1.631    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_fifo_irq/dest_clk
    SLICE_X117Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc3_supplies_up_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.234ns  (logic 0.000ns (0.000%)  route 0.234ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.483ns (routing 0.408ns, distribution 1.075ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[1]
                         net (fo=2, routed)           0.234     0.234    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc3_supplies_up_i/src_in
    SLICE_X115Y205       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc3_supplies_up_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.483     1.630    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc3_supplies_up_i/dest_clk
    SLICE_X115Y205       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/cdc_adc3_supplies_up_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[0]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc2_status_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.240ns  (logic 0.000ns (0.000%)  route 0.240ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.509ns (routing 0.408ns, distribution 1.101ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[0]
                         net (fo=1, routed)           0.240     0.240    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc2_status_i/src_in
    SLICE_X116Y172       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc2_status_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.509     1.656    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc2_status_i/dest_clk
    SLICE_X116Y172       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/por_state_machine_i/por_fsm_adc2/cdc_adc2_status_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_range/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.268ns  (logic 0.000ns (0.000%)  route 0.268ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.487ns (routing 0.408ns, distribution 1.079ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[3]
                         net (fo=1, routed)           0.268     0.268    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_range/src_in
    SLICE_X118Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_range/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.487     1.634    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_range/dest_clk
    SLICE_X118Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_over_range/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[15]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_fifo_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.301ns  (logic 0.000ns (0.000%)  route 0.301ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.495ns (routing 0.408ns, distribution 1.087ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[15]
                         net (fo=1, routed)           0.301     0.301    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_fifo_irq/src_in
    SLICE_X110Y181       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_fifo_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.495     1.642    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_fifo_irq/dest_clk
    SLICE_X110Y181       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_fifo_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[19]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_cm_under_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.313ns  (logic 0.000ns (0.000%)  route 0.313ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.501ns (routing 0.408ns, distribution 1.093ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC1[19]
                         net (fo=1, routed)           0.313     0.313    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_cm_under_vol/src_in
    SLICE_X118Y175       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_cm_under_vol/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.501     1.648    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_cm_under_vol/dest_clk
    SLICE_X118Y175       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc21_cm_under_vol/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[14]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_data_irq/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.316ns  (logic 0.000ns (0.000%)  route 0.316ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.494ns (routing 0.408ns, distribution 1.086ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[14]
                         net (fo=1, routed)           0.316     0.316    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_data_irq/src_in
    SLICE_X113Y195       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_data_irq/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.494     1.641    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_data_irq/dest_clk
    SLICE_X113Y195       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_data_irq/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[18]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_cm_over_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.323ns  (logic 0.000ns (0.000%)  route 0.323ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.484ns (routing 0.408ns, distribution 1.076ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC3[18]
                         net (fo=1, routed)           0.323     0.323    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_cm_over_vol/src_in
    SLICE_X111Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_cm_over_vol/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.484     1.631    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_cm_over_vol/dest_clk
    SLICE_X111Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc23_cm_over_vol/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[18]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_cm_over_vol/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.326ns  (logic 0.000ns (0.000%)  route 0.326ns (100.000%))
  Logic Levels:           0  
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.487ns (routing 0.408ns, distribution 1.079ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_ADC2[18]
                         net (fo=1, routed)           0.326     0.326    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_cm_over_vol/src_in
    SLICE_X112Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_cm_over_vol/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.487     1.634    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_cm_over_vol/dest_clk
    SLICE_X112Y182       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_irq_sync/sync_adc22_cm_over_vol/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC0_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.594ns  (logic 0.927ns (25.793%)  route 2.667ns (74.207%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.302ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.302ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.120ns (routing 0.606ns, distribution 1.514ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.487     0.487 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           1.937     2.424    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[13]
    SLICE_X103Y184       LUT5 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.152     2.576 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_42/O
                         net (fo=1, routed)           0.172     2.748    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_42_n_0
    SLICE_X101Y187       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.149     2.897 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15/O
                         net (fo=1, routed)           0.320     3.217    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15_n_0
    SLICE_X106Y191       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.089     3.306 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                         net (fo=1, routed)           0.188     3.494    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.050     3.544 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.050     3.594    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.120     2.302    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.524ns  (logic 0.771ns (21.879%)  route 2.753ns (78.121%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.285ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.285ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.103ns (routing 0.606ns, distribution 1.497ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.454     0.454 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           2.054     2.508    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[9]
    SLICE_X106Y184       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.157     2.665 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15/O
                         net (fo=1, routed)           0.210     2.875    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15_n_0
    SLICE_X106Y184       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     2.910 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4/O
                         net (fo=1, routed)           0.430     3.340    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.125     3.465 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.059     3.524    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.103     2.285    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.372ns  (logic 0.819ns (24.288%)  route 2.553ns (75.712%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.298ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.298ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.116ns (routing 0.606ns, distribution 1.510ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.543     0.543 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           1.893     2.436    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[14]
    SLICE_X105Y185       LUT5 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.089     2.525 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_14/O
                         net (fo=1, routed)           0.309     2.834    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_14_n_0
    SLICE_X101Y185       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.150     2.984 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.285     3.269    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.037     3.306 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.066     3.372    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.116     2.298    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.325ns  (logic 0.838ns (25.203%)  route 2.487ns (74.797%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.286ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.104ns (routing 0.606ns, distribution 1.498ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[12])
                                                      0.444     0.444 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           1.981     2.425    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[12]
    SLICE_X105Y184       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.149     2.574 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10/O
                         net (fo=1, routed)           0.146     2.720    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10_n_0
    SLICE_X105Y187       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.122     2.842 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.310     3.152    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X105Y199       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.123     3.275 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.050     3.325    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.104     2.286    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.144ns  (logic 0.862ns (27.417%)  route 2.282ns (72.583%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.295ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.295ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.113ns (routing 0.606ns, distribution 1.507ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.474     0.474 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           1.889     2.363    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[11]
    SLICE_X107Y185       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.145     2.508 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_11/O
                         net (fo=1, routed)           0.093     2.601    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_11_n_0
    SLICE_X106Y185       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.097     2.698 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.250     2.948    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.146     3.094 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.050     3.144    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.113     2.295    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.107ns  (logic 0.661ns (21.275%)  route 2.446ns (78.725%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.300ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.300ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.118ns (routing 0.606ns, distribution 1.512ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[15])
                                                      0.520     0.520 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           1.929     2.449    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[15]
    SLICE_X105Y184       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.051     2.500 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_16/O
                         net (fo=1, routed)           0.140     2.640    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_16_n_0
    SLICE_X104Y186       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.039     2.679 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4/O
                         net (fo=1, routed)           0.305     2.984    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.051     3.035 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.072     3.107    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.118     2.300    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.088ns  (logic 0.644ns (20.855%)  route 2.444ns (79.145%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.299ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.117ns (routing 0.606ns, distribution 1.511ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[10])
                                                      0.425     0.425 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           1.879     2.304    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[10]
    SLICE_X107Y187       LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.037     2.341 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_11/O
                         net (fo=1, routed)           0.154     2.495    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_11_n_0
    SLICE_X106Y187       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.036     2.531 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                         net (fo=1, routed)           0.362     2.893    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    SLICE_X106Y203       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.146     3.039 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     3.088    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.117     2.299    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.981ns  (logic 0.779ns (26.132%)  route 2.202ns (73.868%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.299ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.117ns (routing 0.606ns, distribution 1.511ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[8])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           1.758     2.171    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[8]
    SLICE_X106Y185       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.147     2.318 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_11/O
                         net (fo=1, routed)           0.092     2.410    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_11_n_0
    SLICE_X106Y186       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.123     2.533 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.302     2.835    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X106Y203       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     2.931 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.050     2.981    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.117     2.299    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.463ns  (logic 0.353ns (24.129%)  route 1.110ns (75.872%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[8])
                                                      0.204     0.204 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.886     1.090    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[8]
    SLICE_X106Y185       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.059     1.149 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_11/O
                         net (fo=1, routed)           0.051     1.200    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_11_n_0
    SLICE_X106Y186       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.050     1.250 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2/O
                         net (fo=1, routed)           0.156     1.406    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_2_n_0
    SLICE_X106Y203       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     1.446 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.017     1.463    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.516ns  (logic 0.292ns (19.261%)  route 1.224ns (80.739%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.613ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.613ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.466ns (routing 0.408ns, distribution 1.058ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[15])
                                                      0.232     0.232 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.968     1.200    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[15]
    SLICE_X105Y184       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.023     1.223 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_16/O
                         net (fo=1, routed)           0.073     1.296    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_16_n_0
    SLICE_X104Y186       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.015     1.311 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4/O
                         net (fo=1, routed)           0.157     1.468    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_4_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.022     1.490 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.026     1.516    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.466     1.613    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.529ns  (logic 0.299ns (19.555%)  route 1.230ns (80.445%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[10])
                                                      0.211     0.211 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.950     1.161    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[10]
    SLICE_X107Y187       LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.014     1.175 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_11/O
                         net (fo=1, routed)           0.077     1.252    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_11_n_0
    SLICE_X106Y187       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.015     1.267 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2/O
                         net (fo=1, routed)           0.187     1.454    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_2_n_0
    SLICE_X106Y203       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.059     1.513 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.529    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.529ns  (logic 0.378ns (24.722%)  route 1.151ns (75.278%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.602ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.602ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.455ns (routing 0.408ns, distribution 1.047ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.220     0.220 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.950     1.170    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[11]
    SLICE_X107Y185       LUT5 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.059     1.229 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_11/O
                         net (fo=1, routed)           0.049     1.278    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_11_n_0
    SLICE_X106Y185       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.040     1.318 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2/O
                         net (fo=1, routed)           0.135     1.453    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_2_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.059     1.512 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     1.529    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.455     1.602    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.606ns  (logic 0.359ns (22.354%)  route 1.247ns (77.646%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.608ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.608ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.461ns (routing 0.408ns, distribution 1.053ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.940     1.190    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[14]
    SLICE_X105Y185       LUT5 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.035     1.225 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_14/O
                         net (fo=1, routed)           0.135     1.360    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_14_n_0
    SLICE_X101Y185       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.060     1.420 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5/O
                         net (fo=1, routed)           0.148     1.568    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_5_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.014     1.582 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.024     1.606    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.461     1.608    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.626ns  (logic 0.370ns (22.755%)  route 1.256ns (77.245%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[12])
                                                      0.210     0.210 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           1.000     1.210    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[12]
    SLICE_X105Y184       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.060     1.270 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10/O
                         net (fo=1, routed)           0.076     1.346    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_10_n_0
    SLICE_X105Y187       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.050     1.396 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2/O
                         net (fo=1, routed)           0.163     1.559    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_2_n_0
    SLICE_X105Y199       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.050     1.609 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     1.626    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.700ns  (logic 0.342ns (20.118%)  route 1.358ns (79.882%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.221     0.221 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           1.006     1.227    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[9]
    SLICE_X106Y184       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.057     1.284 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15/O
                         net (fo=1, routed)           0.106     1.390    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_15_n_0
    SLICE_X106Y184       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.014     1.404 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4/O
                         net (fo=1, routed)           0.225     1.629    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_4_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.050     1.679 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.021     1.700    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC0_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.756ns  (logic 0.416ns (23.690%)  route 1.340ns (76.310%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.606ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.606ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.459ns (routing 0.408ns, distribution 1.051ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.238     0.238 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.973     1.211    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[13]
    SLICE_X103Y184       LUT5 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.061     1.272 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_42/O
                         net (fo=1, routed)           0.087     1.359    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_42_n_0
    SLICE_X101Y187       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.060     1.419 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15/O
                         net (fo=1, routed)           0.166     1.585    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_15_n_0
    SLICE_X106Y191       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     1.620 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3/O
                         net (fo=1, routed)           0.097     1.717    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_3_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.022     1.739 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.017     1.756    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.459     1.606    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC1_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.303ns  (logic 0.859ns (26.007%)  route 2.444ns (73.993%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.300ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.300ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.118ns (routing 0.606ns, distribution 1.512ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[15])
                                                      0.520     0.520 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           1.698     2.218    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[15]
    SLICE_X101Y195       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.051     2.269 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59/O
                         net (fo=1, routed)           0.196     2.465    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59_n_0
    SLICE_X101Y195       LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.099     2.564 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_20/O
                         net (fo=1, routed)           0.343     2.907    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_20_n_0
    SLICE_X105Y198       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.090     2.997 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.135     3.132    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.099     3.231 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.072     3.303    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.118     2.300    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.065ns  (logic 0.741ns (24.176%)  route 2.324ns (75.824%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.302ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.302ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.120ns (routing 0.606ns, distribution 1.514ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.487     0.487 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           1.828     2.315    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[13]
    SLICE_X103Y194       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.090     2.405 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_54/O
                         net (fo=1, routed)           0.144     2.549    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_54_n_0
    SLICE_X103Y195       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.039     2.588 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21/O
                         net (fo=1, routed)           0.219     2.807    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21_n_0
    SLICE_X106Y195       LUT5 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.090     2.897 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7/O
                         net (fo=1, routed)           0.083     2.980    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     3.015 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.050     3.065    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.120     2.302    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.059ns  (logic 0.767ns (25.074%)  route 2.292ns (74.926%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.299ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.117ns (routing 0.606ns, distribution 1.511ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[8])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           1.556     1.969    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[8]
    SLICE_X106Y196       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.123     2.092 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31/O
                         net (fo=1, routed)           0.227     2.319    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31_n_0
    SLICE_X104Y197       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.099     2.418 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_15/O
                         net (fo=1, routed)           0.227     2.645    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_15_n_0
    SLICE_X106Y197       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.097     2.742 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.232     2.974    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X106Y203       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.035     3.009 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.050     3.059    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.117     2.299    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.974ns  (logic 0.691ns (23.235%)  route 2.283ns (76.765%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.285ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.285ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.103ns (routing 0.606ns, distribution 1.497ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.454     0.454 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           1.329     1.783    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[9]
    SLICE_X110Y194       LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.100     1.883 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_44/O
                         net (fo=1, routed)           0.609     2.492    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_44_n_0
    SLICE_X105Y196       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.050     2.542 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_21/O
                         net (fo=1, routed)           0.089     2.631    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_21_n_0
    SLICE_X105Y196       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.050     2.681 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.197     2.878    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.037     2.915 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.059     2.974    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.103     2.285    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.952ns  (logic 0.897ns (30.386%)  route 2.055ns (69.614%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.295ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.295ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.113ns (routing 0.606ns, distribution 1.507ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.474     0.474 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           1.301     1.775    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[11]
    SLICE_X110Y197       LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.148     1.923 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35/O
                         net (fo=1, routed)           0.456     2.379    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35_n_0
    SLICE_X106Y197       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.090     2.469 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13/O
                         net (fo=1, routed)           0.045     2.514    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_n_0
    SLICE_X106Y197       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.097     2.611 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.203     2.814    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.088     2.902 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.050     2.952    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.113     2.295    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.826ns  (logic 0.714ns (25.265%)  route 2.112ns (74.735%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.299ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.117ns (routing 0.606ns, distribution 1.511ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[10])
                                                      0.425     0.425 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           1.411     1.836    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[10]
    SLICE_X111Y198       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.050     1.886 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26/O
                         net (fo=1, routed)           0.399     2.285    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26_n_0
    SLICE_X106Y198       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.051     2.336 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12/O
                         net (fo=1, routed)           0.037     2.373    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12_n_0
    SLICE_X106Y198       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.089     2.462 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.216     2.678    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X106Y203       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.099     2.777 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     2.826    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.117     2.299    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.738ns  (logic 0.668ns (24.397%)  route 2.070ns (75.603%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        2.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.286ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.104ns (routing 0.606ns, distribution 1.498ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[12])
                                                      0.444     0.444 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           1.414     1.858    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[12]
    SLICE_X110Y198       LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.039     1.897 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12/O
                         net (fo=1, routed)           0.454     2.351    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12_n_0
    SLICE_X105Y198       LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.089     2.440 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                         net (fo=1, routed)           0.152     2.592    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    SLICE_X105Y199       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.096     2.688 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.050     2.738    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.104     2.286    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.660ns  (logic 0.824ns (30.977%)  route 1.836ns (69.023%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.298ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.298ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.116ns (routing 0.606ns, distribution 1.510ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.543     0.543 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           1.478     2.021    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[14]
    SLICE_X104Y195       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.052     2.073 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_52/O
                         net (fo=1, routed)           0.096     2.169    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_52_n_0
    SLICE_X104Y195       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.088     2.257 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20/O
                         net (fo=1, routed)           0.040     2.297    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20_n_0
    SLICE_X104Y195       LUT6 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.090     2.387 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.156     2.543    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.051     2.594 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.066     2.660    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.116     2.298    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.277ns  (logic 0.364ns (28.504%)  route 0.913ns (71.496%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.608ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.608ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.461ns (routing 0.408ns, distribution 1.053ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.743     0.993    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[14]
    SLICE_X104Y195       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.022     1.015 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_52/O
                         net (fo=1, routed)           0.045     1.060    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_52_n_0
    SLICE_X104Y195       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.035     1.095 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20/O
                         net (fo=1, routed)           0.022     1.117    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_20_n_0
    SLICE_X104Y195       LUT6 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.035     1.152 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.079     1.231    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.022     1.253 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.024     1.277    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.461     1.608    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.318ns  (logic 0.300ns (22.762%)  route 1.018ns (77.238%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[12])
                                                      0.210     0.210 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.698     0.908    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[12]
    SLICE_X110Y198       LUT5 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.015     0.923 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12/O
                         net (fo=1, routed)           0.226     1.149    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_12_n_0
    SLICE_X105Y198       LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     1.184 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4/O
                         net (fo=1, routed)           0.077     1.261    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_4_n_0
    SLICE_X105Y199       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.040     1.301 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     1.318    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.361ns  (logic 0.332ns (24.394%)  route 1.029ns (75.606%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[10])
                                                      0.211     0.211 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.672     0.883    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[10]
    SLICE_X111Y198       LUT5 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.022     0.905 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26/O
                         net (fo=1, routed)           0.208     1.113    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_26_n_0
    SLICE_X106Y198       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.023     1.136 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12/O
                         net (fo=1, routed)           0.021     1.157    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_12_n_0
    SLICE_X106Y198       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     1.192 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.112     1.304    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X106Y203       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.041     1.345 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.361    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.400ns  (logic 0.390ns (27.857%)  route 1.010ns (72.143%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.602ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.602ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.455ns (routing 0.408ns, distribution 1.047ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.220     0.220 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.645     0.865    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[11]
    SLICE_X110Y197       LUT5 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.059     0.924 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35/O
                         net (fo=1, routed)           0.219     1.143    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_35_n_0
    SLICE_X106Y197       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.036     1.179 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13/O
                         net (fo=1, routed)           0.025     1.204    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_13_n_0
    SLICE_X106Y197       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.040     1.244 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.104     1.348    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.035     1.383 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     1.400    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.455     1.602    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.437ns  (logic 0.320ns (22.269%)  route 1.117ns (77.731%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.221     0.221 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.653     0.874    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[9]
    SLICE_X110Y194       LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.041     0.915 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_44/O
                         net (fo=1, routed)           0.298     1.213    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_44_n_0
    SLICE_X105Y196       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.022     1.235 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_21/O
                         net (fo=1, routed)           0.043     1.278    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_21_n_0
    SLICE_X105Y196       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.022     1.300 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.102     1.402    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.014     1.416 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.021     1.437    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.478ns  (logic 0.349ns (23.613%)  route 1.129ns (76.387%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[8])
                                                      0.204     0.204 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.759     0.963    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[8]
    SLICE_X106Y196       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.050     1.013 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31/O
                         net (fo=1, routed)           0.117     1.130    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_31_n_0
    SLICE_X104Y197       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.041     1.171 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_15/O
                         net (fo=1, routed)           0.117     1.288    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_15_n_0
    SLICE_X106Y197       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.040     1.328 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.119     1.447    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X106Y203       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.014     1.461 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.017     1.478    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.491ns  (logic 0.337ns (22.602%)  route 1.154ns (77.398%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.606ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.606ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.459ns (routing 0.408ns, distribution 1.051ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.238     0.238 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.905     1.143    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[13]
    SLICE_X103Y194       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.035     1.178 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_54/O
                         net (fo=1, routed)           0.072     1.250    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_54_n_0
    SLICE_X103Y195       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.015     1.265 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21/O
                         net (fo=1, routed)           0.113     1.378    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_21_n_0
    SLICE_X106Y195       LUT5 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.035     1.413 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7/O
                         net (fo=1, routed)           0.047     1.460    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_7_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.014     1.474 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.017     1.491    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.459     1.606    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC1_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.591ns  (logic 0.372ns (23.382%)  route 1.219ns (76.618%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.613ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.613ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.466ns (routing 0.408ns, distribution 1.058ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y1           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y1           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[15])
                                                      0.232     0.232 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.849     1.081    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_1[15]
    SLICE_X101Y195       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.023     1.104 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59/O
                         net (fo=1, routed)           0.095     1.199    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_59_n_0
    SLICE_X101Y195       LUT5 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.041     1.240 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_20/O
                         net (fo=1, routed)           0.178     1.418    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_20_n_0
    SLICE_X105Y198       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.035     1.453 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.071     1.524    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.041     1.565 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.026     1.591    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.466     1.613    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC2_CLK
  To Clock:  clk_pl_0

Max Delay           144 Endpoints
Min Delay           144 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.885ns  (logic 0.107ns (3.709%)  route 2.778ns (96.291%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.291ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.339ns
    Source Clock Delay      (SCD):    2.630ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.104ns (routing 0.888ns, distribution 1.216ns)
  Clock Net Delay (Destination): 2.157ns (routing 0.606ns, distribution 1.551ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.104     2.630    d_1_i/rst_adc2/U0/slowest_sync_clk
    SLICE_X65Y231        FDRE                                         r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y231        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.709 r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.364     4.073    d_1_i/rst_adc2/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y110        BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.101 r  d_1_i/rst_adc2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=3340, routed)        1.414     5.515    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/src_in
    SLICE_X112Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.157     2.339    d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/dest_clk
    SLICE_X112Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_adc2_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.596ns  (logic 0.649ns (25.000%)  route 1.947ns (75.000%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        -0.617ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.279ns
    Source Clock Delay      (SCD):    2.896ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.370ns (routing 0.888ns, distribution 1.482ns)
  Clock Net Delay (Destination): 2.097ns (routing 0.606ns, distribution 1.491ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.370     2.896    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/m2_axis_aclk
    RFADC_X0Y2           RFADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/FABRIC_CLK
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_FABRIC_CLK_STATUS_COMMON[5])
                                                      0.338     3.234 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[5]
                         net (fo=1, routed)           0.797     4.031    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[5]
    SLICE_X112Y197       LUT6 (Prop_E6LUT_SLICEM_I1_O)
                                                      0.124     4.155 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_42/O
                         net (fo=1, routed)           0.418     4.573    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_42_n_0
    SLICE_X107Y196       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.051     4.624 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_19/O
                         net (fo=1, routed)           0.415     5.039    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_19_n_0
    SLICE_X105Y203       LUT6 (Prop_E6LUT_SLICEL_I3_O)
                                                      0.099     5.138 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_5/O
                         net (fo=1, routed)           0.245     5.383    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_5_n_0
    SLICE_X103Y207       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.037     5.420 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[5]_i_1/O
                         net (fo=1, routed)           0.072     5.492    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_79
    SLICE_X103Y207       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.097     2.279    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y207       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.324ns  (logic 0.081ns (25.000%)  route 0.243ns (75.000%))
  Logic Levels:           0  
  Clock Path Skew:        -0.536ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.236ns
    Source Clock Delay      (SCD):    2.772ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.246ns (routing 0.888ns, distribution 1.358ns)
  Clock Net Delay (Destination): 2.054ns (routing 0.606ns, distribution 1.448ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.246     2.772    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X91Y130        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y130        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     2.853 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.243     3.096    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X91Y130        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.054     2.236    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X91Y130        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.350ns  (logic 0.081ns (23.140%)  route 0.269ns (76.860%))
  Logic Levels:           0  
  Clock Path Skew:        -0.665ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.020ns
    Source Clock Delay      (SCD):    2.685ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.159ns (routing 0.888ns, distribution 1.271ns)
  Clock Net Delay (Destination): 1.838ns (routing 0.606ns, distribution 1.232ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.159     2.685    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X52Y78         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y78         FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.081     2.766 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.269     3.035    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X49Y77         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.838     2.020    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X49Y77         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.917ns  (logic 1.039ns (35.619%)  route 1.878ns (64.381%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        2.298ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.298ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.116ns (routing 0.606ns, distribution 1.510ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.543     0.543 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.922     1.465    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[14]
    SLICE_X111Y196       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.148     1.613 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_75/O
                         net (fo=1, routed)           0.040     1.653    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_75_n_0
    SLICE_X111Y196       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     1.703 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_48/O
                         net (fo=1, routed)           0.218     1.921    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_48_n_0
    SLICE_X108Y196       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.097     2.018 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/O
                         net (fo=1, routed)           0.476     2.494    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19_n_0
    SLICE_X104Y195       LUT6 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.150     2.644 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.156     2.800    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.051     2.851 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.066     2.917    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.116     2.298    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.680ns  (logic 0.983ns (36.679%)  route 1.697ns (63.321%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.302ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.302ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.120ns (routing 0.606ns, distribution 1.514ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.487     0.487 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.852     1.339    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[13]
    SLICE_X109Y197       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.125     1.464 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_47/O
                         net (fo=1, routed)           0.146     1.610    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_47_n_0
    SLICE_X108Y197       LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.124     1.734 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17/O
                         net (fo=1, routed)           0.476     2.210    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17_n_0
    SLICE_X107Y194       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.101     2.311 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/O
                         net (fo=1, routed)           0.173     2.484    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.146     2.630 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.050     2.680    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.120     2.302    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.603ns  (logic 0.783ns (30.081%)  route 1.820ns (69.919%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.300ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.300ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.118ns (routing 0.606ns, distribution 1.512ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[15])
                                                      0.520     0.520 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.910     1.430    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[15]
    SLICE_X110Y196       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.039     1.469 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_63/O
                         net (fo=1, routed)           0.221     1.690    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_63_n_0
    SLICE_X108Y196       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.089     1.779 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22/O
                         net (fo=1, routed)           0.482     2.261    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_n_0
    SLICE_X105Y198       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.036     2.297 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.135     2.432    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.099     2.531 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.072     2.603    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.118     2.300    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.576ns  (logic 0.794ns (30.823%)  route 1.782ns (69.177%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.299ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.117ns (routing 0.606ns, distribution 1.511ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[10])
                                                      0.425     0.425 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.819     1.244    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[10]
    SLICE_X112Y198       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.090     1.334 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29/O
                         net (fo=1, routed)           0.533     1.867    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29_n_0
    SLICE_X107Y198       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.145     2.012 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13/O
                         net (fo=1, routed)           0.165     2.177    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13_n_0
    SLICE_X106Y198       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.035     2.212 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.216     2.428    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X106Y203       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.099     2.527 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     2.576    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.117     2.299    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.365ns  (logic 0.689ns (29.133%)  route 1.676ns (70.867%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.295ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.295ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.113ns (routing 0.606ns, distribution 1.507ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.474     0.474 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.917     1.391    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[11]
    SLICE_X112Y197       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.039     1.430 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31/O
                         net (fo=1, routed)           0.414     1.844    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31_n_0
    SLICE_X107Y197       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.053     1.897 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_12/O
                         net (fo=1, routed)           0.092     1.989    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_12_n_0
    SLICE_X106Y197       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     2.024 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.203     2.227    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.088     2.315 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.050     2.365    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.113     2.295    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.361ns  (logic 0.701ns (29.691%)  route 1.660ns (70.309%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.285ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.285ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.103ns (routing 0.606ns, distribution 1.497ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.454     0.454 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.826     1.280    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[9]
    SLICE_X110Y197       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.123     1.403 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_41/O
                         net (fo=1, routed)           0.347     1.750    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_41_n_0
    SLICE_X107Y197       LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.052     1.802 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/O
                         net (fo=1, routed)           0.231     2.033    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20_n_0
    SLICE_X105Y196       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.035     2.068 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.197     2.265    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.037     2.302 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.059     2.361    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.103     2.285    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.999ns  (logic 0.329ns (32.933%)  route 0.670ns (67.067%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[12])
                                                      0.210     0.210 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.480     0.690    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[12]
    SLICE_X107Y199       LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.035     0.725 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_32/O
                         net (fo=1, routed)           0.023     0.748    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_32_n_0
    SLICE_X107Y199       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.035     0.783 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_11/O
                         net (fo=1, routed)           0.024     0.807    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_11_n_0
    SLICE_X107Y199       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.014     0.821 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3/O
                         net (fo=1, routed)           0.126     0.947    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_3_n_0
    SLICE_X105Y199       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.035     0.982 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     0.999    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.094ns  (logic 0.272ns (24.863%)  route 0.822ns (75.137%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[8])
                                                      0.204     0.204 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.494     0.698    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[8]
    SLICE_X109Y197       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.040     0.738 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13/O
                         net (fo=1, routed)           0.192     0.930    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_13_n_0
    SLICE_X106Y197       LUT6 (Prop_F6LUT_SLICEL_I3_O)
                                                      0.014     0.944 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3/O
                         net (fo=1, routed)           0.119     1.063    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_3_n_0
    SLICE_X106Y203       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.014     1.077 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.017     1.094    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.123ns  (logic 0.307ns (27.337%)  route 0.816ns (72.663%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.602ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.602ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.455ns (routing 0.408ns, distribution 1.047ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.220     0.220 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.429     0.649    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[11]
    SLICE_X112Y197       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.015     0.664 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31/O
                         net (fo=1, routed)           0.218     0.882    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_31_n_0
    SLICE_X107Y197       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.023     0.905 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_12/O
                         net (fo=1, routed)           0.048     0.953    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_12_n_0
    SLICE_X106Y197       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.014     0.967 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3/O
                         net (fo=1, routed)           0.104     1.071    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_3_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.035     1.106 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     1.123    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.455     1.602    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.142ns  (logic 0.321ns (28.109%)  route 0.821ns (71.891%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.221     0.221 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.402     0.623    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[9]
    SLICE_X110Y197       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.050     0.673 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_41/O
                         net (fo=1, routed)           0.179     0.852    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_41_n_0
    SLICE_X107Y197       LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.022     0.874 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20/O
                         net (fo=1, routed)           0.117     0.991    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_20_n_0
    SLICE_X105Y196       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.014     1.005 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5/O
                         net (fo=1, routed)           0.102     1.107    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_5_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.014     1.121 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.021     1.142    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.234ns  (logic 0.338ns (27.391%)  route 0.896ns (72.609%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.613ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.613ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.466ns (routing 0.408ns, distribution 1.058ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[15])
                                                      0.232     0.232 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.449     0.681    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[15]
    SLICE_X110Y196       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.015     0.696 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_63/O
                         net (fo=1, routed)           0.111     0.807    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_63_n_0
    SLICE_X108Y196       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.035     0.842 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22/O
                         net (fo=1, routed)           0.239     1.081    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_22_n_0
    SLICE_X105Y198       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.015     1.096 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5/O
                         net (fo=1, routed)           0.071     1.167    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_5_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.041     1.208 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.026     1.234    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.466     1.613    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.237ns  (logic 0.360ns (29.103%)  route 0.877ns (70.897%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[10])
                                                      0.211     0.211 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.397     0.608    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[10]
    SLICE_X112Y198       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.035     0.643 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29/O
                         net (fo=1, routed)           0.269     0.912    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_29_n_0
    SLICE_X107Y198       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.059     0.971 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13/O
                         net (fo=1, routed)           0.083     1.054    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_13_n_0
    SLICE_X106Y198       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.014     1.068 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3/O
                         net (fo=1, routed)           0.112     1.180    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_3_n_0
    SLICE_X106Y203       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.041     1.221 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.237    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.278ns  (logic 0.439ns (34.351%)  route 0.839ns (65.649%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.606ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.606ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.459ns (routing 0.408ns, distribution 1.051ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.238     0.238 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.419     0.657    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[13]
    SLICE_X109Y197       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.051     0.708 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_47/O
                         net (fo=1, routed)           0.072     0.780    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_47_n_0
    SLICE_X108Y197       LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.050     0.830 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17/O
                         net (fo=1, routed)           0.243     1.073    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_17_n_0
    SLICE_X107Y194       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.041     1.114 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4/O
                         net (fo=1, routed)           0.088     1.202    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_4_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.059     1.261 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.017     1.278    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.459     1.606    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.362ns  (logic 0.453ns (33.260%)  route 0.909ns (66.740%))
  Logic Levels:           5  (LUT6=5)
  Clock Path Skew:        1.608ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.608ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.461ns (routing 0.408ns, distribution 1.053ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.448     0.698    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[14]
    SLICE_X111Y196       LUT6 (Prop_F6LUT_SLICEL_I1_O)
                                                      0.059     0.757 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_75/O
                         net (fo=1, routed)           0.022     0.779    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_75_n_0
    SLICE_X111Y196       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.022     0.801 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_48/O
                         net (fo=1, routed)           0.107     0.908    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_48_n_0
    SLICE_X108Y196       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.040     0.948 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19/O
                         net (fo=1, routed)           0.229     1.177    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_19_n_0
    SLICE_X104Y195       LUT6 (Prop_A6LUT_SLICEM_I2_O)
                                                      0.060     1.237 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.079     1.316    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.022     1.338 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.024     1.362    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.461     1.608    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.040ns (33.333%)  route 0.080ns (66.667%))
  Logic Levels:           0  
  Clock Path Skew:        0.077ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.565ns
    Source Clock Delay      (SCD):    1.488ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.226ns (routing 0.485ns, distribution 0.741ns)
  Clock Net Delay (Destination): 1.418ns (routing 0.408ns, distribution 1.010ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.226     1.488    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X91Y130        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y130        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.528 r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.080     1.608    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X91Y130        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.418     1.565    d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X91Y130        FDRE                                         r  d_1_i/axis_switch_mr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.158ns  (logic 0.040ns (25.367%)  route 0.118ns (74.633%))
  Logic Levels:           0  
  Clock Path Skew:        -0.019ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.433ns
    Source Clock Delay      (SCD):    1.453ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.191ns (routing 0.485ns, distribution 0.706ns)
  Clock Net Delay (Destination): 1.286ns (routing 0.408ns, distribution 0.878ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.191     1.453    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_clk
    SLICE_X52Y78         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y78         FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.493 r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/dest_req_ff_reg/Q
                         net (fo=2, routed)           0.118     1.610    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/src_in
    SLICE_X49Y77         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.286     1.433    d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/dest_clk
    SLICE_X49Y77         FDRE                                         r  d_1_i/axis_switch_ddr/inst/gen_static_router.gen_synch.inst_cdc_handshake/inst_xpm_cdc_handshake/xpm_cdc_single_dest2src_inst/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC3_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.233ns  (logic 0.900ns (27.838%)  route 2.333ns (72.162%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.300ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.300ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.118ns (routing 0.606ns, distribution 1.512ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[15])
                                                      0.520     0.520 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.834     1.354    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[15]
    SLICE_X105Y206       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.090     1.444 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_68/O
                         net (fo=1, routed)           0.335     1.779    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_68_n_0
    SLICE_X103Y203       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.152     1.931 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_24/O
                         net (fo=1, routed)           0.641     2.572    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_24_n_0
    SLICE_X108Y202       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.050     2.622 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/O
                         net (fo=1, routed)           0.451     3.073    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.088     3.161 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.072     3.233    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.118     2.300    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.775ns  (logic 0.677ns (24.396%)  route 2.098ns (75.604%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.299ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.117ns (routing 0.606ns, distribution 1.511ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[8])
                                                      0.413     0.413 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.795     1.208    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[8]
    SLICE_X105Y206       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.066     1.274 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_35/O
                         net (fo=1, routed)           0.154     1.428    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_35_n_0
    SLICE_X104Y205       LUT4 (Prop_D5LUT_SLICEM_I2_O)
                                                      0.097     1.525 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/O
                         net (fo=1, routed)           0.657     2.182    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16_n_0
    SLICE_X110Y203       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.051     2.233 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/O
                         net (fo=1, routed)           0.442     2.675    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4_n_0
    SLICE_X106Y203       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.050     2.725 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.050     2.775    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.117     2.299    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.397ns  (logic 0.824ns (34.376%)  route 1.573ns (65.624%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.302ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.302ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.120ns (routing 0.606ns, distribution 1.514ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.487     0.487 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.844     1.331    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[13]
    SLICE_X107Y202       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.090     1.421 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_49/O
                         net (fo=1, routed)           0.289     1.710    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_49_n_0
    SLICE_X105Y204       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.124     1.834 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_20/O
                         net (fo=1, routed)           0.176     2.010    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_20_n_0
    SLICE_X106Y203       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.035     2.045 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.214     2.259    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.088     2.347 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.050     2.397    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.120     2.302    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.390ns  (logic 0.846ns (35.397%)  route 1.544ns (64.603%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.298ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.298ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.116ns (routing 0.606ns, distribution 1.510ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.543     0.543 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.743     1.286    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[14]
    SLICE_X106Y206       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.146     1.432 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_42/O
                         net (fo=1, routed)           0.347     1.779    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_42_n_0
    SLICE_X104Y201       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.053     1.832 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_18/O
                         net (fo=1, routed)           0.232     2.064    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_18_n_0
    SLICE_X104Y195       LUT6 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.053     2.117 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.156     2.273    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.051     2.324 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.066     2.390    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.116     2.298    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.255ns  (logic 0.811ns (35.965%)  route 1.444ns (64.035%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        2.295ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.295ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.113ns (routing 0.606ns, distribution 1.507ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.474     0.474 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.687     1.161    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[11]
    SLICE_X108Y202       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.089     1.250 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39/O
                         net (fo=1, routed)           0.046     1.296    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39_n_0
    SLICE_X108Y202       LUT4 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.099     1.395 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_14/O
                         net (fo=1, routed)           0.205     1.600    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_14_n_0
    SLICE_X110Y202       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.053     1.653 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/O
                         net (fo=1, routed)           0.456     2.109    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.096     2.205 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.050     2.255    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.113     2.295    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.193ns  (logic 0.793ns (36.161%)  route 1.400ns (63.839%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.299ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.117ns (routing 0.606ns, distribution 1.511ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[10])
                                                      0.425     0.425 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.696     1.121    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[10]
    SLICE_X109Y203       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.098     1.219 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_33/O
                         net (fo=1, routed)           0.039     1.258    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_33_n_0
    SLICE_X109Y203       LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.089     1.347 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_14/O
                         net (fo=1, routed)           0.113     1.460    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_14_n_0
    SLICE_X110Y203       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.145     1.605 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.503     2.108    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X106Y203       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.036     2.144 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     2.193    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.117     2.299    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.053ns  (logic 0.680ns (33.122%)  route 1.373ns (66.878%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.285ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.285ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.103ns (routing 0.606ns, distribution 1.497ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.454     0.454 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.853     1.307    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[9]
    SLICE_X107Y203       LUT5 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.038     1.345 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_22/O
                         net (fo=1, routed)           0.224     1.569    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_22_n_0
    SLICE_X103Y203       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.088     1.657 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.237     1.894    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.100     1.994 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.059     2.053    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.103     2.285    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.849ns  (logic 0.580ns (31.368%)  route 1.269ns (68.632%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.286ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.104ns (routing 0.606ns, distribution 1.498ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[12])
                                                      0.444     0.444 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.862     1.306    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[12]
    SLICE_X105Y206       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.035     1.341 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/O
                         net (fo=1, routed)           0.206     1.547    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18_n_0
    SLICE_X105Y201       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.051     1.598 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.151     1.749    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X105Y199       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.050     1.799 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.050     1.849    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.104     2.286    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.861ns  (logic 0.269ns (31.243%)  route 0.592ns (68.757%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[12])
                                                      0.210     0.210 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[12]
                         net (fo=1, routed)           0.395     0.605    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[12]
    SLICE_X105Y206       LUT5 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.014     0.619 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18/O
                         net (fo=1, routed)           0.105     0.724    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_18_n_0
    SLICE_X105Y201       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.023     0.747 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5/O
                         net (fo=1, routed)           0.075     0.822    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_5_n_0
    SLICE_X105Y199       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.022     0.844 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     0.861    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.969ns  (logic 0.311ns (32.095%)  route 0.658ns (67.905%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[9])
                                                      0.221     0.221 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[9]
                         net (fo=1, routed)           0.400     0.621    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[9]
    SLICE_X107Y203       LUT5 (Prop_A6LUT_SLICEM_I4_O)
                                                      0.014     0.635 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_22/O
                         net (fo=1, routed)           0.117     0.752    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_22_n_0
    SLICE_X103Y203       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.035     0.787 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6/O
                         net (fo=1, routed)           0.120     0.907    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_6_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.041     0.948 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.021     0.969    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.045ns  (logic 0.359ns (34.354%)  route 0.686ns (65.646%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        1.602ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.602ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.455ns (routing 0.408ns, distribution 1.047ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[11])
                                                      0.220     0.220 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[11]
                         net (fo=1, routed)           0.322     0.542    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[11]
    SLICE_X108Y202       LUT5 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     0.577 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39/O
                         net (fo=1, routed)           0.025     0.602    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_39_n_0
    SLICE_X108Y202       LUT4 (Prop_E6LUT_SLICEL_I2_O)
                                                      0.041     0.643 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_14/O
                         net (fo=1, routed)           0.102     0.745    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_14_n_0
    SLICE_X110Y202       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.023     0.768 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4/O
                         net (fo=1, routed)           0.220     0.988    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_4_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.040     1.028 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     1.045    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.455     1.602    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.047ns  (logic 0.359ns (34.288%)  route 0.688ns (65.712%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[10])
                                                      0.211     0.211 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[10]
                         net (fo=1, routed)           0.332     0.543    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[10]
    SLICE_X109Y203       LUT5 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.040     0.583 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_33/O
                         net (fo=1, routed)           0.022     0.605    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_33_n_0
    SLICE_X109Y203       LUT4 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.035     0.640 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_14/O
                         net (fo=1, routed)           0.060     0.700    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_14_n_0
    SLICE_X110Y203       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.059     0.759 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4/O
                         net (fo=1, routed)           0.258     1.017    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_4_n_0
    SLICE_X106Y203       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.014     1.031 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.047    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.121ns  (logic 0.377ns (33.631%)  route 0.744ns (66.369%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.608ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.608ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.461ns (routing 0.408ns, distribution 1.053ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[14])
                                                      0.250     0.250 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[14]
                         net (fo=1, routed)           0.347     0.597    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[14]
    SLICE_X106Y206       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.059     0.656 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_42/O
                         net (fo=1, routed)           0.178     0.834    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_42_n_0
    SLICE_X104Y201       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.023     0.857 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_18/O
                         net (fo=1, routed)           0.116     0.973    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_18_n_0
    SLICE_X104Y195       LUT6 (Prop_A6LUT_SLICEM_I1_O)
                                                      0.023     0.996 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6/O
                         net (fo=1, routed)           0.079     1.075    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_6_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.022     1.097 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.024     1.121    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.461     1.608    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.139ns  (logic 0.372ns (32.660%)  route 0.767ns (67.340%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.606ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.606ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.459ns (routing 0.408ns, distribution 1.051ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[13])
                                                      0.238     0.238 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[13]
                         net (fo=1, routed)           0.396     0.634    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[13]
    SLICE_X107Y202       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.035     0.669 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_49/O
                         net (fo=1, routed)           0.148     0.817    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_49_n_0
    SLICE_X105Y204       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.050     0.867 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_20/O
                         net (fo=1, routed)           0.093     0.960    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_20_n_0
    SLICE_X106Y203       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.014     0.974 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5/O
                         net (fo=1, routed)           0.113     1.087    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_5_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.035     1.122 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.017     1.139    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.459     1.606    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.339ns  (logic 0.305ns (22.778%)  route 1.034ns (77.222%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[8])
                                                      0.204     0.204 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[8]
                         net (fo=1, routed)           0.389     0.593    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[8]
    SLICE_X105Y206       LUT5 (Prop_D5LUT_SLICEL_I4_O)
                                                      0.020     0.613 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_35/O
                         net (fo=1, routed)           0.084     0.697    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_35_n_0
    SLICE_X104Y205       LUT4 (Prop_D5LUT_SLICEM_I2_O)
                                                      0.037     0.734 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16/O
                         net (fo=1, routed)           0.317     1.051    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_16_n_0
    SLICE_X110Y203       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.022     1.073 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4/O
                         net (fo=1, routed)           0.227     1.300    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_4_n_0
    SLICE_X106Y203       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.022     1.322 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.017     1.339    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
                            (rising edge-triggered cell RFADC clocked by RFADC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.512ns  (logic 0.385ns (25.463%)  route 1.127ns (74.537%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.613ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.613ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.466ns (routing 0.408ns, distribution 1.058ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/INTERNAL_FBRC_DIV1_MUX
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_STATUS_COMMON[15])
                                                      0.232     0.232 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[15]
                         net (fo=1, routed)           0.391     0.623    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[15]
    SLICE_X105Y206       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.035     0.658 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_68/O
                         net (fo=1, routed)           0.166     0.824    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_68_n_0
    SLICE_X103Y203       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.061     0.885 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_24/O
                         net (fo=1, routed)           0.323     1.208    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_24_n_0
    SLICE_X108Y202       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.022     1.230 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6/O
                         net (fo=1, routed)           0.221     1.451    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_6_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I4_O)
                                                      0.035     1.486 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.026     1.512    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.466     1.613    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC0_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.757ns  (logic 1.411ns (37.557%)  route 2.346ns (62.443%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.302ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.302ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.120ns (routing 0.606ns, distribution 1.514ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.920     0.920 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.203     2.123    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][13]
    SLICE_X103Y211       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.123     2.246 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37/O
                         net (fo=1, routed)           0.250     2.496    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37_n_0
    SLICE_X104Y209       LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.148     2.644 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12/O
                         net (fo=1, routed)           0.418     3.062    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12_n_0
    SLICE_X106Y218       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.124     3.186 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.425     3.611    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.707 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.050     3.757    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.120     2.302    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.521ns  (logic 1.290ns (36.637%)  route 2.231ns (63.363%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        2.298ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.298ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.116ns (routing 0.606ns, distribution 1.510ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.831     0.831 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.373     2.204    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][14]
    SLICE_X103Y213       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.123     2.327 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_54/O
                         net (fo=1, routed)           0.157     2.484    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_54_n_0
    SLICE_X102Y211       LUT5 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.124     2.608 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_22/O
                         net (fo=1, routed)           0.187     2.795    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_22_n_0
    SLICE_X103Y211       LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.037     2.832 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8/O
                         net (fo=1, routed)           0.196     3.028    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8_n_0
    SLICE_X104Y207       LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.052     3.080 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.252     3.332    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.123     3.455 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.066     3.521    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.116     2.298    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.426ns  (logic 1.232ns (35.960%)  route 2.194ns (64.040%))
  Logic Levels:           6  (LUT6=6)
  Clock Path Skew:        2.300ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.300ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.118ns (routing 0.606ns, distribution 1.512ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.816     0.816 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.298     2.114    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][15]
    SLICE_X103Y213       LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.037     2.151 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_99/O
                         net (fo=1, routed)           0.170     2.321    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_99_n_0
    SLICE_X102Y212       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.035     2.356 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_71/O
                         net (fo=1, routed)           0.086     2.442    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_71_n_0
    SLICE_X102Y212       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     2.477 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_34/O
                         net (fo=1, routed)           0.142     2.619    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_34_n_0
    SLICE_X101Y212       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.089     2.708 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10/O
                         net (fo=1, routed)           0.260     2.968    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10_n_0
    SLICE_X104Y207       LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.098     3.066 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.166     3.232    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.122     3.354 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.072     3.426    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.118     2.300    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.144ns  (logic 1.188ns (37.786%)  route 1.956ns (62.214%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.286ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.104ns (routing 0.606ns, distribution 1.498ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.853     0.853 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.221     2.074    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][12]
    SLICE_X103Y211       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.152     2.226 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_22/O
                         net (fo=1, routed)           0.239     2.465    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_22_n_0
    SLICE_X104Y209       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.037     2.502 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/O
                         net (fo=1, routed)           0.446     2.948    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6_n_0
    SLICE_X105Y199       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.146     3.094 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.050     3.144    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.104     2.286    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.949ns  (logic 1.194ns (40.488%)  route 1.755ns (59.512%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.295ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.295ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.113ns (routing 0.606ns, distribution 1.507ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.857     0.857 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.251     2.108    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][11]
    SLICE_X105Y210       LUT5 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.124     2.232 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19/O
                         net (fo=1, routed)           0.163     2.395    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19_n_0
    SLICE_X105Y208       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.090     2.485 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.291     2.776    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.123     2.899 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.050     2.949    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.113     2.295    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.911ns  (logic 1.127ns (38.715%)  route 1.784ns (61.285%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.299ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.117ns (routing 0.606ns, distribution 1.511ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.841     0.841 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.124     1.965    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][8]
    SLICE_X103Y210       LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.051     2.016 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19/O
                         net (fo=1, routed)           0.271     2.287    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19_n_0
    SLICE_X102Y207       LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.089     2.376 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.339     2.715    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X106Y203       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.146     2.861 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.050     2.911    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.117     2.299    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.852ns  (logic 1.117ns (39.166%)  route 1.735ns (60.835%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.285ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.285ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.103ns (routing 0.606ns, distribution 1.497ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.794     0.794 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.265     2.059    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][9]
    SLICE_X103Y209       LUT6 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.148     2.207 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_7/O
                         net (fo=1, routed)           0.159     2.366    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_7_n_0
    SLICE_X103Y208       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.123     2.489 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.252     2.741    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.052     2.793 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.059     2.852    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.103     2.285    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.587ns  (logic 1.028ns (39.737%)  route 1.559ns (60.263%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.299ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.117ns (routing 0.606ns, distribution 1.511ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.184     1.963    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][10]
    SLICE_X105Y208       LUT5 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.124     2.087 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18/O
                         net (fo=1, routed)           0.090     2.177    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18_n_0
    SLICE_X105Y208       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.036     2.213 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.236     2.449    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X106Y203       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.089     2.538 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     2.587    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.117     2.299    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.251ns  (logic 0.481ns (38.449%)  route 0.770ns (61.551%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           0.586     0.968    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][10]
    SLICE_X105Y208       LUT5 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.050     1.018 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18/O
                         net (fo=1, routed)           0.044     1.062    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_18_n_0
    SLICE_X105Y208       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.014     1.076 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5/O
                         net (fo=1, routed)           0.124     1.200    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_5_n_0
    SLICE_X106Y203       LUT6 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.035     1.235 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.251    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.397ns  (logic 0.530ns (37.938%)  route 0.867ns (62.062%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.399     0.399 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           0.633     1.032    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][9]
    SLICE_X103Y209       LUT6 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.059     1.091 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_7/O
                         net (fo=1, routed)           0.080     1.171    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_7_n_0
    SLICE_X103Y208       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.050     1.221 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2/O
                         net (fo=1, routed)           0.133     1.354    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_2_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.022     1.376 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.021     1.397    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.409ns  (logic 0.519ns (36.835%)  route 0.890ns (63.165%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.403     0.403 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           0.564     0.967    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][8]
    SLICE_X103Y210       LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.022     0.989 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19/O
                         net (fo=1, routed)           0.137     1.126    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_19_n_0
    SLICE_X102Y207       LUT4 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.035     1.161 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5/O
                         net (fo=1, routed)           0.172     1.333    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_5_n_0
    SLICE_X106Y203       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.059     1.392 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.017     1.409    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.430ns  (logic 0.552ns (38.601%)  route 0.878ns (61.399%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Path Skew:        1.602ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.602ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.455ns (routing 0.408ns, distribution 1.047ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           0.628     1.045    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][11]
    SLICE_X105Y210       LUT5 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.050     1.095 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19/O
                         net (fo=1, routed)           0.081     1.176    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_19_n_0
    SLICE_X105Y208       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.035     1.211 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5/O
                         net (fo=1, routed)           0.152     1.363    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_5_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.050     1.413 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     1.430    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.455     1.602    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.530ns  (logic 0.552ns (36.078%)  route 0.978ns (63.922%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.418     0.418 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           0.606     1.024    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][12]
    SLICE_X103Y211       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.061     1.085 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_22/O
                         net (fo=1, routed)           0.121     1.206    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_22_n_0
    SLICE_X104Y209       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.014     1.220 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6/O
                         net (fo=1, routed)           0.234     1.454    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_6_n_0
    SLICE_X105Y199       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.059     1.513 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     1.530    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.672ns  (logic 0.578ns (34.569%)  route 1.094ns (65.431%))
  Logic Levels:           6  (LUT6=6)
  Clock Path Skew:        1.613ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.613ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.466ns (routing 0.408ns, distribution 1.058ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.411     0.411 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           0.650     1.061    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][15]
    SLICE_X103Y213       LUT6 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.014     1.075 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_99/O
                         net (fo=1, routed)           0.087     1.162    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_99_n_0
    SLICE_X102Y212       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.014     1.176 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_71/O
                         net (fo=1, routed)           0.043     1.219    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_71_n_0
    SLICE_X102Y212       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.014     1.233 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_34/O
                         net (fo=1, routed)           0.070     1.303    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_34_n_0
    SLICE_X101Y212       LUT6 (Prop_F6LUT_SLICEL_I5_O)
                                                      0.035     1.338 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10/O
                         net (fo=1, routed)           0.131     1.469    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_10_n_0
    SLICE_X104Y207       LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.040     1.509 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2/O
                         net (fo=1, routed)           0.087     1.596    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_2_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.050     1.646 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.026     1.672    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.466     1.613    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.693ns  (logic 0.603ns (35.617%)  route 1.090ns (64.383%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Path Skew:        1.608ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.608ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.461ns (routing 0.408ns, distribution 1.053ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           0.662     1.079    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][14]
    SLICE_X103Y213       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.050     1.129 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_54/O
                         net (fo=1, routed)           0.081     1.210    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_54_n_0
    SLICE_X102Y211       LUT5 (Prop_A6LUT_SLICEL_I0_O)
                                                      0.050     1.260 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_22/O
                         net (fo=1, routed)           0.091     1.351    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_22_n_0
    SLICE_X103Y211       LUT6 (Prop_F6LUT_SLICEM_I4_O)
                                                      0.014     1.365 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8/O
                         net (fo=1, routed)           0.098     1.463    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_8_n_0
    SLICE_X104Y207       LUT6 (Prop_G6LUT_SLICEM_I4_O)
                                                      0.022     1.485 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2/O
                         net (fo=1, routed)           0.134     1.619    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_2_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.050     1.669 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.024     1.693    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.461     1.608    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC0_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.815ns  (logic 0.628ns (34.601%)  route 1.187ns (65.399%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.606ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.606ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.459ns (routing 0.408ns, distribution 1.051ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC0_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.429     0.429 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           0.600     1.029    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][13]
    SLICE_X103Y211       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.050     1.079 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37/O
                         net (fo=1, routed)           0.128     1.207    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_37_n_0
    SLICE_X104Y209       LUT5 (Prop_F6LUT_SLICEM_I3_O)
                                                      0.059     1.266 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12/O
                         net (fo=1, routed)           0.221     1.487    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_12_n_0
    SLICE_X106Y218       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.050     1.537 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.221     1.758    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     1.798 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.017     1.815    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.459     1.606    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC1_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.060ns  (logic 1.186ns (29.212%)  route 2.874ns (70.788%))
  Logic Levels:           6  (LUT5=1 LUT6=5)
  Clock Path Skew:        2.298ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.298ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.116ns (routing 0.606ns, distribution 1.510ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.831     0.831 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.639     2.470    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[12]
    SLICE_X102Y223       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.035     2.505 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_85/O
                         net (fo=1, routed)           0.089     2.594    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_85_n_0
    SLICE_X102Y223       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.050     2.644 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_65/O
                         net (fo=1, routed)           0.085     2.729    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_65_n_0
    SLICE_X102Y222       LUT5 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.050     2.779 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_33/O
                         net (fo=1, routed)           0.212     2.991    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_33_n_0
    SLICE_X106Y222       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.036     3.027 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12/O
                         net (fo=1, routed)           0.289     3.316    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12_n_0
    SLICE_X104Y217       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.039     3.355 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3/O
                         net (fo=1, routed)           0.494     3.849    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.145     3.994 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.066     4.060    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.116     2.298    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.931ns  (logic 1.298ns (33.020%)  route 2.633ns (66.980%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.302ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.302ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.120ns (routing 0.606ns, distribution 1.514ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.920     0.920 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.844     2.764    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[11]
    SLICE_X103Y221       LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.123     2.887 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_24/O
                         net (fo=1, routed)           0.223     3.110    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_24_n_0
    SLICE_X106Y221       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.123     3.233 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_8/O
                         net (fo=1, routed)           0.091     3.324    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_8_n_0
    SLICE_X106Y218       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.036     3.360 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.425     3.785    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.881 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.050     3.931    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.120     2.302    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.883ns  (logic 1.249ns (32.166%)  route 2.634ns (67.834%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.286ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.104ns (routing 0.606ns, distribution 1.498ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.853     0.853 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.634     2.487    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[10]
    SLICE_X103Y221       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.090     2.577 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_57/O
                         net (fo=1, routed)           0.313     2.890    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_57_n_0
    SLICE_X105Y221       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.122     3.012 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_28/O
                         net (fo=1, routed)           0.275     3.287    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_28_n_0
    SLICE_X103Y216       LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.149     3.436 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7/O
                         net (fo=1, routed)           0.362     3.798    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7_n_0
    SLICE_X105Y199       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     3.833 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.050     3.883    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.104     2.286    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.779ns  (logic 1.256ns (33.236%)  route 2.523ns (66.764%))
  Logic Levels:           6  (LUT5=1 LUT6=5)
  Clock Path Skew:        2.300ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.300ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.118ns (routing 0.606ns, distribution 1.512ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.816     0.816 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.511     2.327    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[13]
    SLICE_X102Y223       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     2.424 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_104/O
                         net (fo=1, routed)           0.040     2.464    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_104_n_0
    SLICE_X102Y223       LUT6 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.090     2.554 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_82/O
                         net (fo=1, routed)           0.131     2.685    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_82_n_0
    SLICE_X102Y222       LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.035     2.720 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_46/O
                         net (fo=1, routed)           0.228     2.948    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_46_n_0
    SLICE_X105Y221       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.036     2.984 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_13/O
                         net (fo=1, routed)           0.206     3.190    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_13_n_0
    SLICE_X104Y219       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.145     3.335 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3/O
                         net (fo=1, routed)           0.335     3.670    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.037     3.707 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.072     3.779    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.118     2.300    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.528ns  (logic 1.260ns (35.714%)  route 2.268ns (64.286%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        2.285ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.285ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.103ns (routing 0.606ns, distribution 1.497ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.794     0.794 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.524     2.318    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[7]
    SLICE_X106Y223       LUT3 (Prop_C5LUT_SLICEL_I2_O)
                                                      0.098     2.416 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_37/O
                         net (fo=1, routed)           0.120     2.536    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_37_n_0
    SLICE_X106Y222       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.096     2.632 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_14/O
                         net (fo=1, routed)           0.162     2.794    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_14_n_0
    SLICE_X106Y215       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.123     2.917 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.403     3.320    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.149     3.469 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.059     3.528    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.103     2.285    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.090ns  (logic 1.108ns (35.858%)  route 1.982ns (64.142%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        2.295ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.295ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.113ns (routing 0.606ns, distribution 1.507ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.857     0.857 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.486     2.343    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[9]
    SLICE_X107Y222       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.125     2.468 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_26/O
                         net (fo=1, routed)           0.044     2.512    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_26_n_0
    SLICE_X107Y222       LUT4 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.091     2.603 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7/O
                         net (fo=1, routed)           0.402     3.005    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     3.040 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.050     3.090    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.113     2.295    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.004ns  (logic 1.127ns (37.517%)  route 1.877ns (62.483%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.299ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.117ns (routing 0.606ns, distribution 1.511ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.841     0.841 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.475     2.316    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[6]
    SLICE_X106Y223       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.148     2.464 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26/O
                         net (fo=1, routed)           0.041     2.505    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26_n_0
    SLICE_X106Y223       LUT4 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.050     2.555 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7/O
                         net (fo=1, routed)           0.311     2.866    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7_n_0
    SLICE_X106Y203       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.088     2.954 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.050     3.004    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.117     2.299    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.990ns  (logic 0.989ns (33.077%)  route 2.001ns (66.923%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.299ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.117ns (routing 0.606ns, distribution 1.511ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.504     2.283    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[8]
    SLICE_X107Y220       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.051     2.334 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24/O
                         net (fo=1, routed)           0.088     2.422    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24_n_0
    SLICE_X107Y220       LUT4 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.037     2.459 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7/O
                         net (fo=1, routed)           0.360     2.819    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7_n_0
    SLICE_X106Y203       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.122     2.941 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     2.990    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.117     2.299    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.453ns  (logic 0.468ns (32.209%)  route 0.985ns (67.791%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           0.740     1.122    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[8]
    SLICE_X107Y220       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.022     1.144 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24/O
                         net (fo=1, routed)           0.043     1.187    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_24_n_0
    SLICE_X107Y220       LUT4 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.014     1.201 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7/O
                         net (fo=1, routed)           0.186     1.387    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_7_n_0
    SLICE_X106Y203       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.050     1.437 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.453    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.462ns  (logic 0.520ns (35.568%)  route 0.942ns (64.432%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.403     0.403 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           0.737     1.140    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[6]
    SLICE_X106Y223       LUT6 (Prop_B6LUT_SLICEL_I2_O)
                                                      0.060     1.200 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26/O
                         net (fo=1, routed)           0.023     1.223    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_26_n_0
    SLICE_X106Y223       LUT4 (Prop_A6LUT_SLICEL_I2_O)
                                                      0.022     1.245 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7/O
                         net (fo=1, routed)           0.165     1.410    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_7_n_0
    SLICE_X106Y203       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     1.445 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.017     1.462    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.510ns  (logic 0.517ns (34.238%)  route 0.993ns (65.762%))
  Logic Levels:           3  (LUT4=1 LUT6=2)
  Clock Path Skew:        1.602ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.602ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.455ns (routing 0.408ns, distribution 1.047ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           0.739     1.156    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[9]
    SLICE_X107Y222       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.051     1.207 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_26/O
                         net (fo=1, routed)           0.025     1.232    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_26_n_0
    SLICE_X107Y222       LUT4 (Prop_E6LUT_SLICEM_I2_O)
                                                      0.035     1.267 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7/O
                         net (fo=1, routed)           0.212     1.479    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_7_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.014     1.493 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     1.510    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.455     1.602    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.724ns  (logic 0.582ns (33.759%)  route 1.142ns (66.241%))
  Logic Levels:           4  (LUT3=1 LUT6=3)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.399     0.399 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           0.758     1.157    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[7]
    SLICE_X106Y223       LUT3 (Prop_C5LUT_SLICEL_I2_O)
                                                      0.033     1.190 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_37/O
                         net (fo=1, routed)           0.066     1.256    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_37_n_0
    SLICE_X106Y222       LUT6 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.040     1.296 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_14/O
                         net (fo=1, routed)           0.086     1.382    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_14_n_0
    SLICE_X106Y215       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.050     1.432 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.211     1.643    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.060     1.703 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.021     1.724    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.862ns  (logic 0.588ns (31.579%)  route 1.274ns (68.421%))
  Logic Levels:           6  (LUT5=1 LUT6=5)
  Clock Path Skew:        1.613ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.613ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.466ns (routing 0.408ns, distribution 1.058ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.411     0.411 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           0.765     1.176    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[13]
    SLICE_X102Y223       LUT6 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.040     1.216 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_104/O
                         net (fo=1, routed)           0.023     1.239    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_104_n_0
    SLICE_X102Y223       LUT6 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.035     1.274 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_82/O
                         net (fo=1, routed)           0.067     1.341    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_82_n_0
    SLICE_X102Y222       LUT5 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.014     1.355 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_46/O
                         net (fo=1, routed)           0.117     1.472    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_46_n_0
    SLICE_X105Y221       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.015     1.487 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_13/O
                         net (fo=1, routed)           0.104     1.591    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_13_n_0
    SLICE_X104Y219       LUT6 (Prop_D6LUT_SLICEM_I3_O)
                                                      0.059     1.650 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3/O
                         net (fo=1, routed)           0.172     1.822    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.014     1.836 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.026     1.862    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.466     1.613    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.890ns  (logic 0.577ns (30.529%)  route 1.313ns (69.471%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.418     0.418 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           0.823     1.241    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[10]
    SLICE_X103Y221       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.035     1.276 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_57/O
                         net (fo=1, routed)           0.139     1.415    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_57_n_0
    SLICE_X105Y221       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.050     1.465 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_28/O
                         net (fo=1, routed)           0.142     1.607    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_28_n_0
    SLICE_X103Y216       LUT6 (Prop_B6LUT_SLICEM_I5_O)
                                                      0.060     1.667 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7/O
                         net (fo=1, routed)           0.192     1.859    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7_n_0
    SLICE_X105Y199       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.014     1.873 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     1.890    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.915ns  (logic 0.584ns (30.496%)  route 1.331ns (69.504%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.606ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.606ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.459ns (routing 0.408ns, distribution 1.051ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.429     0.429 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           0.931     1.360    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[11]
    SLICE_X103Y221       LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.050     1.410 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_24/O
                         net (fo=1, routed)           0.114     1.524    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_24_n_0
    SLICE_X106Y221       LUT6 (Prop_C6LUT_SLICEL_I2_O)
                                                      0.050     1.574 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_8/O
                         net (fo=1, routed)           0.048     1.622    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_8_n_0
    SLICE_X106Y218       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.015     1.637 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.221     1.858    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     1.898 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.017     1.915    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.459     1.606    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC1_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.019ns  (logic 0.564ns (27.935%)  route 1.455ns (72.065%))
  Logic Levels:           6  (LUT5=1 LUT6=5)
  Clock Path Skew:        1.608ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.608ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.461ns (routing 0.408ns, distribution 1.053ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC1_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y1           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y1           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           0.824     1.241    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_2[12]
    SLICE_X102Y223       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.014     1.255 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_85/O
                         net (fo=1, routed)           0.044     1.299    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_85_n_0
    SLICE_X102Y223       LUT6 (Prop_D6LUT_SLICEL_I2_O)
                                                      0.022     1.321 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_65/O
                         net (fo=1, routed)           0.047     1.368    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_65_n_0
    SLICE_X102Y222       LUT5 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.022     1.390 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_33/O
                         net (fo=1, routed)           0.110     1.500    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_33_n_0
    SLICE_X106Y222       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.015     1.515 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12/O
                         net (fo=1, routed)           0.150     1.665    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_12_n_0
    SLICE_X104Y217       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.015     1.680 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3/O
                         net (fo=1, routed)           0.256     1.936    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.059     1.995 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.024     2.019    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.461     1.608    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC2_CLK
  To Clock:  clk_pl_0

Max Delay            35 Endpoints
Min Delay            35 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.692ns  (logic 0.267ns (9.917%)  route 2.425ns (90.083%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -1.200ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.326ns
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.814ns (routing 1.474ns, distribution 1.340ns)
  Clock Net Delay (Destination): 2.144ns (routing 0.606ns, distribution 1.538ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.814     3.525    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.601 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.068     4.669    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.697 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       1.334     6.032    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/src_in
    SLICE_X109Y224       LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.163     6.195 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.023     6.218    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X109Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.144     2.326    d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/dest_clk
    SLICE_X109Y224       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac1_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.662ns  (logic 0.267ns (10.030%)  route 2.395ns (89.970%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -1.201ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.324ns
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.814ns (routing 1.474ns, distribution 1.340ns)
  Clock Net Delay (Destination): 2.142ns (routing 0.606ns, distribution 1.536ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.814     3.525    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.601 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.068     4.669    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.697 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       1.304     6.001    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/src_in
    SLICE_X110Y211       LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.163     6.164 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.023     6.187    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X110Y211       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.142     2.324    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/dest_clk
    SLICE_X110Y211       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.605ns  (logic 0.242ns (9.290%)  route 2.363ns (90.710%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -1.228ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.298ns
    Source Clock Delay      (SCD):    3.525ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.814ns (routing 1.474ns, distribution 1.340ns)
  Clock Net Delay (Destination): 2.116ns (routing 0.606ns, distribution 1.510ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.814     3.525    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.076     3.601 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.068     4.669    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     4.697 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       1.278     5.975    d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/src_in
    SLICE_X106Y225       LUT1 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.138     6.113 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.017     6.130    d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X106Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.116     2.298    d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/dest_clk
    SLICE_X106Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.418ns  (logic 1.313ns (29.719%)  route 3.105ns (70.281%))
  Logic Levels:           6  (LUT6=6)
  Clock Path Skew:        2.300ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.300ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.118ns (routing 0.606ns, distribution 1.512ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.816     0.816 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           2.125     2.941    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[15]
    SLICE_X104Y217       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.145     3.086 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_100/O
                         net (fo=1, routed)           0.153     3.239    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_100_n_0
    SLICE_X103Y217       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.145     3.384 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_72/O
                         net (fo=1, routed)           0.088     3.472    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_72_n_0
    SLICE_X102Y217       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.098     3.570 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_35/O
                         net (fo=1, routed)           0.089     3.659    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_35_n_0
    SLICE_X102Y217       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.035     3.694 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/O
                         net (fo=1, routed)           0.243     3.937    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11_n_0
    SLICE_X104Y219       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.037     3.974 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3/O
                         net (fo=1, routed)           0.335     4.309    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.037     4.346 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.072     4.418    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.118     2.300    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.240ns  (logic 1.278ns (30.142%)  route 2.962ns (69.858%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.298ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.298ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.116ns (routing 0.606ns, distribution 1.510ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.831     0.831 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           2.078     2.909    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[14]
    SLICE_X103Y215       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.125     3.034 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_30/O
                         net (fo=1, routed)           0.099     3.133    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_30_n_0
    SLICE_X102Y215       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.124     3.257 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_11/O
                         net (fo=1, routed)           0.225     3.482    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_11_n_0
    SLICE_X104Y217       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.053     3.535 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3/O
                         net (fo=1, routed)           0.494     4.029    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.145     4.174 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.066     4.240    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.116     2.298    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.194ns  (logic 1.349ns (32.165%)  route 2.845ns (67.835%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.302ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.302ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.120ns (routing 0.606ns, distribution 1.514ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.920     0.920 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           2.054     2.974    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[13]
    SLICE_X104Y217       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.145     3.119 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33/O
                         net (fo=1, routed)           0.084     3.203    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33_n_0
    SLICE_X105Y217       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.089     3.292 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11/O
                         net (fo=1, routed)           0.232     3.524    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11_n_0
    SLICE_X106Y218       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.099     3.623 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.425     4.048    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     4.144 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.050     4.194    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.120     2.302    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.068ns  (logic 1.093ns (26.868%)  route 2.975ns (73.132%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.295ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.295ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.113ns (routing 0.606ns, distribution 1.507ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.857     0.857 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           2.556     3.413    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[11]
    SLICE_X106Y215       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     3.509 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23/O
                         net (fo=1, routed)           0.041     3.550    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23_n_0
    SLICE_X106Y215       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.090     3.640 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.328     3.968    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.050     4.018 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.050     4.068    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.113     2.295    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.970ns  (logic 1.166ns (29.370%)  route 2.804ns (70.630%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        2.285ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.285ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.103ns (routing 0.606ns, distribution 1.497ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.794     0.794 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           2.017     2.811    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[9]
    SLICE_X107Y217       LUT4 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.099     2.910 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_30/O
                         net (fo=1, routed)           0.135     3.045    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_30_n_0
    SLICE_X107Y216       LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.089     3.134 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_11/O
                         net (fo=1, routed)           0.190     3.324    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_11_n_0
    SLICE_X106Y215       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.035     3.359 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.403     3.762    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.149     3.911 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.059     3.970    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.103     2.285    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.754ns  (logic 1.144ns (30.474%)  route 2.610ns (69.526%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.299ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.117ns (routing 0.606ns, distribution 1.511ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.841     0.841 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.844     2.685    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[8]
    SLICE_X107Y217       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.090     2.775 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_23/O
                         net (fo=1, routed)           0.304     3.079    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_23_n_0
    SLICE_X105Y216       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.090     3.169 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6/O
                         net (fo=1, routed)           0.412     3.581    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_n_0
    SLICE_X106Y203       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.123     3.704 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.050     3.754    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.117     2.299    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.704ns  (logic 1.122ns (30.292%)  route 2.582ns (69.708%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.286ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.104ns (routing 0.606ns, distribution 1.498ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.853     0.853 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           2.092     2.945    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[12]
    SLICE_X103Y216       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.145     3.090 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_49/O
                         net (fo=1, routed)           0.040     3.130    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_49_n_0
    SLICE_X103Y216       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.037     3.167 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_25/O
                         net (fo=1, routed)           0.038     3.205    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_25_n_0
    SLICE_X103Y216       LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.052     3.257 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7/O
                         net (fo=1, routed)           0.362     3.619    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7_n_0
    SLICE_X105Y199       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     3.654 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.050     3.704    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.104     2.286    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.725ns  (logic 0.486ns (28.174%)  route 1.239ns (71.826%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.004     1.386    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[10]
    SLICE_X107Y217       LUT6 (Prop_B6LUT_SLICEM_I0_O)
                                                      0.041     1.427 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_21/O
                         net (fo=1, routed)           0.027     1.454    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_21_n_0
    SLICE_X107Y217       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.041     1.495 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6/O
                         net (fo=1, routed)           0.192     1.687    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6_n_0
    SLICE_X106Y203       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.022     1.709 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     1.725    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.832ns  (logic 0.527ns (28.766%)  route 1.305ns (71.234%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.418     0.418 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.053     1.471    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[12]
    SLICE_X103Y216       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.059     1.530 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_49/O
                         net (fo=1, routed)           0.022     1.552    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_49_n_0
    SLICE_X103Y216       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.014     1.566 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_25/O
                         net (fo=1, routed)           0.021     1.587    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_25_n_0
    SLICE_X103Y216       LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.022     1.609 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7/O
                         net (fo=1, routed)           0.192     1.801    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7_n_0
    SLICE_X105Y199       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.014     1.815 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     1.832    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.834ns  (logic 0.524ns (28.571%)  route 1.310ns (71.429%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.403     0.403 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           0.931     1.334    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[8]
    SLICE_X107Y217       LUT6 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.035     1.369 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_23/O
                         net (fo=1, routed)           0.152     1.521    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_23_n_0
    SLICE_X105Y216       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.036     1.557 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6/O
                         net (fo=1, routed)           0.210     1.767    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_n_0
    SLICE_X106Y203       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.050     1.817 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.017     1.834    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.965ns  (logic 0.544ns (27.684%)  route 1.421ns (72.316%))
  Logic Levels:           4  (LUT4=1 LUT6=3)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.399     0.399 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.025     1.424    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[9]
    SLICE_X107Y217       LUT4 (Prop_C5LUT_SLICEM_I1_O)
                                                      0.036     1.460 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_30/O
                         net (fo=1, routed)           0.070     1.530    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_30_n_0
    SLICE_X107Y216       LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.035     1.565 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_11/O
                         net (fo=1, routed)           0.094     1.659    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_11_n_0
    SLICE_X106Y215       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.014     1.673 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.211     1.884    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.060     1.944 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.021     1.965    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.011ns  (logic 0.515ns (25.609%)  route 1.496ns (74.391%))
  Logic Levels:           3  (LUT6=3)
  Clock Path Skew:        1.602ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.602ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.455ns (routing 0.408ns, distribution 1.047ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.285     1.702    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[11]
    SLICE_X106Y215       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     1.742 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23/O
                         net (fo=1, routed)           0.022     1.764    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_23_n_0
    SLICE_X106Y215       LUT6 (Prop_B6LUT_SLICEL_I4_O)
                                                      0.036     1.800 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.172     1.972    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.022     1.994 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     2.011    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.455     1.602    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.044ns  (logic 0.604ns (29.550%)  route 1.440ns (70.450%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.606ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.606ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.459ns (routing 0.408ns, distribution 1.051ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.429     0.429 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.039     1.468    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[13]
    SLICE_X104Y217       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.059     1.527 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33/O
                         net (fo=1, routed)           0.044     1.571    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_33_n_0
    SLICE_X105Y217       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.035     1.606 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11/O
                         net (fo=1, routed)           0.119     1.725    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_11_n_0
    SLICE_X106Y218       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.041     1.766 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.221     1.987    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     2.027 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.017     2.044    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.459     1.606    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.092ns  (logic 0.600ns (28.681%)  route 1.492ns (71.319%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.608ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.608ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.461ns (routing 0.408ns, distribution 1.053ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.044     1.461    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[14]
    SLICE_X103Y215       LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.051     1.512 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_30/O
                         net (fo=1, routed)           0.051     1.563    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_30_n_0
    SLICE_X102Y215       LUT6 (Prop_H6LUT_SLICEL_I3_O)
                                                      0.050     1.613 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_11/O
                         net (fo=1, routed)           0.117     1.730    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_11_n_0
    SLICE_X104Y217       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.023     1.753 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3/O
                         net (fo=1, routed)           0.256     2.009    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.059     2.068 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.024     2.092    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.461     1.608    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.185ns  (logic 0.612ns (28.009%)  route 1.573ns (71.991%))
  Logic Levels:           6  (LUT6=6)
  Clock Path Skew:        1.613ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.613ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.466ns (routing 0.408ns, distribution 1.058ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.411     0.411 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.077     1.488    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_0[15]
    SLICE_X104Y217       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.059     1.547 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_100/O
                         net (fo=1, routed)           0.078     1.625    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_100_n_0
    SLICE_X103Y217       LUT6 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.059     1.684 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_72/O
                         net (fo=1, routed)           0.048     1.732    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_72_n_0
    SLICE_X102Y217       LUT6 (Prop_B6LUT_SLICEL_I0_O)
                                                      0.041     1.773 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_35/O
                         net (fo=1, routed)           0.044     1.817    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_35_n_0
    SLICE_X102Y217       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.014     1.831 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11/O
                         net (fo=1, routed)           0.128     1.959    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_11_n_0
    SLICE_X104Y219       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.014     1.973 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3/O
                         net (fo=1, routed)           0.172     2.145    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.014     2.159 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.026     2.185    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.466     1.613    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.392ns  (logic 0.102ns (7.328%)  route 1.290ns (92.672%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.298ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.604ns
    Source Clock Delay      (SCD):    1.903ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.536ns (routing 0.796ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.457ns (routing 0.408ns, distribution 1.049ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.536     1.903    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.941 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.569     2.510    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.527 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       0.714     3.241    d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/src_in
    SLICE_X106Y225       LUT1 (Prop_A5LUT_SLICEL_I0_O)
                                                      0.047     3.288 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.007     3.295    d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X106Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.457     1.604    d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/dest_clk
    SLICE_X106Y225       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac2_clk_valid_i/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        1.413ns  (logic 0.114ns (8.068%)  route 1.299ns (91.932%))
  Logic Levels:           2  (BUFGCE=1 LUT1=1)
  Clock Path Skew:        -0.277ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.626ns
    Source Clock Delay      (SCD):    1.903ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.536ns (routing 0.796ns, distribution 0.740ns)
  Clock Net Delay (Destination): 1.479ns (routing 0.408ns, distribution 1.071ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.536     1.903    d_1_i/rst_dac2/U0/slowest_sync_clk
    SLICE_X66Y272        FDRE                                         r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y272        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.941 r  d_1_i/rst_dac2/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           0.569     2.510    d_1_i/rst_dac2/U0/peripheral_aresetn[0]
    BUFGCE_X0Y96         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     2.527 r  d_1_i/rst_dac2/U0/peripheral_aresetn[0]_BUFG_inst/O
                         net (fo=28374, routed)       0.723     3.250    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/src_in
    SLICE_X110Y211       LUT1 (Prop_A5LUT_SLICEM_I0_O)
                                                      0.059     3.309 r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt/O
                         net (fo=1, routed)           0.007     3.316    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]_xlnx_opt_1
    SLICE_X110Y211       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.479     1.626    d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/dest_clk
    SLICE_X110Y211       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/cdc_dac0_clk_valid_i/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC3_CLK
  To Clock:  clk_pl_0

Max Delay             8 Endpoints
Min Delay             8 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.068ns  (logic 1.388ns (27.388%)  route 3.680ns (72.612%))
  Logic Levels:           6  (LUT5=1 LUT6=5)
  Clock Path Skew:        2.298ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.298ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.116ns (routing 0.606ns, distribution 1.510ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.831     0.831 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           2.497     3.328    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[14]
    SLICE_X101Y222       LUT5 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.149     3.477 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_80/O
                         net (fo=1, routed)           0.088     3.565    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_80_n_0
    SLICE_X100Y222       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     3.615 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_56/O
                         net (fo=1, routed)           0.196     3.811    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_56_n_0
    SLICE_X103Y220       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.037     3.848 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_26/O
                         net (fo=1, routed)           0.196     4.044    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_26_n_0
    SLICE_X105Y218       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.051     4.095 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                         net (fo=1, routed)           0.143     4.238    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    SLICE_X104Y217       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.125     4.363 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3/O
                         net (fo=1, routed)           0.494     4.857    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.145     5.002 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.066     5.068    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.116     2.298    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.681ns  (logic 1.275ns (27.238%)  route 3.406ns (72.762%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.285ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.285ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.103ns (routing 0.606ns, distribution 1.497ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.794     0.794 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           2.779     3.573    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[9]
    SLICE_X106Y214       LUT6 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.035     3.608 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_33/O
                         net (fo=1, routed)           0.057     3.665    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_33_n_0
    SLICE_X106Y214       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.148     3.813 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12/O
                         net (fo=1, routed)           0.108     3.921    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12_n_0
    SLICE_X106Y215       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.149     4.070 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.403     4.473    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.149     4.622 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.059     4.681    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.103     2.285    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.578ns  (logic 1.120ns (24.465%)  route 3.458ns (75.535%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.286ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.286ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.104ns (routing 0.606ns, distribution 1.498ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.853     0.853 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           2.451     3.304    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[12]
    SLICE_X103Y220       LUT5 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.145     3.449 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_53/O
                         net (fo=1, routed)           0.302     3.751    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_53_n_0
    SLICE_X100Y217       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.050     3.801 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_26/O
                         net (fo=1, routed)           0.293     4.094    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_26_n_0
    SLICE_X103Y216       LUT6 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.037     4.131 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7/O
                         net (fo=1, routed)           0.362     4.493    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7_n_0
    SLICE_X105Y199       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.035     4.528 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.050     4.578    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.104     2.286    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.574ns  (logic 1.318ns (28.815%)  route 3.256ns (71.185%))
  Logic Levels:           6  (LUT5=1 LUT6=5)
  Clock Path Skew:        2.300ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.300ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.118ns (routing 0.606ns, distribution 1.512ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.816     0.816 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           2.343     3.159    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[15]
    SLICE_X100Y222       LUT5 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.099     3.258 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_102/O
                         net (fo=1, routed)           0.089     3.347    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_102_n_0
    SLICE_X100Y222       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.099     3.446 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_78/O
                         net (fo=1, routed)           0.141     3.587    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_78_n_0
    SLICE_X102Y220       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090     3.677 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_44/O
                         net (fo=1, routed)           0.084     3.761    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_44_n_0
    SLICE_X102Y220       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.089     3.850 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_12/O
                         net (fo=1, routed)           0.192     4.042    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_12_n_0
    SLICE_X104Y219       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.088     4.130 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3/O
                         net (fo=1, routed)           0.335     4.465    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.037     4.502 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.072     4.574    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.118     2.300    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.563ns  (logic 1.296ns (28.402%)  route 3.267ns (71.598%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        2.302ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.302ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.120ns (routing 0.606ns, distribution 1.514ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.920     0.920 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           2.347     3.267    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[13]
    SLICE_X103Y220       LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.089     3.356 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_30/O
                         net (fo=1, routed)           0.098     3.454    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_30_n_0
    SLICE_X103Y218       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.101     3.555 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10/O
                         net (fo=1, routed)           0.347     3.902    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10_n_0
    SLICE_X106Y218       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.090     3.992 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.425     4.417    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.096     4.513 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.050     4.563    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.120     2.302    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.552ns  (logic 1.027ns (22.562%)  route 3.525ns (77.438%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.299ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.117ns (routing 0.606ns, distribution 1.511ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.779     0.779 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           2.874     3.653    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[10]
    SLICE_X107Y219       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.123     3.776 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_37/O
                         net (fo=1, routed)           0.090     3.866    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_37_n_0
    SLICE_X106Y219       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.036     3.902 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_20/O
                         net (fo=1, routed)           0.143     4.045    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_20_n_0
    SLICE_X107Y217       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.039     4.084 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6/O
                         net (fo=1, routed)           0.369     4.453    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6_n_0
    SLICE_X106Y203       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.050     4.503 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.049     4.552    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.117     2.299    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.188ns  (logic 1.145ns (27.340%)  route 3.043ns (72.660%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.295ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.295ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.113ns (routing 0.606ns, distribution 1.507ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.857     0.857 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           2.383     3.240    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[11]
    SLICE_X107Y215       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.090     3.330 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46/O
                         net (fo=1, routed)           0.140     3.470    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46_n_0
    SLICE_X106Y214       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.050     3.520 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_21/O
                         net (fo=1, routed)           0.142     3.662    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_21_n_0
    SLICE_X106Y215       LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.098     3.760 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.328     4.088    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.050     4.138 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.050     4.188    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.113     2.295    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.151ns  (logic 1.101ns (26.524%)  route 3.050ns (73.476%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        2.299ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.299ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.117ns (routing 0.606ns, distribution 1.511ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.841     0.841 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           2.510     3.351    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[8]
    SLICE_X105Y216       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.050     3.401 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_42/O
                         net (fo=1, routed)           0.041     3.442    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_42_n_0
    SLICE_X105Y216       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.036     3.478 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22/O
                         net (fo=1, routed)           0.037     3.515    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22_n_0
    SLICE_X105Y216       LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.051     3.566 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6/O
                         net (fo=1, routed)           0.412     3.978    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_n_0
    SLICE_X106Y203       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.123     4.101 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.050     4.151    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.117     2.299    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.058ns  (logic 0.512ns (24.879%)  route 1.546ns (75.121%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[8])
                                                      0.403     0.403 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[8]
                         net (fo=1, routed)           1.276     1.679    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[8]
    SLICE_X105Y216       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.022     1.701 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_42/O
                         net (fo=1, routed)           0.022     1.723    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_42_n_0
    SLICE_X105Y216       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.014     1.737 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22/O
                         net (fo=1, routed)           0.021     1.758    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_22_n_0
    SLICE_X105Y216       LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.023     1.781 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6/O
                         net (fo=1, routed)           0.210     1.991    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_6_n_0
    SLICE_X106Y203       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.050     2.041 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[8]_i_1/O
                         net (fo=1, routed)           0.017     2.058    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_76
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.084ns  (logic 0.537ns (25.768%)  route 1.547ns (74.232%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.602ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.602ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.455ns (routing 0.408ns, distribution 1.047ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[11])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[11]
                         net (fo=1, routed)           1.213     1.630    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[11]
    SLICE_X107Y215       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.035     1.665 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46/O
                         net (fo=1, routed)           0.073     1.738    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_46_n_0
    SLICE_X106Y214       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.022     1.760 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_21/O
                         net (fo=1, routed)           0.072     1.832    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_21_n_0
    SLICE_X106Y215       LUT6 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.041     1.873 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6/O
                         net (fo=1, routed)           0.172     2.045    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_6_n_0
    SLICE_X106Y202       LUT6 (Prop_C6LUT_SLICEL_I4_O)
                                                      0.022     2.067 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[11]_i_1/O
                         net (fo=1, routed)           0.017     2.084    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_73
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.455     1.602    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.209ns  (logic 0.580ns (26.256%)  route 1.629ns (73.744%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.606ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.606ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.459ns (routing 0.408ns, distribution 1.051ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[13])
                                                      0.429     0.429 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[13]
                         net (fo=1, routed)           1.187     1.616    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[13]
    SLICE_X103Y220       LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.035     1.651 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_30/O
                         net (fo=1, routed)           0.052     1.703    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_30_n_0
    SLICE_X103Y218       LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.041     1.744 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10/O
                         net (fo=1, routed)           0.152     1.896    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_10_n_0
    SLICE_X106Y218       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.035     1.931 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2/O
                         net (fo=1, routed)           0.221     2.152    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_2_n_0
    SLICE_X106Y194       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.040     2.192 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[13]_i_1/O
                         net (fo=1, routed)           0.017     2.209    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_71
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.459     1.606    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[13]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.255ns  (logic 0.612ns (27.140%)  route 1.643ns (72.860%))
  Logic Levels:           6  (LUT5=1 LUT6=5)
  Clock Path Skew:        1.613ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.613ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.466ns (routing 0.408ns, distribution 1.058ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[15])
                                                      0.411     0.411 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[15]
                         net (fo=1, routed)           1.182     1.593    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[15]
    SLICE_X100Y222       LUT5 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.041     1.634 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_102/O
                         net (fo=1, routed)           0.047     1.681    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_102_n_0
    SLICE_X100Y222       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.041     1.722 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_78/O
                         net (fo=1, routed)           0.074     1.796    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_78_n_0
    SLICE_X102Y220       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.035     1.831 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_44/O
                         net (fo=1, routed)           0.040     1.871    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_44_n_0
    SLICE_X102Y220       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.035     1.906 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_12/O
                         net (fo=1, routed)           0.102     2.008    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_12_n_0
    SLICE_X104Y219       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.035     2.043 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3/O
                         net (fo=1, routed)           0.172     2.215    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_3_n_0
    SLICE_X104Y201       LUT6 (Prop_D6LUT_SLICEM_I1_O)
                                                      0.014     2.229 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[15]_i_1/O
                         net (fo=1, routed)           0.026     2.255    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_69
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.466     1.613    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y201       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.257ns  (logic 0.484ns (21.444%)  route 1.773ns (78.556%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.605ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.605ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.458ns (routing 0.408ns, distribution 1.050ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[10])
                                                      0.382     0.382 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[10]
                         net (fo=1, routed)           1.440     1.822    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[10]
    SLICE_X107Y219       LUT6 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.050     1.872 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_37/O
                         net (fo=1, routed)           0.048     1.920    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_37_n_0
    SLICE_X106Y219       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.015     1.935 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_20/O
                         net (fo=1, routed)           0.077     2.012    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_20_n_0
    SLICE_X107Y217       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.015     2.027 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6/O
                         net (fo=1, routed)           0.192     2.219    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_6_n_0
    SLICE_X106Y203       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.022     2.241 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[10]_i_1/O
                         net (fo=1, routed)           0.016     2.257    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_74
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.458     1.605    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y203       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[10]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.257ns  (logic 0.527ns (23.350%)  route 1.730ns (76.650%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[12])
                                                      0.418     0.418 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[12]
                         net (fo=1, routed)           1.242     1.660    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[12]
    SLICE_X103Y220       LUT5 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.059     1.719 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_53/O
                         net (fo=1, routed)           0.137     1.856    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_53_n_0
    SLICE_X100Y217       LUT6 (Prop_D6LUT_SLICEL_I4_O)
                                                      0.022     1.878 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_26/O
                         net (fo=1, routed)           0.142     2.020    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_26_n_0
    SLICE_X103Y216       LUT6 (Prop_B6LUT_SLICEM_I3_O)
                                                      0.014     2.034 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7/O
                         net (fo=1, routed)           0.192     2.226    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_7_n_0
    SLICE_X105Y199       LUT6 (Prop_C6LUT_SLICEL_I5_O)
                                                      0.014     2.240 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[12]_i_1/O
                         net (fo=1, routed)           0.017     2.257    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_72
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X105Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.305ns  (logic 0.592ns (25.683%)  route 1.713ns (74.317%))
  Logic Levels:           4  (LUT6=4)
  Clock Path Skew:        1.598ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.598ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[9])
                                                      0.399     0.399 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[9]
                         net (fo=1, routed)           1.396     1.795    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[9]
    SLICE_X106Y214       LUT6 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.014     1.809 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_33/O
                         net (fo=1, routed)           0.031     1.840    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_33_n_0
    SLICE_X106Y214       LUT6 (Prop_F6LUT_SLICEL_I4_O)
                                                      0.059     1.899 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12/O
                         net (fo=1, routed)           0.054     1.953    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_12_n_0
    SLICE_X106Y215       LUT6 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.060     2.013 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3/O
                         net (fo=1, routed)           0.211     2.224    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_3_n_0
    SLICE_X103Y198       LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.060     2.284 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[9]_i_1/O
                         net (fo=1, routed)           0.021     2.305    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_75
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y198       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
                            (rising edge-triggered cell RFDAC clocked by RFDAC3_CLK  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        2.509ns  (logic 0.646ns (25.747%)  route 1.863ns (74.253%))
  Logic Levels:           6  (LUT5=1 LUT6=5)
  Clock Path Skew:        1.608ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.608ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.461ns (routing 0.408ns, distribution 1.053ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC3_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/INTERNAL_FBRC_MUX
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_STATUS_COMMON[14])
                                                      0.417     0.417 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[14]
                         net (fo=1, routed)           1.259     1.676    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[14]
    SLICE_X101Y222       LUT5 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.060     1.736 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_80/O
                         net (fo=1, routed)           0.048     1.784    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_80_n_0
    SLICE_X100Y222       LUT6 (Prop_G6LUT_SLICEL_I4_O)
                                                      0.022     1.806 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_56/O
                         net (fo=1, routed)           0.101     1.907    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_56_n_0
    SLICE_X103Y220       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.014     1.921 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_26/O
                         net (fo=1, routed)           0.102     2.023    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_26_n_0
    SLICE_X105Y218       LUT6 (Prop_H6LUT_SLICEL_I4_O)
                                                      0.023     2.046 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9/O
                         net (fo=1, routed)           0.073     2.119    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_9_n_0
    SLICE_X104Y217       LUT6 (Prop_H6LUT_SLICEM_I0_O)
                                                      0.051     2.170 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3/O
                         net (fo=1, routed)           0.256     2.426    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_3_n_0
    SLICE_X104Y193       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.059     2.485 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[14]_i_1/O
                         net (fo=1, routed)           0.024     2.509    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_70
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.461     1.608    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[14]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_out1_d_1_clk_core_0
  To Clock:  clk_pl_0

Max Delay          1476 Endpoints
Min Delay          1476 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.291ns  (logic 0.176ns (13.635%)  route 1.115ns (86.365%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -2.324ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.002ns
    Source Clock Delay      (SCD):    4.326ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.861ns (routing 0.947ns, distribution 0.914ns)
  Clock Net Delay (Destination): 1.820ns (routing 0.606ns, distribution 1.214ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.861     4.326    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y218        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y218        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     4.403 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=213, routed)         0.875     5.278    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/peripheral_aresetn[0]_bufg_place_replica_1
    SLICE_X49Y183        LUT1 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.099     5.377 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.240     5.617    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X49Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.820     2.002    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X49Y183        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.247ns  (logic 0.174ns (13.955%)  route 1.073ns (86.045%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -2.240ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.086ns
    Source Clock Delay      (SCD):    4.326ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.861ns (routing 0.947ns, distribution 0.914ns)
  Clock Net Delay (Destination): 1.904ns (routing 0.606ns, distribution 1.298ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.861     4.326    d_1_i/rst_core/U0/slowest_sync_clk
    SLICE_X69Y218        FDRE                                         r  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X69Y218        FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     4.403 f  d_1_i/rst_core/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=213, routed)         0.818     5.221    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/peripheral_aresetn[0]_bufg_place_replica_1
    SLICE_X68Y185        LUT1 (Prop_F6LUT_SLICEL_I0_O)
                                                      0.097     5.318 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst_i_1/O
                         net (fo=1, routed)           0.255     5.573    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/src_rst
    SLICE_X68Y185        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.904     2.086    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/dest_clk
    SLICE_X68Y185        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/inst_xpm_cdc_sync_rst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.572ns  (logic 0.079ns (13.800%)  route 0.493ns (86.200%))
  Logic Levels:           0  
  Clock Path Skew:        -2.242ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.994ns
    Source Clock Delay      (SCD):    4.236ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.771ns (routing 0.947ns, distribution 0.824ns)
  Clock Net Delay (Destination): 1.812ns (routing 0.606ns, distribution 1.206ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.771     4.236    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X50Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y184        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.079     4.315 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.493     4.808    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X50Y181        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.812     1.994    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X50Y181        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.354ns  (logic 0.079ns (22.311%)  route 0.275ns (77.689%))
  Logic Levels:           0  
  Clock Path Skew:        -2.254ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.093ns
    Source Clock Delay      (SCD):    4.347ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.882ns (routing 0.947ns, distribution 0.935ns)
  Clock Net Delay (Destination): 1.911ns (routing 0.606ns, distribution 1.305ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.882     4.347    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X68Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y182        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.079     4.426 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.275     4.701    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X69Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.911     2.093    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X69Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4/WEA[1]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.216ns  (logic 0.265ns (8.240%)  route 2.951ns (91.760%))
  Logic Levels:           2  (LUT2=1 LUT6=1)
  Clock Path Skew:        -2.207ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.126ns
    Source Clock Delay      (SCD):    4.333ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.868ns (routing 0.947ns, distribution 0.921ns)
  Clock Net Delay (Destination): 1.944ns (routing 0.606ns, distribution 1.338ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.868     4.333    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X66Y197        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     4.411 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/Q
                         net (fo=208, routed)         0.712     5.123    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1_0
    SLICE_X72Y191        LUT2 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.090     5.213 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/RAM_reg_bram_0_i_1__1/O
                         net (fo=102, routed)         0.844     6.057    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/mem_rw_i/RAM_reg_bram_4_0
    SLICE_X65Y190        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     6.154 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/mem_rw_i/RAM_reg_bram_0_i_2__1/O
                         net (fo=20, routed)          1.395     7.549    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4_0[0]
    RAMB36_X7Y40         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4/WEA[1]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.944     2.126    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/ps_clk_i
    RAMB36_X7Y40         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4/WEA[0]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.210ns  (logic 0.265ns (8.256%)  route 2.945ns (91.744%))
  Logic Levels:           2  (LUT2=1 LUT6=1)
  Clock Path Skew:        -2.207ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.126ns
    Source Clock Delay      (SCD):    4.333ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.868ns (routing 0.947ns, distribution 0.921ns)
  Clock Net Delay (Destination): 1.944ns (routing 0.606ns, distribution 1.338ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.868     4.333    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X66Y197        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     4.411 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/Q
                         net (fo=208, routed)         0.712     5.123    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1_0
    SLICE_X72Y191        LUT2 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.090     5.213 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/RAM_reg_bram_0_i_1__1/O
                         net (fo=102, routed)         0.844     6.057    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/mem_rw_i/RAM_reg_bram_4_0
    SLICE_X65Y190        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     6.154 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/mem_rw_i/RAM_reg_bram_0_i_2__1/O
                         net (fo=20, routed)          1.389     7.543    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4_0[0]
    RAMB36_X7Y40         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4/WEA[0]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.944     2.126    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/ps_clk_i
    RAMB36_X7Y40         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4/WEA[2]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.158ns  (logic 0.265ns (8.392%)  route 2.893ns (91.608%))
  Logic Levels:           2  (LUT2=1 LUT6=1)
  Clock Path Skew:        -2.207ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.126ns
    Source Clock Delay      (SCD):    4.333ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.868ns (routing 0.947ns, distribution 0.921ns)
  Clock Net Delay (Destination): 1.944ns (routing 0.606ns, distribution 1.338ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.868     4.333    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X66Y197        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     4.411 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/Q
                         net (fo=208, routed)         0.712     5.123    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1_0
    SLICE_X72Y191        LUT2 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.090     5.213 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/RAM_reg_bram_0_i_1__1/O
                         net (fo=102, routed)         0.844     6.057    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/mem_rw_i/RAM_reg_bram_4_0
    SLICE_X65Y190        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     6.154 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/mem_rw_i/RAM_reg_bram_0_i_2__1/O
                         net (fo=20, routed)          1.337     7.491    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4_0[0]
    RAMB36_X7Y40         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4/WEA[2]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.944     2.126    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/ps_clk_i
    RAMB36_X7Y40         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4/WEA[3]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.152ns  (logic 0.265ns (8.408%)  route 2.887ns (91.592%))
  Logic Levels:           2  (LUT2=1 LUT6=1)
  Clock Path Skew:        -2.207ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.126ns
    Source Clock Delay      (SCD):    4.333ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.868ns (routing 0.947ns, distribution 0.921ns)
  Clock Net Delay (Destination): 1.944ns (routing 0.606ns, distribution 1.338ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.868     4.333    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X66Y197        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     4.411 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/Q
                         net (fo=208, routed)         0.712     5.123    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1_0
    SLICE_X72Y191        LUT2 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.090     5.213 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/RAM_reg_bram_0_i_1__1/O
                         net (fo=102, routed)         0.844     6.057    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/mem_rw_i/RAM_reg_bram_4_0
    SLICE_X65Y190        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     6.154 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/mem_rw_i/RAM_reg_bram_0_i_2__1/O
                         net (fo=20, routed)          1.331     7.485    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4_0[0]
    RAMB36_X7Y40         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4/WEA[3]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.944     2.126    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/ps_clk_i
    RAMB36_X7Y40         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_0/WEA[2]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.839ns  (logic 0.265ns (9.336%)  route 2.574ns (90.664%))
  Logic Levels:           2  (LUT2=1 LUT6=1)
  Clock Path Skew:        -2.252ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.081ns
    Source Clock Delay      (SCD):    4.333ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.868ns (routing 0.947ns, distribution 0.921ns)
  Clock Net Delay (Destination): 1.899ns (routing 0.606ns, distribution 1.293ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.868     4.333    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X66Y197        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     4.411 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/Q
                         net (fo=208, routed)         0.712     5.123    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1_0
    SLICE_X72Y191        LUT2 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.090     5.213 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/RAM_reg_bram_0_i_1__1/O
                         net (fo=102, routed)         0.844     6.057    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/mem_rw_i/RAM_reg_bram_4_0
    SLICE_X65Y190        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     6.154 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/mem_rw_i/RAM_reg_bram_0_i_2__1/O
                         net (fo=20, routed)          1.018     7.172    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4_0[0]
    RAMB36_X6Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_0/WEA[2]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.899     2.081    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/ps_clk_i
    RAMB36_X6Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_0/CLKARDCLK

Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_0/WEA[1]
                            (rising edge-triggered cell RAMB36E2 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.837ns  (logic 0.265ns (9.342%)  route 2.572ns (90.658%))
  Logic Levels:           2  (LUT2=1 LUT6=1)
  Clock Path Skew:        -2.252ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.081ns
    Source Clock Delay      (SCD):    4.333ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.868ns (routing 0.947ns, distribution 0.921ns)
  Clock Net Delay (Destination): 1.899ns (routing 0.606ns, distribution 1.293ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.093     2.319    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     2.192 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     2.437    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     2.465 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.868     4.333    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/c_clk_i
    SLICE_X66Y197        FDRE                                         r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X66Y197        FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     4.411 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1/Q
                         net (fo=208, routed)         0.712     5.123    d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/TPROC_CFG_reg[3]_rep__1_0
    SLICE_X72Y191        LUT2 (Prop_G6LUT_SLICEM_I1_O)
                                                      0.090     5.213 r  d_1_i/qick_processor_0/inst/QPROC/QPROC_xREG/RAM_reg_bram_0_i_1__1/O
                         net (fo=102, routed)         0.844     6.057    d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/mem_rw_i/RAM_reg_bram_4_0
    SLICE_X65Y190        LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.097     6.154 r  d_1_i/qick_processor_0/inst/QPROC/QMEM_CTRL/mem_rw_i/RAM_reg_bram_0_i_2__1/O
                         net (fo=20, routed)          1.016     7.170    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_4_0[0]
    RAMB36_X6Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_0/WEA[1]
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.899     2.081    d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/ps_clk_i
    RAMB36_X6Y42         RAMB36E2                                     r  d_1_i/qick_processor_0/inst/QPROC/CORE_0/CORE_MEM/W_MEM/RAM_reg_bram_0/CLKARDCLK





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.039ns (31.967%)  route 0.083ns (68.033%))
  Logic Levels:           0  
  Clock Path Skew:        -1.235ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.405ns
    Source Clock Delay      (SCD):    2.640ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.980ns (routing 0.518ns, distribution 0.462ns)
  Clock Net Delay (Destination): 1.258ns (routing 0.408ns, distribution 0.850ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.980     2.640    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X50Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y184        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.679 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.083     2.762    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X50Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.258     1.405    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X50Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.039ns (38.614%)  route 0.062ns (61.386%))
  Logic Levels:           0  
  Clock Path Skew:        -1.215ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.478ns
    Source Clock Delay      (SCD):    2.693ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.033ns (routing 0.518ns, distribution 0.515ns)
  Clock Net Delay (Destination): 1.331ns (routing 0.408ns, distribution 0.923ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.033     2.693    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X67Y181        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y181        FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     2.732 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q
                         net (fo=1, routed)           0.062     2.794    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[0]
    SLICE_X67Y180        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.331     1.478    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X67Y180        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.171ns  (logic 0.039ns (22.807%)  route 0.132ns (77.193%))
  Logic Levels:           0  
  Clock Path Skew:        -1.237ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.403ns
    Source Clock Delay      (SCD):    2.640ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.980ns (routing 0.518ns, distribution 0.462ns)
  Clock Net Delay (Destination): 1.256ns (routing 0.408ns, distribution 0.848ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.980     2.640    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X51Y180        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y180        FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     2.679 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.132     2.811    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[1]
    SLICE_X52Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.256     1.403    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X52Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.141ns  (logic 0.039ns (27.660%)  route 0.102ns (72.340%))
  Logic Levels:           0  
  Clock Path Skew:        -1.219ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.474ns
    Source Clock Delay      (SCD):    2.693ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.033ns (routing 0.518ns, distribution 0.515ns)
  Clock Net Delay (Destination): 1.327ns (routing 0.408ns, distribution 0.919ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.033     2.693    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X67Y181        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y181        FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     2.732 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.102     2.834    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X67Y181        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.327     1.474    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X67Y181        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.143ns  (logic 0.039ns (27.273%)  route 0.104ns (72.727%))
  Logic Levels:           0  
  Clock Path Skew:        -1.235ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.462ns
    Source Clock Delay      (SCD):    2.698ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.038ns (routing 0.518ns, distribution 0.520ns)
  Clock Net Delay (Destination): 1.315ns (routing 0.408ns, distribution 0.907ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.038     2.698    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X68Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y182        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.737 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.104     2.841    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[4]
    SLICE_X68Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.315     1.462    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X68Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.205ns  (logic 0.040ns (19.512%)  route 0.165ns (80.488%))
  Logic Levels:           0  
  Clock Path Skew:        -1.235ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.405ns
    Source Clock Delay      (SCD):    2.640ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.980ns (routing 0.518ns, distribution 0.462ns)
  Clock Net Delay (Destination): 1.258ns (routing 0.408ns, distribution 0.850ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.980     2.640    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X51Y180        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y180        FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     2.680 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.165     2.845    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[3]
    SLICE_X51Y180        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.258     1.405    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X51Y180        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.159ns  (logic 0.039ns (24.499%)  route 0.120ns (75.501%))
  Logic Levels:           0  
  Clock Path Skew:        -1.231ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.467ns
    Source Clock Delay      (SCD):    2.698ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.038ns (routing 0.518ns, distribution 0.520ns)
  Clock Net Delay (Destination): 1.320ns (routing 0.408ns, distribution 0.912ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.038     2.698    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X68Y182        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X68Y182        FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     2.737 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.120     2.857    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X69Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.320     1.467    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X69Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.172ns  (logic 0.039ns (22.674%)  route 0.133ns (77.326%))
  Logic Levels:           0  
  Clock Path Skew:        -1.215ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.478ns
    Source Clock Delay      (SCD):    2.693ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      1.033ns (routing 0.518ns, distribution 0.515ns)
  Clock Net Delay (Destination): 1.331ns (routing 0.408ns, distribution 0.923ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.033     2.693    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X67Y181        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X67Y181        FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     2.732 r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.133     2.865    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X67Y180        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.331     1.478    d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X67Y180        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_1/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.235ns  (logic 0.039ns (16.596%)  route 0.196ns (83.404%))
  Logic Levels:           0  
  Clock Path Skew:        -1.231ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.409ns
    Source Clock Delay      (SCD):    2.640ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.980ns (routing 0.518ns, distribution 0.462ns)
  Clock Net Delay (Destination): 1.262ns (routing 0.408ns, distribution 0.854ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.980     2.640    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_clk
    SLICE_X51Y180        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y180        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.679 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q
                         net (fo=1, routed)           0.196     2.875    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/async_path[2]
    SLICE_X50Y180        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.262     1.409    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_clk
    SLICE_X50Y180        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/C

Slack:                    inf
  Source:                 d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Destination:            d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.267ns  (logic 0.039ns (14.622%)  route 0.228ns (85.378%))
  Logic Levels:           0  
  Clock Path Skew:        -1.239ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.401ns
    Source Clock Delay      (SCD):    2.640ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.217ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Source):      0.980ns (routing 0.518ns, distribution 0.462ns)
  Clock Net Delay (Destination): 1.254ns (routing 0.408ns, distribution 0.846ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.147     1.267    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     1.497 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     1.643    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.660 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        0.980     2.640    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X50Y184        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y184        FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     2.679 r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=85, routed)          0.228     2.907    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X50Y181        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.254     1.401    d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X50Y181        FDRE                                         r  d_1_i/axis_clk_cnvrt_avg_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  clk_pl_0

Max Delay           394 Endpoints
Min Delay           394 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.957ns  (logic 0.118ns (2.381%)  route 4.839ns (97.619%))
  Logic Levels:           1  (LUT1=1)
  Clock Path Skew:        -0.368ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.132ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.274ns (routing 0.670ns, distribution 1.604ns)
  Clock Net Delay (Destination): 1.950ns (routing 0.606ns, distribution 1.344ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.274     2.500    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X91Y153        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y153        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.581 f  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=287, routed)         4.475     7.056    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X63Y3          LUT1 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.037     7.093 r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1/O
                         net (fo=1, routed)           0.364     7.457    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/asr_d1
    SLICE_X63Y3          FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.950     2.132    d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/aclk
    SLICE_X63Y3          FDRE                                         r  d_1_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/ACTIVE_LOW_AUX.ACT_LO_AUX/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.635ns  (logic 0.081ns (1.748%)  route 4.554ns (98.252%))
  Logic Levels:           0  
  Clock Path Skew:        -0.355ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.145ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.274ns (routing 0.670ns, distribution 1.604ns)
  Clock Net Delay (Destination): 1.963ns (routing 0.606ns, distribution 1.357ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.274     2.500    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X91Y153        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y153        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.581 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=287, routed)         4.554     7.135    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X69Y5          FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.963     2.145    d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X69Y5          FDRE                                         r  d_1_i/axi_dma_tproc/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.516ns  (logic 0.081ns (2.304%)  route 3.435ns (97.696%))
  Logic Levels:           0  
  Clock Path Skew:        -0.337ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.163ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.274ns (routing 0.670ns, distribution 1.604ns)
  Clock Net Delay (Destination): 1.981ns (routing 0.606ns, distribution 1.375ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.274     2.500    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X91Y153        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y153        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.581 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=287, routed)         3.435     6.016    d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X75Y47         FDRE                                         r  d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.981     2.163    d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X75Y47         FDRE                                         r  d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.343ns  (logic 0.081ns (2.423%)  route 3.262ns (97.577%))
  Logic Levels:           0  
  Clock Path Skew:        -0.423ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.077ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.274ns (routing 0.670ns, distribution 1.604ns)
  Clock Net Delay (Destination): 1.895ns (routing 0.606ns, distribution 1.289ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.274     2.500    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X91Y153        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y153        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.581 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=287, routed)         3.262     5.843    d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST_OUT/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X37Y33         FDRE                                         r  d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.895     2.077    d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST_OUT/s_axi_lite_aclk
    SLICE_X37Y33         FDRE                                         r  d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.221ns  (logic 0.081ns (2.515%)  route 3.140ns (97.485%))
  Logic Levels:           0  
  Clock Path Skew:        -0.444ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.056ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.274ns (routing 0.670ns, distribution 1.604ns)
  Clock Net Delay (Destination): 1.874ns (routing 0.606ns, distribution 1.268ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.274     2.500    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X91Y153        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y153        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.581 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=287, routed)         3.140     5.721    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X59Y45         FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.874     2.056    d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X59Y45         FDRE                                         r  d_1_i/axi_dma_mr/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.079ns  (logic 0.081ns (2.630%)  route 2.998ns (97.370%))
  Logic Levels:           0  
  Clock Path Skew:        -0.458ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.042ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.274ns (routing 0.670ns, distribution 1.604ns)
  Clock Net Delay (Destination): 1.860ns (routing 0.606ns, distribution 1.254ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.274     2.500    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X91Y153        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y153        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.581 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=287, routed)         2.998     5.579    d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X52Y43         FDRE                                         r  d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.860     2.042    d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST/s_axi_lite_aclk
    SLICE_X52Y43         FDRE                                         r  d_1_i/axi_dma_avg/U0/I_RST_MODULE/REG_HRD_RST/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        2.981ns  (logic 0.081ns (2.717%)  route 2.900ns (97.283%))
  Logic Levels:           0  
  Clock Path Skew:        -0.413ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.087ns
    Source Clock Delay      (SCD):    2.500ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.274ns (routing 0.670ns, distribution 1.604ns)
  Clock Net Delay (Destination): 1.905ns (routing 0.606ns, distribution 1.299ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.274     2.500    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X91Y153        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y153        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.081     2.581 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_replica/Q
                         net (fo=287, routed)         2.900     5.481    d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST_OUT/peripheral_aresetn[0]_bufg_place_replica
    SLICE_X34Y28         FDRE                                         r  d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.905     2.087    d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST_OUT/s_axi_lite_aclk
    SLICE_X34Y28         FDRE                                         r  d_1_i/axi_dma_buf/U0/I_RST_MODULE/REG_HRD_RST_OUT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m22_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.939ns  (logic 0.107ns (3.641%)  route 2.832ns (96.359%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.388ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.125ns
    Source Clock Delay      (SCD):    2.513ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.287ns (routing 0.670ns, distribution 1.617ns)
  Clock Net Delay (Destination): 1.943ns (routing 0.606ns, distribution 1.337ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.287     2.513    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y157        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y157        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.592 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.052     3.644    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y92         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.672 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=18133, routed)       1.780     5.452    d_1_i/ps8_0_axi_periph/m22_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    SLICE_X31Y10         FDPE                                         f  d_1_i/ps8_0_axi_periph/m22_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.943     2.125    d_1_i/ps8_0_axi_periph/m22_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
    SLICE_X31Y10         FDPE                                         r  d_1_i/ps8_0_axi_periph/m22_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m22_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.939ns  (logic 0.107ns (3.641%)  route 2.832ns (96.359%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.388ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.125ns
    Source Clock Delay      (SCD):    2.513ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.287ns (routing 0.670ns, distribution 1.617ns)
  Clock Net Delay (Destination): 1.943ns (routing 0.606ns, distribution 1.337ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.287     2.513    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y157        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y157        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.592 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.052     3.644    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y92         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.672 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=18133, routed)       1.780     5.452    d_1_i/ps8_0_axi_periph/m22_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    SLICE_X31Y10         FDPE                                         f  d_1_i/ps8_0_axi_periph/m22_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.943     2.125    d_1_i/ps8_0_axi_periph/m22_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
    SLICE_X31Y10         FDPE                                         r  d_1_i/ps8_0_axi_periph/m22_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/cmd_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ps8_0_axi_periph/m19_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE
                            (recovery check against rising-edge clock clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.937ns  (logic 0.107ns (3.643%)  route 2.830ns (96.357%))
  Logic Levels:           1  (BUFGCE=1)
  Clock Path Skew:        -0.399ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.114ns
    Source Clock Delay      (SCD):    2.513ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.287ns (routing 0.670ns, distribution 1.617ns)
  Clock Net Delay (Destination): 1.932ns (routing 0.606ns, distribution 1.326ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.287     2.513    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X92Y157        FDRE                                         r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y157        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.592 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N/Q
                         net (fo=1, routed)           1.052     3.644    d_1_i/rst_100/U0/peripheral_aresetn[0]_bufg_place
    BUFGCE_X0Y92         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     3.672 r  d_1_i/rst_100/U0/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_bufg_place/O
                         net (fo=18133, routed)       1.778     5.450    d_1_i/ps8_0_axi_periph/m19_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/src_arst
    SLICE_X24Y31         FDPE                                         f  d_1_i/ps8_0_axi_periph/m19_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/PRE  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.932     2.114    d_1_i/ps8_0_axi_periph/m19_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/dest_clk
    SLICE_X24Y31         FDPE                                         r  d_1_i/ps8_0_axi_periph/m19_couplers/auto_ds/inst/gen_downsizer.gen_simple_downsizer.axi_downsizer_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/inst/fifo_gen_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.g7serrst.gnsckt_wrst.rst_wr_reg2_inst/arststages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.093ns  (logic 0.039ns (42.157%)  route 0.054ns (57.843%))
  Logic Levels:           0  
  Clock Path Skew:        0.176ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.434ns
    Source Clock Delay      (SCD):    1.258ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.138ns (routing 0.363ns, distribution 0.775ns)
  Clock Net Delay (Destination): 1.287ns (routing 0.408ns, distribution 0.879ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.138     1.258    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X50Y89         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y89         FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     1.297 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.054     1.350    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X50Y89         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.287     1.434    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X50Y89         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.074ns  (logic 0.039ns (52.811%)  route 0.035ns (47.189%))
  Logic Levels:           0  
  Clock Path Skew:        0.176ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.456ns
    Source Clock Delay      (SCD):    1.280ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.160ns (routing 0.363ns, distribution 0.797ns)
  Clock Net Delay (Destination): 1.309ns (routing 0.408ns, distribution 0.901ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.160     1.280    d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X64Y143        FDRE                                         r  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X64Y143        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.319 r  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.035     1.354    d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X64Y143        FDRE                                         r  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.309     1.456    d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X64Y143        FDRE                                         r  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.039ns (38.735%)  route 0.062ns (61.265%))
  Logic Levels:           0  
  Clock Path Skew:        0.178ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.436ns
    Source Clock Delay      (SCD):    1.258ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.138ns (routing 0.363ns, distribution 0.775ns)
  Clock Net Delay (Destination): 1.289ns (routing 0.408ns, distribution 0.881ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.138     1.258    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X50Y89         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y89         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.297 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=35, routed)          0.062     1.358    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X50Y87         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.289     1.436    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X50Y87         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.039ns (31.963%)  route 0.083ns (68.037%))
  Logic Levels:           0  
  Clock Path Skew:        0.175ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.428ns
    Source Clock Delay      (SCD):    1.254ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.134ns (routing 0.363ns, distribution 0.771ns)
  Clock Net Delay (Destination): 1.281ns (routing 0.408ns, distribution 0.873ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.134     1.254    d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X52Y95         FDRE                                         r  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y95         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.293 r  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.083     1.376    d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X52Y95         FDRE                                         r  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.281     1.428    d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X52Y95         FDRE                                         r  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/RAMG/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.113ns  (logic 0.105ns (92.920%)  route 0.008ns (7.080%))
  Logic Levels:           0  
  Clock Path Skew:        0.167ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.435ns
    Source Clock Delay      (SCD):    1.268ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.148ns (routing 0.363ns, distribution 0.785ns)
  Clock Net Delay (Destination): 1.288ns (routing 0.408ns, distribution 0.880ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.148     1.268    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/WCLK
    SLICE_X46Y92         RAMD32                                       r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/RAMG/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y92         RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.105     1.373 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/RAMG/O
                         net (fo=1, routed)           0.008     1.381    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[12]
    SLICE_X46Y92         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.288     1.435    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X46Y92         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.038ns (29.835%)  route 0.089ns (70.165%))
  Logic Levels:           0  
  Clock Path Skew:        0.183ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.438ns
    Source Clock Delay      (SCD):    1.255ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.135ns (routing 0.363ns, distribution 0.772ns)
  Clock Net Delay (Destination): 1.291ns (routing 0.408ns, distribution 0.883ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.135     1.255    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/rd_clk
    SLICE_X41Y88         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y88         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.293 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_rd_rst_ic_reg/Q
                         net (fo=41, routed)          0.089     1.382    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/src_rst
    SLICE_X40Y88         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.291     1.438    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/dest_clk
    SLICE_X40Y88         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.RX_FIFO_II/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.rrst_wr_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_14_15__0/DP/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.113ns  (logic 0.105ns (92.920%)  route 0.008ns (7.080%))
  Logic Levels:           0  
  Clock Path Skew:        0.167ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.436ns
    Source Clock Delay      (SCD):    1.269ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.149ns (routing 0.363ns, distribution 0.786ns)
  Clock Net Delay (Destination): 1.289ns (routing 0.408ns, distribution 0.881ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.149     1.269    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_14_15__0/WCLK
    SLICE_X48Y92         RAMD32                                       r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_14_15__0/DP/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y92         RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.105     1.374 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_14_15__0/DP/O
                         net (fo=1, routed)           0.008     1.382    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[15]
    SLICE_X48Y92         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.289     1.436    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X48Y92         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[15]/C

Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.116ns  (logic 0.109ns (93.966%)  route 0.007ns (6.034%))
  Logic Levels:           0  
  Clock Path Skew:        0.169ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.437ns
    Source Clock Delay      (SCD):    1.268ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.148ns (routing 0.363ns, distribution 0.785ns)
  Clock Net Delay (Destination): 1.290ns (routing 0.408ns, distribution 0.882ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.148     1.268    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/WCLK
    SLICE_X46Y92         RAMD32                                       r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y92         RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.109     1.377 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/RAMA/O
                         net (fo=1, routed)           0.007     1.384    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[0]
    SLICE_X46Y92         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.290     1.437    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X46Y92         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.116ns  (logic 0.108ns (93.103%)  route 0.008ns (6.897%))
  Logic Levels:           0  
  Clock Path Skew:        0.167ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.435ns
    Source Clock Delay      (SCD):    1.268ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.148ns (routing 0.363ns, distribution 0.785ns)
  Clock Net Delay (Destination): 1.288ns (routing 0.408ns, distribution 0.880ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.148     1.268    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/WCLK
    SLICE_X46Y92         RAMD32                                       r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y92         RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.108     1.376 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/RAME/O
                         net (fo=1, routed)           0.008     1.384    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[8]
    SLICE_X46Y92         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.288     1.435    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X46Y92         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.118ns  (logic 0.110ns (93.220%)  route 0.008ns (6.780%))
  Logic Levels:           0  
  Clock Path Skew:        0.169ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.437ns
    Source Clock Delay      (SCD):    1.268ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.148ns (routing 0.363ns, distribution 0.785ns)
  Clock Net Delay (Destination): 1.290ns (routing 0.408ns, distribution 0.882ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.148     1.268    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/WCLK
    SLICE_X46Y92         RAMD32                                       r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X46Y92         RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.110     1.378 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_15_0_13/RAMB/O
                         net (fo=1, routed)           0.008     1.386    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[2]
    SLICE_X46Y92         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.290     1.437    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X46Y92         FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/FIFO_EXISTS.TX_FIFO_II/xpm_fifo_instance.xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout5
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Max Delay            94 Endpoints
Min Delay           102 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[12]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.071ns  (logic 0.079ns (7.379%)  route 0.992ns (92.621%))
  Logic Levels:           0  
  Clock Path Skew:        0.806ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.189ns
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.718ns (routing 0.968ns, distribution 0.750ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.992     3.453    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[12]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.718     3.189    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[12]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[13]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.071ns  (logic 0.079ns (7.379%)  route 0.992ns (92.621%))
  Logic Levels:           0  
  Clock Path Skew:        0.806ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.189ns
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.718ns (routing 0.968ns, distribution 0.750ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.992     3.453    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[13]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.718     3.189    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[13]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[14]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.071ns  (logic 0.079ns (7.379%)  route 0.992ns (92.621%))
  Logic Levels:           0  
  Clock Path Skew:        0.806ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.189ns
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.718ns (routing 0.968ns, distribution 0.750ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.992     3.453    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[14]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.718     3.189    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[14]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[15]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.071ns  (logic 0.079ns (7.379%)  route 0.992ns (92.621%))
  Logic Levels:           0  
  Clock Path Skew:        0.806ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.189ns
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.718ns (routing 0.968ns, distribution 0.750ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.992     3.453    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[15]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.718     3.189    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[15]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.071ns  (logic 0.079ns (7.379%)  route 0.992ns (92.621%))
  Logic Levels:           0  
  Clock Path Skew:        0.806ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.189ns
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.718ns (routing 0.968ns, distribution 0.750ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.992     3.453    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.718     3.189    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[20]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[21]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.071ns  (logic 0.079ns (7.379%)  route 0.992ns (92.621%))
  Logic Levels:           0  
  Clock Path Skew:        0.806ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.189ns
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.718ns (routing 0.968ns, distribution 0.750ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.992     3.453    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[21]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.718     3.189    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[21]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.071ns  (logic 0.079ns (7.379%)  route 0.992ns (92.621%))
  Logic Levels:           0  
  Clock Path Skew:        0.806ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.189ns
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.718ns (routing 0.968ns, distribution 0.750ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.992     3.453    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.718     3.189    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.071ns  (logic 0.079ns (7.379%)  route 0.992ns (92.621%))
  Logic Levels:           0  
  Clock Path Skew:        0.806ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.189ns
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.718ns (routing 0.968ns, distribution 0.750ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.992     3.453    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.718     3.189    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[16]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.070ns  (logic 0.079ns (7.386%)  route 0.991ns (92.614%))
  Logic Levels:           0  
  Clock Path Skew:        0.808ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.191ns
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.720ns (routing 0.968ns, distribution 0.752ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.991     3.452    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[16]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.720     3.191    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[16]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[17]/R
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.070ns  (logic 0.079ns (7.386%)  route 0.991ns (92.614%))
  Logic Levels:           0  
  Clock Path Skew:        0.808ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.191ns
    Source Clock Delay      (SCD):    2.383ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.276ns (routing 0.171ns, distribution 1.105ns)
  Clock Net Delay (Destination): 1.720ns (routing 0.968ns, distribution 0.752ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.235     1.079    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.107 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.276     2.383    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     2.462 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD1/ctl_reg_reg[0]/Q
                         net (fo=176, routed)         0.991     3.452    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/SR[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[17]/R
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.720     3.191    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[17]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.039ns (38.235%)  route 0.063ns (61.765%))
  Logic Levels:           0  
  Clock Path Skew:        4.897ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.528ns
    Source Clock Delay      (SCD):    1.631ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.713ns (routing 0.096ns, distribution 0.617ns)
  Clock Net Delay (Destination): 1.217ns (routing 0.658ns, distribution 0.559ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.713     1.631    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X103Y63        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y63        FDCE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     1.670 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[2]/Q
                         net (fo=1, routed)           0.063     1.733    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[2]
    SLICE_X103Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.217     6.528    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/wr_clk
    SLICE_X103Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.105ns  (logic 0.038ns (36.190%)  route 0.067ns (63.810%))
  Logic Levels:           0  
  Clock Path Skew:        4.896ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.527ns
    Source Clock Delay      (SCD):    1.631ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.713ns (routing 0.096ns, distribution 0.617ns)
  Clock Net Delay (Destination): 1.216ns (routing 0.658ns, distribution 0.558ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.713     1.631    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_clk
    SLICE_X103Y63        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y63        FDCE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.669 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.rd_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.067     1.736    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q[0]
    SLICE_X103Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.216     6.527    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/wr_clk
    SLICE_X103Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].wr_stg_inst/Q_reg_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.041ns (41.837%)  route 0.057ns (58.163%))
  Logic Levels:           0  
  Clock Path Skew:        4.890ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.532ns
    Source Clock Delay      (SCD):    1.642ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.724ns (routing 0.096ns, distribution 0.628ns)
  Clock Net Delay (Destination): 1.221ns (routing 0.658ns, distribution 0.563ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.724     1.642    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X106Y64        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y64        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.683 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.057     1.740    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X106Y63        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.221     6.532    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X106Y63        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        4.885ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.519ns
    Source Clock Delay      (SCD):    1.634ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.716ns (routing 0.096ns, distribution 0.620ns)
  Clock Net Delay (Destination): 1.208ns (routing 0.658ns, distribution 0.550ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.716     1.634    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/clk
    SLICE_X105Y73        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y73        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.674 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[3]/Q
                         net (fo=1, routed)           0.079     1.753    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg[3]
    SLICE_X105Y74        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.208     6.519    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X105Y74        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[3]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        4.886ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.524ns
    Source Clock Delay      (SCD):    1.639ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.720ns (routing 0.096ns, distribution 0.624ns)
  Clock Net Delay (Destination): 1.213ns (routing 0.658ns, distribution 0.555ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.720     1.639    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/clk
    SLICE_X105Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y71        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.679 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[2]/Q
                         net (fo=1, routed)           0.079     1.758    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg[2]
    SLICE_X105Y72        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.213     6.524    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X105Y72        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        4.881ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.521ns
    Source Clock Delay      (SCD):    1.640ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.722ns (routing 0.096ns, distribution 0.626ns)
  Clock Net Delay (Destination): 1.210ns (routing 0.658ns, distribution 0.552ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.722     1.640    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X106Y73        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y73        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.680 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[0]/Q
                         net (fo=1, routed)           0.079     1.759    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[0]
    SLICE_X106Y74        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.210     6.521    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X106Y74        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.040ns (33.613%)  route 0.079ns (66.387%))
  Logic Levels:           0  
  Clock Path Skew:        4.878ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.520ns
    Source Clock Delay      (SCD):    1.642ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.724ns (routing 0.096ns, distribution 0.628ns)
  Clock Net Delay (Destination): 1.209ns (routing 0.658ns, distribution 0.551ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.724     1.642    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/clk
    SLICE_X105Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y69        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.682 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_reg[0]/Q
                         net (fo=1, routed)           0.079     1.761    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg[0]
    SLICE_X105Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.209     6.520    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X105Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.039ns (32.500%)  route 0.081ns (67.500%))
  Logic Levels:           0  
  Clock Path Skew:        4.883ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.524ns
    Source Clock Delay      (SCD):    1.641ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.723ns (routing 0.096ns, distribution 0.627ns)
  Clock Net Delay (Destination): 1.213ns (routing 0.658ns, distribution 0.555ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.723     1.641    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X106Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y62        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.680 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.081     1.761    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X106Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.213     6.524    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X106Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_RD/U_RD_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_rdfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        4.890ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.531ns
    Source Clock Delay      (SCD):    1.641ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.723ns (routing 0.096ns, distribution 0.627ns)
  Clock Net Delay (Destination): 1.220ns (routing 0.658ns, distribution 0.562ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.723     1.641    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X107Y74        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y74        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.680 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[1]/Q
                         net (fo=1, routed)           0.085     1.765    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[1]
    SLICE_X107Y75        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.220     6.531    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X107Y75        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.039ns (31.452%)  route 0.085ns (68.548%))
  Logic Levels:           0  
  Clock Path Skew:        4.890ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    6.531ns
    Source Clock Delay      (SCD):    1.641ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.723ns (routing 0.096ns, distribution 0.627ns)
  Clock Net Delay (Destination): 1.220ns (routing 0.658ns, distribution 0.562ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.723     1.641    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/clk
    SLICE_X107Y72        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X107Y72        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.680 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_reg[2]/Q
                         net (fo=1, routed)           0.085     1.765    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg[2]
    SLICE_X107Y73        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.220     6.531    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/m_bscan_tck[0]
    SLICE_X107Y73        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_STAT/stat_reg_1_reg[2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  default_sysclk_c0_300mhz_clk_p

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
                            (recovery check against rising-edge clock default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.661ns  (logic 0.079ns (11.952%)  route 0.582ns (88.048%))
  Logic Levels:           0  
  Clock Path Skew:        -1.051ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.458ns
    Source Clock Delay      (SCD):    2.509ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.283ns (routing 0.670ns, distribution 1.613ns)
  Clock Net Delay (Destination): 0.672ns (routing 0.001ns, distribution 0.671ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.283     2.509    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X91Y146        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y146        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.588 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.582     3.170    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X91Y118        FDPE                                         f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     0.762    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.786 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.672     1.458    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y118        FDPE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
                            (recovery check against rising-edge clock default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        0.661ns  (logic 0.079ns (11.952%)  route 0.582ns (88.048%))
  Logic Levels:           0  
  Clock Path Skew:        -1.051ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    1.458ns
    Source Clock Delay      (SCD):    2.509ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.283ns (routing 0.670ns, distribution 1.613ns)
  Clock Net Delay (Destination): 0.672ns (routing 0.001ns, distribution 0.671ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.283     2.509    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X91Y146        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y146        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.588 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.582     3.170    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X91Y118        FDPE                                         f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     0.762    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.786 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.672     1.458    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y118        FDPE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
                            (removal check against rising-edge clock default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.328ns  (logic 0.039ns (11.890%)  route 0.289ns (88.110%))
  Logic Levels:           0  
  Clock Path Skew:        -0.202ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.174ns
    Source Clock Delay      (SCD):    1.376ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.256ns (routing 0.363ns, distribution 0.893ns)
  Clock Net Delay (Destination): 0.494ns (routing 0.001ns, distribution 0.493ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.256     1.376    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X91Y146        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y146        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.415 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.289     1.704    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X91Y118        FDPE                                         f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.494     1.174    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y118        FDPE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
                            (removal check against rising-edge clock default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.328ns  (logic 0.039ns (11.890%)  route 0.289ns (88.110%))
  Logic Levels:           0  
  Clock Path Skew:        -0.202ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.174ns
    Source Clock Delay      (SCD):    1.376ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.130ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.256ns (routing 0.363ns, distribution 0.893ns)
  Clock Net Delay (Destination): 0.494ns (routing 0.001ns, distribution 0.493ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.256     1.376    d_1_i/rst_100/U0/slowest_sync_clk
    SLICE_X91Y146        FDRE                                         r  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y146        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.415 f  d_1_i/rst_100/U0/BSR_OUT_DFF[0].FDRE_BSR/Q
                         net (fo=2, routed)           0.289     1.704    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_rst
    SLICE_X91Y118        FDPE                                         f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/PRE
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.494     1.174    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X91Y118        FDPE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_input_async_reg[1]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFADC2_CLK
  To Clock:  mmcm_clkout0

Max Delay           262 Endpoints
Min Delay           262 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[131]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.971ns  (logic 0.307ns (31.617%)  route 0.664ns (68.383%))
  Logic Levels:           0  
  Clock Path Skew:        0.186ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.035ns
    Source Clock Delay      (SCD):    2.849ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.323ns (routing 0.888ns, distribution 1.435ns)
  Clock Net Delay (Destination): 1.355ns (routing 0.379ns, distribution 0.976ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.323     2.849    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/WCLK
    SLICE_X103Y122       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y122       RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.307     3.156 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMC_D1/O
                         net (fo=1, routed)           0.664     3.820    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[131]
    SLICE_X103Y123       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[131]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.355     3.035    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X103Y123       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[131]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[183]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.951ns  (logic 0.305ns (32.071%)  route 0.646ns (67.928%))
  Logic Levels:           0  
  Clock Path Skew:        0.184ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.029ns
    Source Clock Delay      (SCD):    2.845ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.319ns (routing 0.888ns, distribution 1.431ns)
  Clock Net Delay (Destination): 1.349ns (routing 0.379ns, distribution 0.970ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.319     2.845    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/WCLK
    SLICE_X99Y122        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y122        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     3.150 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/RAMA_D1/O
                         net (fo=1, routed)           0.646     3.796    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[183]
    SLICE_X100Y122       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[183]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.349     3.029    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X100Y122       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[183]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAME/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[204]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.918ns  (logic 0.288ns (31.373%)  route 0.630ns (68.627%))
  Logic Levels:           0  
  Clock Path Skew:        0.129ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.991ns
    Source Clock Delay      (SCD):    2.862ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.336ns (routing 0.888ns, distribution 1.448ns)
  Clock Net Delay (Destination): 1.311ns (routing 0.379ns, distribution 0.932ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.336     2.862    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/WCLK
    SLICE_X99Y118        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAME/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y118        RAMD32 (Prop_E5LUT_SLICEM_CLK_O)
                                                      0.288     3.150 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_196_209/RAME/O
                         net (fo=1, routed)           0.630     3.780    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[204]
    SLICE_X101Y117       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[204]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.311     2.991    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X101Y117       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[204]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[114]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.910ns  (logic 0.292ns (32.088%)  route 0.618ns (67.912%))
  Logic Levels:           0  
  Clock Path Skew:        0.125ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.991ns
    Source Clock Delay      (SCD):    2.866ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.340ns (routing 0.888ns, distribution 1.452ns)
  Clock Net Delay (Destination): 1.311ns (routing 0.379ns, distribution 0.932ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.340     2.866    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/WCLK
    SLICE_X103Y119       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y119       RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     3.158 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMB/O
                         net (fo=1, routed)           0.618     3.776    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[114]
    SLICE_X102Y116       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[114]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.311     2.991    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X102Y116       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[114]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[189]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.914ns  (logic 0.301ns (32.932%)  route 0.613ns (67.068%))
  Logic Levels:           0  
  Clock Path Skew:        0.076ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.921ns
    Source Clock Delay      (SCD):    2.845ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.319ns (routing 0.888ns, distribution 1.431ns)
  Clock Net Delay (Destination): 1.241ns (routing 0.379ns, distribution 0.862ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.319     2.845    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/WCLK
    SLICE_X99Y122        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y122        RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.301     3.146 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_182_195/RAMD_D1/O
                         net (fo=1, routed)           0.613     3.759    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[189]
    SLICE_X96Y118        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[189]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.241     2.921    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X96Y118        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[189]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMD_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[105]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.908ns  (logic 0.301ns (33.150%)  route 0.607ns (66.850%))
  Logic Levels:           0  
  Clock Path Skew:        0.187ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.035ns
    Source Clock Delay      (SCD):    2.848ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.322ns (routing 0.888ns, distribution 1.434ns)
  Clock Net Delay (Destination): 1.355ns (routing 0.379ns, distribution 0.976ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.322     2.848    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/WCLK
    SLICE_X103Y127       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMD_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y127       RAMD32 (Prop_D6LUT_SLICEM_CLK_O)
                                                      0.301     3.149 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_98_111/RAMD_D1/O
                         net (fo=1, routed)           0.607     3.756    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[105]
    SLICE_X103Y126       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[105]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.355     3.035    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X103Y126       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[105]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/RAMF/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[220]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.906ns  (logic 0.295ns (32.561%)  route 0.611ns (67.439%))
  Logic Levels:           0  
  Clock Path Skew:        0.135ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.984ns
    Source Clock Delay      (SCD):    2.849ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.323ns (routing 0.888ns, distribution 1.435ns)
  Clock Net Delay (Destination): 1.304ns (routing 0.379ns, distribution 0.925ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.323     2.849    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/WCLK
    SLICE_X103Y121       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/RAMF/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y121       RAMD32 (Prop_F5LUT_SLICEM_CLK_O)
                                                      0.295     3.144 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_210_223/RAMF/O
                         net (fo=1, routed)           0.611     3.755    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[220]
    SLICE_X102Y119       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[220]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.304     2.984    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X102Y119       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[220]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[113]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.888ns  (logic 0.305ns (34.347%)  route 0.583ns (65.653%))
  Logic Levels:           0  
  Clock Path Skew:        0.125ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.991ns
    Source Clock Delay      (SCD):    2.866ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.340ns (routing 0.888ns, distribution 1.452ns)
  Clock Net Delay (Destination): 1.311ns (routing 0.379ns, distribution 0.932ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.340     2.866    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/WCLK
    SLICE_X103Y119       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y119       RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     3.171 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_112_125/RAMA_D1/O
                         net (fo=1, routed)           0.583     3.754    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[113]
    SLICE_X102Y116       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[113]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.311     2.991    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X102Y116       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[113]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[144]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.886ns  (logic 0.288ns (32.506%)  route 0.598ns (67.494%))
  Logic Levels:           0  
  Clock Path Skew:        0.114ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.982ns
    Source Clock Delay      (SCD):    2.868ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.342ns (routing 0.888ns, distribution 1.454ns)
  Clock Net Delay (Destination): 1.302ns (routing 0.379ns, distribution 0.923ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.342     2.868    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/WCLK
    SLICE_X99Y120        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y120        RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.288     3.156 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_140_153/RAMC/O
                         net (fo=1, routed)           0.598     3.754    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[144]
    SLICE_X100Y118       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[144]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.302     2.982    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X100Y118       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[144]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[57]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.889ns  (logic 0.305ns (34.308%)  route 0.584ns (65.692%))
  Logic Levels:           0  
  Clock Path Skew:        0.175ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.030ns
    Source Clock Delay      (SCD):    2.855ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.329ns (routing 0.888ns, distribution 1.441ns)
  Clock Net Delay (Destination): 1.350ns (routing 0.379ns, distribution 0.971ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.150     0.150 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.246     0.396    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.526 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       2.329     2.855    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/WCLK
    SLICE_X99Y125        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y125        RAMD32 (Prop_A6LUT_SLICEM_CLK_O)
                                                      0.305     3.160 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_56_69/RAMA_D1/O
                         net (fo=1, routed)           0.584     3.744    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[57]
    SLICE_X99Y123        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[57]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.350     3.030    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X99Y123        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[57]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.039ns (31.200%)  route 0.086ns (68.800%))
  Logic Levels:           0  
  Clock Path Skew:        -0.012ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.509ns
    Source Clock Delay      (SCD):    1.521ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.259ns (routing 0.485ns, distribution 0.774ns)
  Clock Net Delay (Destination): 0.946ns (routing 0.255ns, distribution 0.691ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.259     1.521    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X100Y125       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y125       FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.560 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q
                         net (fo=1, routed)           0.086     1.646    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[1]
    SLICE_X100Y125       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.946     1.509    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X100Y125       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.233%)  route 0.090ns (69.767%))
  Logic Levels:           0  
  Clock Path Skew:        -0.014ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.511ns
    Source Clock Delay      (SCD):    1.525ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.263ns (routing 0.485ns, distribution 0.778ns)
  Clock Net Delay (Destination): 0.948ns (routing 0.255ns, distribution 0.693ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.263     1.525    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X102Y126       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y126       FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.564 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q
                         net (fo=1, routed)           0.090     1.654    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[3]
    SLICE_X102Y126       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.948     1.511    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X102Y126       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.147ns  (logic 0.039ns (26.528%)  route 0.108ns (73.472%))
  Logic Levels:           0  
  Clock Path Skew:        -0.011ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.509ns
    Source Clock Delay      (SCD):    1.520ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.258ns (routing 0.485ns, distribution 0.773ns)
  Clock Net Delay (Destination): 0.946ns (routing 0.255ns, distribution 0.691ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.258     1.520    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/wr_clk
    SLICE_X100Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X100Y128       FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.559 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.fifo_wr_rst_ic_reg/Q
                         net (fo=2, routed)           0.108     1.667    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/src_rst
    SLICE_X100Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.946     1.509    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/dest_clk
    SLICE_X100Y128       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/xpm_fifo_rst_inst/gen_rst_ic.wrst_rd_inst/syncstages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[39]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.170ns  (logic 0.111ns (65.294%)  route 0.059ns (34.706%))
  Logic Levels:           0  
  Clock Path Skew:        -0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.476ns
    Source Clock Delay      (SCD):    1.502ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.240ns (routing 0.485ns, distribution 0.755ns)
  Clock Net Delay (Destination): 0.913ns (routing 0.255ns, distribution 0.658ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.240     1.502    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X96Y121        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y121        RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     1.613 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMF_D1/O
                         net (fo=1, routed)           0.059     1.672    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[39]
    SLICE_X96Y122        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[39]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.913     1.476    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X96Y122        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[39]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.151ns  (logic 0.039ns (25.828%)  route 0.112ns (74.172%))
  Logic Levels:           0  
  Clock Path Skew:        -0.005ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.516ns
    Source Clock Delay      (SCD):    1.521ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.259ns (routing 0.485ns, distribution 0.774ns)
  Clock Net Delay (Destination): 0.953ns (routing 0.255ns, distribution 0.698ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.259     1.521    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_clk
    SLICE_X103Y129       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y129       FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.039     1.560 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/src_gray_ff_reg[4]/Q
                         net (fo=1, routed)           0.112     1.672    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/async_path[4]
    SLICE_X103Y129       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.953     1.516    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_clk
    SLICE_X103Y129       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_cdc_pntr.wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_252_255/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[253]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.185ns  (logic 0.108ns (58.378%)  route 0.077ns (41.622%))
  Logic Levels:           0  
  Clock Path Skew:        -0.031ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.475ns
    Source Clock Delay      (SCD):    1.506ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.244ns (routing 0.485ns, distribution 0.759ns)
  Clock Net Delay (Destination): 0.912ns (routing 0.255ns, distribution 0.657ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.244     1.506    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_252_255/WCLK
    SLICE_X96Y127        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_252_255/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y127        RAMD32 (Prop_E6LUT_SLICEM_CLK_O)
                                                      0.108     1.614 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_252_255/RAMA_D1/O
                         net (fo=1, routed)           0.077     1.691    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[253]
    SLICE_X96Y125        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[253]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.912     1.475    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X96Y125        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[253]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[33]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.197ns  (logic 0.110ns (55.838%)  route 0.087ns (44.162%))
  Logic Levels:           0  
  Clock Path Skew:        -0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.476ns
    Source Clock Delay      (SCD):    1.502ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.240ns (routing 0.485ns, distribution 0.755ns)
  Clock Net Delay (Destination): 0.913ns (routing 0.255ns, distribution 0.658ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.240     1.502    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X96Y121        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y121        RAMD32 (Prop_C6LUT_SLICEM_CLK_O)
                                                      0.110     1.612 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMC_D1/O
                         net (fo=1, routed)           0.087     1.699    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[33]
    SLICE_X96Y122        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[33]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.913     1.476    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X96Y122        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[33]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[46]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.197ns  (logic 0.112ns (56.853%)  route 0.085ns (43.147%))
  Logic Levels:           0  
  Clock Path Skew:        -0.027ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.475ns
    Source Clock Delay      (SCD):    1.502ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.240ns (routing 0.485ns, distribution 0.755ns)
  Clock Net Delay (Destination): 0.912ns (routing 0.255ns, distribution 0.657ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.240     1.502    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/WCLK
    SLICE_X96Y126        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y126        RAMD32 (Prop_C5LUT_SLICEM_CLK_O)
                                                      0.112     1.614 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_55/RAMC/O
                         net (fo=1, routed)           0.085     1.699    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[46]
    SLICE_X96Y125        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[46]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.912     1.475    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X96Y125        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[46]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[28]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.200ns  (logic 0.109ns (54.500%)  route 0.091ns (45.500%))
  Logic Levels:           0  
  Clock Path Skew:        -0.026ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.476ns
    Source Clock Delay      (SCD):    1.502ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.240ns (routing 0.485ns, distribution 0.755ns)
  Clock Net Delay (Destination): 0.913ns (routing 0.255ns, distribution 0.658ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.240     1.502    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/WCLK
    SLICE_X96Y121        RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y121        RAMD32 (Prop_A5LUT_SLICEM_CLK_O)
                                                      0.109     1.611 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_28_41/RAMA/O
                         net (fo=1, routed)           0.091     1.702    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[28]
    SLICE_X96Y122        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[28]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.913     1.476    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X96Y122        FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[28]/C

Slack:                    inf
  Source:                 d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMF_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by RFADC2_CLK  {rise@0.000ns fall@1.628ns period=3.255ns})
  Destination:            d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[137]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.170ns  (logic 0.111ns (65.294%)  route 0.059ns (34.706%))
  Logic Levels:           0  
  Clock Path Skew:        -0.012ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.528ns
    Source Clock Delay      (SCD):    1.540ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.278ns (routing 0.485ns, distribution 0.793ns)
  Clock Net Delay (Destination): 0.966ns (routing 0.255ns, distribution 0.711ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFADC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/INTERNAL_FBRC_DIV1_MUX
    RFADC_X0Y2           RFADC (Prop_RFADC_INTERNAL_FBRC_DIV1_MUX_CLK_ADC)
                                                      0.079     0.079 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/CLK_ADC
                         net (fo=2, routed)           0.110     0.189    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt_0
    BUFG_GT_X1Y50        BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.262 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/adc2_bufg_gt/O
    X3Y2 (CLOCK_ROOT)    net (fo=41946, routed)       1.278     1.540    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/WCLK
    SLICE_X103Y122       RAMD32                                       r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMF_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y122       RAMD32 (Prop_F6LUT_SLICEM_CLK_O)
                                                      0.111     1.651 r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_126_139/RAMF_D1/O
                         net (fo=1, routed)           0.059     1.710    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg0[137]
    SLICE_X102Y122       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[137]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.966     1.528    d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/clkb
    SLICE_X102Y122       FDRE                                         r  d_1_i/axis_clock_converter_0/inst/gen_async_conv.axisc_async_clock_converter_0/xpm_fifo_async_inst/gnuram_async_fifo.xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_rd_b.doutb_reg_reg[137]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  RFDAC2_CLK
  To Clock:  mmcm_clkout0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.642ns  (logic 0.077ns (4.689%)  route 1.565ns (95.311%))
  Logic Levels:           0  
  Clock Path Skew:        -0.536ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.090ns
    Source Clock Delay      (SCD):    3.626ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.915ns (routing 1.474ns, distribution 1.441ns)
  Clock Net Delay (Destination): 1.410ns (routing 0.379ns, distribution 1.031ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.336     0.336 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.245     0.581    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.130     0.711 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       2.915     3.626    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X54Y222        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y222        FDCE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     3.703 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/Q
                         net (fo=2, routed)           1.565     5.268    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/trigger
    SLICE_X66Y63         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.410     3.090    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/aclk
    SLICE_X66Y63         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
                            (rising edge-triggered cell FDCE clocked by RFDAC2_CLK  {rise@0.000ns fall@1.018ns period=2.035ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.829ns  (logic 0.039ns (4.706%)  route 0.790ns (95.294%))
  Logic Levels:           0  
  Clock Path Skew:        -0.406ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.555ns
    Source Clock Delay      (SCD):    1.961ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.594ns (routing 0.796ns, distribution 0.798ns)
  Clock Net Delay (Destination): 0.992ns (routing 0.255ns, distribution 0.737ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock RFDAC2_CLK rise edge)
                                                      0.000     0.000 r  
    RFDAC_X0Y2           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/INTERNAL_FBRC_MUX
    RFDAC_X0Y2           RFDAC (Prop_RFDAC_INTERNAL_FBRC_MUX_CLK_DAC)
                                                      0.184     0.184 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/CLK_DAC
                         net (fo=2, routed)           0.110     0.294    d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt_0
    BUFG_GT_X1Y154       BUFG_GT (Prop_BUFG_GT_I_O)
                                                      0.073     0.367 r  d_1_i/usp_rf_data_converter_0/inst/i_d_1_usp_rf_data_converter_0_0_bufg_gt_ctrl/dac2_bufg_gt/O
    X3Y4 (CLOCK_ROOT)    net (fo=87498, routed)       1.594     1.961    d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/t_clk_i
    SLICE_X54Y222        FDCE                                         r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y222        FDCE (Prop_CFF2_SLICEM_C_Q)
                                                      0.039     2.000 r  d_1_i/qick_processor_0/inst/QPROC/DISPATCHER/port_trig_r_reg[7]/Q
                         net (fo=2, routed)           0.790     2.790    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/trigger
    SLICE_X66Y63         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.992     1.555    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/aclk
    SLICE_X66Y63         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/trigger_resync_i/data_int_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  mmcm_clkout0

Max Delay           106 Endpoints
Min Delay           106 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.043ns  (logic 0.079ns (7.574%)  route 0.964ns (92.426%))
  Logic Levels:           0  
  Clock Path Skew:        0.738ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.077ns
    Source Clock Delay      (SCD):    2.339ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.113ns (routing 0.670ns, distribution 1.443ns)
  Clock Net Delay (Destination): 1.397ns (routing 0.379ns, distribution 1.018ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.113     2.339    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X55Y30         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X55Y30         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.079     2.418 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[0]/Q
                         net (fo=2, routed)           0.964     3.382    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[0]
    SLICE_X72Y32         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.397     3.077    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X72Y32         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.887ns  (logic 0.080ns (9.015%)  route 0.807ns (90.985%))
  Logic Levels:           0  
  Clock Path Skew:        0.844ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.158ns
    Source Clock Delay      (SCD):    2.314ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.088ns (routing 0.670ns, distribution 1.418ns)
  Clock Net Delay (Destination): 1.478ns (routing 0.379ns, distribution 1.099ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.088     2.314    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X51Y25         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y25         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     2.394 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[9]/Q
                         net (fo=2, routed)           0.807     3.202    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[9]
    SLICE_X52Y26         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.478     3.158    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X52Y26         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[9]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.851ns  (logic 0.078ns (9.160%)  route 0.773ns (90.840%))
  Logic Levels:           0  
  Clock Path Skew:        0.773ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.100ns
    Source Clock Delay      (SCD):    2.327ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.101ns (routing 0.670ns, distribution 1.431ns)
  Clock Net Delay (Destination): 1.420ns (routing 0.379ns, distribution 1.041ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.101     2.327    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X56Y25         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y25         FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.078     2.405 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[20]/Q
                         net (fo=2, routed)           0.773     3.179    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[20]
    SLICE_X61Y42         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.420     3.100    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X61Y42         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[20]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.819ns  (logic 0.079ns (9.645%)  route 0.740ns (90.355%))
  Logic Levels:           0  
  Clock Path Skew:        0.767ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.077ns
    Source Clock Delay      (SCD):    2.310ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.084ns (routing 0.670ns, distribution 1.414ns)
  Clock Net Delay (Destination): 1.397ns (routing 0.379ns, distribution 1.018ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.084     2.310    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X52Y32         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y32         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.389 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[1]/Q
                         net (fo=2, routed)           0.740     3.129    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[1]
    SLICE_X72Y32         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.397     3.077    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X72Y32         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.792ns  (logic 0.078ns (9.848%)  route 0.714ns (90.152%))
  Logic Levels:           0  
  Clock Path Skew:        0.756ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.081ns
    Source Clock Delay      (SCD):    2.325ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.099ns (routing 0.670ns, distribution 1.429ns)
  Clock Net Delay (Destination): 1.401ns (routing 0.379ns, distribution 1.022ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.099     2.325    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X53Y24         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y24         FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.078     2.403 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[14]/Q
                         net (fo=2, routed)           0.714     3.117    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[14]
    SLICE_X75Y39         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.401     3.081    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X75Y39         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.779ns  (logic 0.079ns (10.141%)  route 0.700ns (89.859%))
  Logic Levels:           0  
  Clock Path Skew:        0.756ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.081ns
    Source Clock Delay      (SCD):    2.325ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.099ns (routing 0.670ns, distribution 1.429ns)
  Clock Net Delay (Destination): 1.401ns (routing 0.379ns, distribution 1.022ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.099     2.325    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X53Y24         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y24         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.404 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[8]/Q
                         net (fo=2, routed)           0.700     3.104    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[8]
    SLICE_X75Y39         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.401     3.081    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X75Y39         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[26]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.768ns  (logic 0.078ns (10.150%)  route 0.690ns (89.850%))
  Logic Levels:           0  
  Clock Path Skew:        0.765ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.093ns
    Source Clock Delay      (SCD):    2.328ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.102ns (routing 0.670ns, distribution 1.432ns)
  Clock Net Delay (Destination): 1.413ns (routing 0.379ns, distribution 1.034ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.102     2.328    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X53Y23         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y23         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.078     2.406 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[26]/Q
                         net (fo=2, routed)           0.690     3.097    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[26]
    SLICE_X65Y39         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[26]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.413     3.093    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X65Y39         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[26]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.764ns  (logic 0.079ns (10.346%)  route 0.685ns (89.654%))
  Logic Levels:           0  
  Clock Path Skew:        0.768ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.087ns
    Source Clock Delay      (SCD):    2.319ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.093ns (routing 0.670ns, distribution 1.423ns)
  Clock Net Delay (Destination): 1.407ns (routing 0.379ns, distribution 1.028ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.093     2.319    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X53Y34         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y34         FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     2.398 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[6]/Q
                         net (fo=2, routed)           0.685     3.083    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[6]
    SLICE_X61Y31         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.407     3.087    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X61Y31         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[6]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.756ns  (logic 0.079ns (10.449%)  route 0.677ns (89.551%))
  Logic Levels:           0  
  Clock Path Skew:        0.737ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.062ns
    Source Clock Delay      (SCD):    2.325ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.099ns (routing 0.670ns, distribution 1.429ns)
  Clock Net Delay (Destination): 1.382ns (routing 0.379ns, distribution 1.003ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.099     2.325    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X53Y24         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y24         FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.079     2.404 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[11]/Q
                         net (fo=2, routed)           0.677     3.081    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[11]
    SLICE_X77Y29         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.382     3.062    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X77Y29         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[11]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[9]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.749ns  (logic 0.078ns (10.413%)  route 0.671ns (89.587%))
  Logic Levels:           0  
  Clock Path Skew:        0.754ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.079ns
    Source Clock Delay      (SCD):    2.325ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      2.099ns (routing 0.670ns, distribution 1.429ns)
  Clock Net Delay (Destination): 1.399ns (routing 0.379ns, distribution 1.020ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.099     2.325    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X53Y24         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X53Y24         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.078     2.403 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg4_reg[9]/Q
                         net (fo=2, routed)           0.671     3.074    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WADDR_REG[9]
    SLICE_X74Y40         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.399     3.079    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X74Y40         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/addr_reg_r_reg[9]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.041ns (33.110%)  route 0.083ns (66.890%))
  Logic Levels:           0  
  Clock Path Skew:        0.366ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.626ns
    Source Clock Delay      (SCD):    1.260ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.140ns (routing 0.363ns, distribution 0.777ns)
  Clock Net Delay (Destination): 1.063ns (routing 0.255ns, distribution 0.808ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.140     1.260    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y31         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y31         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.301 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[7]/Q
                         net (fo=2, routed)           0.083     1.384    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[7]
    SLICE_X49Y31         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.063     1.626    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X49Y31         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.125ns  (logic 0.040ns (32.081%)  route 0.085ns (67.919%))
  Logic Levels:           0  
  Clock Path Skew:        0.366ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.626ns
    Source Clock Delay      (SCD):    1.260ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.140ns (routing 0.363ns, distribution 0.777ns)
  Clock Net Delay (Destination): 1.063ns (routing 0.255ns, distribution 0.808ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.140     1.260    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y31         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y31         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.300 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[5]/Q
                         net (fo=2, routed)           0.085     1.385    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[5]
    SLICE_X49Y31         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.063     1.626    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X49Y31         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[5]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.129ns  (logic 0.039ns (30.307%)  route 0.090ns (69.693%))
  Logic Levels:           0  
  Clock Path Skew:        0.366ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.626ns
    Source Clock Delay      (SCD):    1.260ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.140ns (routing 0.363ns, distribution 0.777ns)
  Clock Net Delay (Destination): 1.063ns (routing 0.255ns, distribution 0.808ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.140     1.260    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X49Y31         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y31         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.299 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[0]/Q
                         net (fo=2, routed)           0.090     1.389    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[0]
    SLICE_X49Y31         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.063     1.626    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X49Y31         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.039ns (32.316%)  route 0.082ns (67.684%))
  Logic Levels:           0  
  Clock Path Skew:        0.363ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.634ns
    Source Clock Delay      (SCD):    1.271ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.151ns (routing 0.363ns, distribution 0.788ns)
  Clock Net Delay (Destination): 1.072ns (routing 0.255ns, distribution 0.817ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.151     1.271    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X48Y23         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[14]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y23         FDRE (Prop_GFF_SLICEM_C_Q)
                                                      0.039     1.310 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[14]/Q
                         net (fo=2, routed)           0.082     1.392    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[14]
    SLICE_X48Y25         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.072     1.634    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X48Y25         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[14]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.113ns  (logic 0.038ns (33.723%)  route 0.075ns (66.277%))
  Logic Levels:           0  
  Clock Path Skew:        0.324ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.603ns
    Source Clock Delay      (SCD):    1.279ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.159ns (routing 0.363ns, distribution 0.796ns)
  Clock Net Delay (Destination): 1.040ns (routing 0.255ns, distribution 0.785ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.159     1.279    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X54Y29         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y29         FDRE (Prop_CFF_SLICEM_C_Q)
                                                      0.038     1.317 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[20]/Q
                         net (fo=2, routed)           0.075     1.392    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[20]
    SLICE_X54Y29         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.040     1.603    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X54Y29         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[20]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.037ns (30.407%)  route 0.085ns (69.593%))
  Logic Levels:           0  
  Clock Path Skew:        0.363ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.634ns
    Source Clock Delay      (SCD):    1.271ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.151ns (routing 0.363ns, distribution 0.788ns)
  Clock Net Delay (Destination): 1.072ns (routing 0.255ns, distribution 0.817ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.151     1.271    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X48Y23         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y23         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     1.308 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[12]/Q
                         net (fo=2, routed)           0.085     1.393    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[12]
    SLICE_X48Y25         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.072     1.634    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X48Y25         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[12]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.039ns (32.050%)  route 0.083ns (67.950%))
  Logic Levels:           0  
  Clock Path Skew:        0.348ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.621ns
    Source Clock Delay      (SCD):    1.273ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.153ns (routing 0.363ns, distribution 0.790ns)
  Clock Net Delay (Destination): 1.058ns (routing 0.255ns, distribution 0.803ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.153     1.273    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X51Y25         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y25         FDRE (Prop_HFF_SLICEL_C_Q)
                                                      0.039     1.312 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg5_reg[8]/Q
                         net (fo=2, routed)           0.083     1.394    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/WNBURST_REG[8]
    SLICE_X51Y25         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.058     1.621    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/aclk
    SLICE_X51Y25         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_write_i/nburst_reg_r_reg[8]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[19]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.116ns  (logic 0.040ns (34.577%)  route 0.076ns (65.423%))
  Logic Levels:           0  
  Clock Path Skew:        0.328ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.607ns
    Source Clock Delay      (SCD):    1.279ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.159ns (routing 0.363ns, distribution 0.796ns)
  Clock Net Delay (Destination): 1.044ns (routing 0.255ns, distribution 0.789ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.159     1.279    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X54Y29         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[19]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y29         FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.040     1.319 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[19]/Q
                         net (fo=2, routed)           0.076     1.395    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[19]
    SLICE_X53Y29         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.044     1.607    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X53Y29         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[19]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.039ns (31.904%)  route 0.083ns (68.096%))
  Logic Levels:           0  
  Clock Path Skew:        0.341ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.614ns
    Source Clock Delay      (SCD):    1.273ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.153ns (routing 0.363ns, distribution 0.790ns)
  Clock Net Delay (Destination): 1.051ns (routing 0.255ns, distribution 0.796ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.153     1.273    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X50Y29         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y29         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.312 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg2_reg[7]/Q
                         net (fo=2, routed)           0.083     1.395    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RLENGTH_REG[7]
    SLICE_X50Y29         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.051     1.614    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X50Y29         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/len_reg_r_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[25]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.127ns  (logic 0.040ns (31.507%)  route 0.087ns (68.493%))
  Logic Levels:           0  
  Clock Path Skew:        0.355ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.625ns
    Source Clock Delay      (SCD):    1.270ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.352ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.150ns (routing 0.363ns, distribution 0.787ns)
  Clock Net Delay (Destination): 1.062ns (routing 0.255ns, distribution 0.807ns)
  Timing Exception:       Asynchronous Clock Groups

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.150     1.270    d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/s_axi_aclk
    SLICE_X50Y25         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y25         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.310 r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_slv_i/slv_reg1_reg[25]/Q
                         net (fo=2, routed)           0.087     1.396    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/RADDR_REG[25]
    SLICE_X50Y25         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[25]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.062     1.625    d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/aclk
    SLICE_X50Y25         FDRE                                         r  d_1_i/axis_buffer_ddr_v1_0/inst/axi_mst_i/axi_mst_read_i/addr_reg_r_reg[25]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  default_sysclk_c0_300mhz_clk_p
  To Clock:  mmcm_clkout0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.366ns  (logic 0.080ns (21.858%)  route 0.286ns (78.142%))
  Logic Levels:           0  
  Clock Path Skew:        1.220ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.922ns
    Source Clock Delay      (SCD):    1.702ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.769ns (routing 0.001ns, distribution 0.768ns)
  Clock Net Delay (Destination): 1.242ns (routing 0.379ns, distribution 0.863ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     0.905    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     0.933 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.769     1.702    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X89Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y79         FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     1.782 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.286     2.068    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X89Y80         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.242     2.922    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk_0
    SLICE_X89Y80         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.157ns  (logic 0.039ns (24.807%)  route 0.118ns (75.193%))
  Logic Levels:           0  
  Clock Path Skew:        0.485ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.448ns
    Source Clock Delay      (SCD):    0.962ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.161ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.434ns (routing 0.000ns, distribution 0.434ns)
  Clock Net Delay (Destination): 0.885ns (routing 0.255ns, distribution 0.630ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.511    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.528 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.434     0.962    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X89Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y79         FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.001 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.118     1.120    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X89Y80         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.885     1.448    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk_0
    SLICE_X89Y80         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_div_sync_r_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout0

Max Delay            68 Endpoints
Min Delay            68 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        4.091ns  (logic 0.078ns (1.907%)  route 4.013ns (98.093%))
  Logic Levels:           0  
  Clock Path Skew:        0.261ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.972ns
    Source Clock Delay      (SCD):    2.711ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.595ns (routing 0.415ns, distribution 1.180ns)
  Clock Net Delay (Destination): 1.292ns (routing 0.379ns, distribution 0.913ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.595     2.711    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.789 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          4.013     6.803    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X82Y146        FDCE                                         f  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.292     2.972    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X82Y146        FDCE                                         r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        4.091ns  (logic 0.078ns (1.907%)  route 4.013ns (98.093%))
  Logic Levels:           0  
  Clock Path Skew:        0.261ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.972ns
    Source Clock Delay      (SCD):    2.711ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.595ns (routing 0.415ns, distribution 1.180ns)
  Clock Net Delay (Destination): 1.292ns (routing 0.379ns, distribution 0.913ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.595     2.711    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.789 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          4.013     6.803    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X82Y146        FDCE                                         f  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.292     2.972    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X82Y146        FDCE                                         r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        4.091ns  (logic 0.078ns (1.907%)  route 4.013ns (98.093%))
  Logic Levels:           0  
  Clock Path Skew:        0.261ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.972ns
    Source Clock Delay      (SCD):    2.711ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.595ns (routing 0.415ns, distribution 1.180ns)
  Clock Net Delay (Destination): 1.292ns (routing 0.379ns, distribution 0.913ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.595     2.711    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.789 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          4.013     6.803    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X82Y146        FDCE                                         f  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.292     2.972    d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X82Y146        FDCE                                         r  d_1_i/axi_smc_1/inst/s00_nodes/s00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.866ns  (logic 0.078ns (2.018%)  route 3.788ns (97.982%))
  Logic Levels:           0  
  Clock Path Skew:        0.237ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.948ns
    Source Clock Delay      (SCD):    2.711ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.595ns (routing 0.415ns, distribution 1.180ns)
  Clock Net Delay (Destination): 1.268ns (routing 0.379ns, distribution 0.889ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.595     2.711    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.789 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.788     6.577    d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X83Y103        FDCE                                         f  d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.268     2.948    d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X83Y103        FDCE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.866ns  (logic 0.078ns (2.018%)  route 3.788ns (97.982%))
  Logic Levels:           0  
  Clock Path Skew:        0.237ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.948ns
    Source Clock Delay      (SCD):    2.711ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.595ns (routing 0.415ns, distribution 1.180ns)
  Clock Net Delay (Destination): 1.268ns (routing 0.379ns, distribution 0.889ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.595     2.711    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.789 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.788     6.577    d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X83Y103        FDCE                                         f  d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.268     2.948    d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X83Y103        FDCE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.866ns  (logic 0.078ns (2.018%)  route 3.788ns (97.982%))
  Logic Levels:           0  
  Clock Path Skew:        0.237ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.948ns
    Source Clock Delay      (SCD):    2.711ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.595ns (routing 0.415ns, distribution 1.180ns)
  Clock Net Delay (Destination): 1.268ns (routing 0.379ns, distribution 0.889ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.595     2.711    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.789 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.788     6.577    d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X83Y103        FDCE                                         f  d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.268     2.948    d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X83Y103        FDCE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.558ns  (logic 0.078ns (2.192%)  route 3.480ns (97.808%))
  Logic Levels:           0  
  Clock Path Skew:        0.238ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.950ns
    Source Clock Delay      (SCD):    2.711ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.595ns (routing 0.415ns, distribution 1.180ns)
  Clock Net Delay (Destination): 1.269ns (routing 0.379ns, distribution 0.890ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.595     2.711    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.789 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.480     6.270    d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X84Y78         FDCE                                         f  d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.269     2.950    d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X84Y78         FDCE                                         r  d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.558ns  (logic 0.078ns (2.192%)  route 3.480ns (97.808%))
  Logic Levels:           0  
  Clock Path Skew:        0.238ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.950ns
    Source Clock Delay      (SCD):    2.711ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.595ns (routing 0.415ns, distribution 1.180ns)
  Clock Net Delay (Destination): 1.269ns (routing 0.379ns, distribution 0.890ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.595     2.711    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.789 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.480     6.270    d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X84Y78         FDCE                                         f  d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.269     2.950    d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X84Y78         FDCE                                         r  d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        3.558ns  (logic 0.078ns (2.192%)  route 3.480ns (97.808%))
  Logic Levels:           0  
  Clock Path Skew:        0.238ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.950ns
    Source Clock Delay      (SCD):    2.711ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.595ns (routing 0.415ns, distribution 1.180ns)
  Clock Net Delay (Destination): 1.269ns (routing 0.379ns, distribution 0.890ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.595     2.711    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.789 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          3.480     6.270    d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X84Y78         FDCE                                         f  d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.269     2.950    d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X84Y78         FDCE                                         r  d_1_i/axi_smc_1/inst/m00_nodes/m00_w_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (recovery check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Recovery (Max at Slow Process Corner)
  Data Path Delay:        2.911ns  (logic 0.078ns (2.679%)  route 2.833ns (97.321%))
  Logic Levels:           0  
  Clock Path Skew:        0.379ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    3.090ns
    Source Clock Delay      (SCD):    2.711ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.595ns (routing 0.415ns, distribution 1.180ns)
  Clock Net Delay (Destination): 1.410ns (routing 0.379ns, distribution 1.031ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.595     2.711    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.078     2.789 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          2.833     5.622    d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X62Y85         FDCE                                         f  d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     1.656    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.410     3.090    d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X62Y85         FDCE                                         r  d_1_i/axi_smc_1/inst/m00_nodes/m00_aw_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/div_clk_rst_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.134ns  (logic 0.041ns (30.597%)  route 0.093ns (69.403%))
  Logic Levels:           0  
  Clock Path Skew:        -0.259ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.466ns
    Source Clock Delay      (SCD):    1.725ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.798ns (routing 0.230ns, distribution 0.568ns)
  Clock Net Delay (Destination): 0.903ns (routing 0.255ns, distribution 0.648ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.798     1.725    d_1_i/ddr4_0/inst/c0_ddr4_ui_clk
    SLICE_X94Y50         FDRE                                         r  d_1_i/ddr4_0/inst/div_clk_rst_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y50         FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     1.766 r  d_1_i/ddr4_0/inst/div_clk_rst_r1_reg/Q
                         net (fo=1, routed)           0.093     1.859    d_1_i/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X93Y50         FDRE                                         r  d_1_i/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.903     1.466    d_1_i/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X93Y50         FDRE                                         r  d_1_i/rst_ddr4/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.171ns  (logic 0.039ns (22.758%)  route 0.132ns (77.242%))
  Logic Levels:           0  
  Clock Path Skew:        -0.254ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.553ns
    Source Clock Delay      (SCD):    1.807ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.880ns (routing 0.230ns, distribution 0.650ns)
  Clock Net Delay (Destination): 0.990ns (routing 0.255ns, distribution 0.735ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.880     1.807    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.846 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.132     1.978    d_1_i/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X77Y17         FDCE                                         f  d_1_i/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.990     1.553    d_1_i/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X77Y17         FDCE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.171ns  (logic 0.039ns (22.758%)  route 0.132ns (77.242%))
  Logic Levels:           0  
  Clock Path Skew:        -0.254ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.553ns
    Source Clock Delay      (SCD):    1.807ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.880ns (routing 0.230ns, distribution 0.650ns)
  Clock Net Delay (Destination): 0.990ns (routing 0.255ns, distribution 0.735ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.880     1.807    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.846 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.132     1.978    d_1_i/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X77Y17         FDCE                                         f  d_1_i/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.990     1.553    d_1_i/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X77Y17         FDCE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.171ns  (logic 0.039ns (22.758%)  route 0.132ns (77.242%))
  Logic Levels:           0  
  Clock Path Skew:        -0.254ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.553ns
    Source Clock Delay      (SCD):    1.807ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.880ns (routing 0.230ns, distribution 0.650ns)
  Clock Net Delay (Destination): 0.990ns (routing 0.255ns, distribution 0.735ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.880     1.807    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.846 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.132     1.978    d_1_i/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X77Y17         FDCE                                         f  d_1_i/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.990     1.553    d_1_i/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X77Y17         FDCE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.208ns  (logic 0.039ns (18.711%)  route 0.169ns (81.289%))
  Logic Levels:           0  
  Clock Path Skew:        -0.253ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.554ns
    Source Clock Delay      (SCD):    1.807ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.880ns (routing 0.230ns, distribution 0.650ns)
  Clock Net Delay (Destination): 0.991ns (routing 0.255ns, distribution 0.736ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.880     1.807    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.846 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.169     2.015    d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X79Y23         FDCE                                         f  d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.991     1.554    d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X79Y23         FDCE                                         r  d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.208ns  (logic 0.039ns (18.711%)  route 0.169ns (81.289%))
  Logic Levels:           0  
  Clock Path Skew:        -0.253ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.554ns
    Source Clock Delay      (SCD):    1.807ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.880ns (routing 0.230ns, distribution 0.650ns)
  Clock Net Delay (Destination): 0.991ns (routing 0.255ns, distribution 0.736ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.880     1.807    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.846 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.169     2.015    d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X79Y23         FDCE                                         f  d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.991     1.554    d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X79Y23         FDCE                                         r  d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.208ns  (logic 0.039ns (18.711%)  route 0.169ns (81.289%))
  Logic Levels:           0  
  Clock Path Skew:        -0.253ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.554ns
    Source Clock Delay      (SCD):    1.807ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.880ns (routing 0.230ns, distribution 0.650ns)
  Clock Net Delay (Destination): 0.991ns (routing 0.255ns, distribution 0.736ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.880     1.807    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.846 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.169     2.015    d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X79Y23         FDCE                                         f  d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.991     1.554    d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X79Y23         FDCE                                         r  d_1_i/axi_smc_1/inst/s00_nodes/s00_r_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.329ns  (logic 0.039ns (11.839%)  route 0.290ns (88.161%))
  Logic Levels:           0  
  Clock Path Skew:        -0.256ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.551ns
    Source Clock Delay      (SCD):    1.807ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.880ns (routing 0.230ns, distribution 0.650ns)
  Clock Net Delay (Destination): 0.988ns (routing 0.255ns, distribution 0.733ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.880     1.807    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.846 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.290     2.136    d_1_i/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X79Y43         FDCE                                         f  d_1_i/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.988     1.551    d_1_i/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X79Y43         FDCE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.329ns  (logic 0.039ns (11.839%)  route 0.290ns (88.161%))
  Logic Levels:           0  
  Clock Path Skew:        -0.256ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.551ns
    Source Clock Delay      (SCD):    1.807ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.880ns (routing 0.230ns, distribution 0.650ns)
  Clock Net Delay (Destination): 0.988ns (routing 0.255ns, distribution 0.733ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.880     1.807    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.846 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.290     2.136    d_1_i/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X79Y43         FDCE                                         f  d_1_i/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.988     1.551    d_1_i/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X79Y43         FDCE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR
                            (removal check against rising-edge clock mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Removal (Min at Fast Process Corner)
  Data Path Delay:        0.329ns  (logic 0.039ns (11.839%)  route 0.290ns (88.161%))
  Logic Levels:           0  
  Clock Path Skew:        -0.256ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.551ns
    Source Clock Delay      (SCD):    1.807ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.062ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.880ns (routing 0.230ns, distribution 0.650ns)
  Clock Net Delay (Destination): 0.988ns (routing 0.255ns, distribution 0.733ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.880     1.807    d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/aclk
    SLICE_X79Y17         FDRE                                         r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/C
  -------------------------------------------------------------------    -------------------
    SLICE_X79Y17         FDRE (Prop_DFF_SLICEM_C_Q)
                                                      0.039     1.846 r  d_1_i/axi_smc_1/inst/clk_map/psr_aclk/U0/ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N/Q
                         net (fo=66, routed)          0.290     2.136    d_1_i/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/src_arst
    SLICE_X79Y43         FDCE                                         f  d_1_i/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/CLR  (IS_INVERTED)
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.988     1.551    d_1_i/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/dest_clk
    SLICE_X79Y43         FDCE                                         r  d_1_i/axi_smc_1/inst/s01_nodes/s01_b_node/inst/s_sc_xpm_cdc_async_rst_inst/arststages_ff_reg[2]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout5
  To Clock:  mmcm_clkout0

Max Delay             0 Endpoints
Min Delay            28 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.039ns (39.000%)  route 0.061ns (61.000%))
  Logic Levels:           0  
  Clock Path Skew:        -0.148ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.449ns
    Source Clock Delay      (SCD):    1.597ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.679ns (routing 0.096ns, distribution 0.583ns)
  Clock Net Delay (Destination): 0.886ns (routing 0.255ns, distribution 0.631ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.679     1.597    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y64         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y64         FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.636 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[2]/Q
                         net (fo=1, routed)           0.061     1.697    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[2]
    SLICE_X95Y64         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.886     1.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[1]_0
    SLICE_X95Y64         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[2].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.040ns (33.333%)  route 0.080ns (66.667%))
  Logic Levels:           0  
  Clock Path Skew:        -0.138ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.449ns
    Source Clock Delay      (SCD):    1.587ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.669ns (routing 0.096ns, distribution 0.573ns)
  Clock Net Delay (Destination): 0.886ns (routing 0.255ns, distribution 0.631ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.669     1.587    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X91Y72         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y72         FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[7]/Q
                         net (fo=1, routed)           0.080     1.707    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[7]
    SLICE_X91Y72         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.886     1.449    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[1]_0
    SLICE_X91Y72         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[7].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_cptd_sclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.040ns (33.333%)  route 0.080ns (66.667%))
  Logic Levels:           0  
  Clock Path Skew:        -0.153ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.435ns
    Source Clock Delay      (SCD):    1.587ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.669ns (routing 0.096ns, distribution 0.573ns)
  Clock Net Delay (Destination): 0.872ns (routing 0.255ns, distribution 0.617ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.669     1.587    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X95Y80         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_cptd_sclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y80         FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_cptd_sclk_reg/Q
                         net (fo=1, routed)           0.080     1.707    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]_1[0]
    SLICE_X95Y80         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.872     1.435    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]_0
    SLICE_X95Y80         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_cptd_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.119ns  (logic 0.039ns (32.773%)  route 0.080ns (67.227%))
  Logic Levels:           0  
  Clock Path Skew:        -0.146ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.443ns
    Source Clock Delay      (SCD):    1.588ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.670ns (routing 0.096ns, distribution 0.574ns)
  Clock Net Delay (Destination): 0.880ns (routing 0.255ns, distribution 0.625ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.670     1.588    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X92Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y67         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[4]/Q
                         net (fo=1, routed)           0.080     1.707    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[4]
    SLICE_X92Y65         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.880     1.443    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[1]_0
    SLICE_X92Y65         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[4].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.039ns (32.231%)  route 0.082ns (67.769%))
  Logic Levels:           0  
  Clock Path Skew:        -0.145ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.444ns
    Source Clock Delay      (SCD):    1.588ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.670ns (routing 0.096ns, distribution 0.574ns)
  Clock Net Delay (Destination): 0.881ns (routing 0.255ns, distribution 0.626ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.670     1.588    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X92Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y67         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.627 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[0]/Q
                         net (fo=1, routed)           0.082     1.709    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[0]
    SLICE_X92Y64         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.881     1.444    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[1]_0
    SLICE_X92Y64         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.120ns  (logic 0.040ns (33.333%)  route 0.080ns (66.667%))
  Logic Levels:           0  
  Clock Path Skew:        -0.140ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.450ns
    Source Clock Delay      (SCD):    1.590ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.672ns (routing 0.096ns, distribution 0.576ns)
  Clock Net Delay (Destination): 0.887ns (routing 0.255ns, distribution 0.632ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.672     1.590    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X92Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y69         FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.630 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[1]/Q
                         net (fo=1, routed)           0.080     1.710    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[1]
    SLICE_X91Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.887     1.450    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[1]_0
    SLICE_X91Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.132ns  (logic 0.039ns (29.545%)  route 0.093ns (70.454%))
  Logic Levels:           0  
  Clock Path Skew:        -0.135ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.454ns
    Source Clock Delay      (SCD):    1.589ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.671ns (routing 0.096ns, distribution 0.575ns)
  Clock Net Delay (Destination): 0.892ns (routing 0.255ns, distribution 0.637ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.671     1.589    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X96Y75         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y75         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.628 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[15]/Q
                         net (fo=1, routed)           0.093     1.721    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[15]
    SLICE_X94Y76         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.892     1.454    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[1]_0
    SLICE_X94Y76         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[15].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[10].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.132ns  (logic 0.039ns (29.545%)  route 0.093ns (70.455%))
  Logic Levels:           0  
  Clock Path Skew:        -0.146ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.444ns
    Source Clock Delay      (SCD):    1.590ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.672ns (routing 0.096ns, distribution 0.576ns)
  Clock Net Delay (Destination): 0.881ns (routing 0.255ns, distribution 0.626ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.672     1.590    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X91Y75         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y75         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.629 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[10]/Q
                         net (fo=1, routed)           0.093     1.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[10]
    SLICE_X91Y75         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[10].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.881     1.444    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[1]_0
    SLICE_X91Y75         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[10].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.137ns  (logic 0.037ns (27.007%)  route 0.100ns (72.993%))
  Logic Levels:           0  
  Clock Path Skew:        -0.148ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.444ns
    Source Clock Delay      (SCD):    1.591ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.673ns (routing 0.096ns, distribution 0.577ns)
  Clock Net Delay (Destination): 0.881ns (routing 0.255ns, distribution 0.626ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.673     1.591    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X93Y66         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y66         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     1.628 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_di_r_reg[8]/Q
                         net (fo=1, routed)           0.100     1.728    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/out[8]
    SLICE_X93Y66         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.881     1.444    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[1]_0
    SLICE_X93Y66         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_di_sync/SYNC[8].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[11].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.143ns  (logic 0.040ns (27.972%)  route 0.103ns (72.028%))
  Logic Levels:           0  
  Clock Path Skew:        -0.145ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.445ns
    Source Clock Delay      (SCD):    1.590ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.672ns (routing 0.096ns, distribution 0.576ns)
  Clock Net Delay (Destination): 0.882ns (routing 0.255ns, distribution 0.627ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.138     0.901    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.918 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.672     1.590    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/CLK
    SLICE_X91Y75         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y75         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.040     1.630 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_addr_r_reg[11]/Q
                         net (fo=1, routed)           0.103     1.733    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/out[11]
    SLICE_X92Y75         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[11].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.882     1.445    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[14].sync_reg_reg[1]_0
    SLICE_X92Y75         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_addr_sync/SYNC[11].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout0

Max Delay             0 Endpoints
Min Delay           115 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[26]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[26].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.094ns  (logic 0.039ns (41.489%)  route 0.055ns (58.511%))
  Logic Levels:           0  
  Clock Path Skew:        -0.264ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.451ns
    Source Clock Delay      (SCD):    1.714ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.778ns (routing 0.230ns, distribution 0.548ns)
  Clock Net Delay (Destination): 0.888ns (routing 0.255ns, distribution 0.633ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.778     1.714    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X92Y32         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[26]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y32         FDRE (Prop_AFF_SLICEL_C_Q)
                                                      0.039     1.753 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[26]/Q
                         net (fo=1, routed)           0.055     1.808    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[31].sync_reg_reg[0]_0[26]
    SLICE_X92Y32         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[26].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.888     1.451    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[30].sync_reg_reg[1]_0
    SLICE_X92Y32         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[26].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[10].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.037ns (38.144%)  route 0.060ns (61.856%))
  Logic Levels:           0  
  Clock Path Skew:        -0.263ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.454ns
    Source Clock Delay      (SCD):    1.716ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.780ns (routing 0.230ns, distribution 0.550ns)
  Clock Net Delay (Destination): 0.891ns (routing 0.255ns, distribution 0.636ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.780     1.716    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X93Y31         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y31         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     1.753 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[10]/Q
                         net (fo=1, routed)           0.060     1.813    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[10]
    SLICE_X92Y31         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[10].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.891     1.454    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X92Y31         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[10].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[19]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.103ns  (logic 0.039ns (37.864%)  route 0.064ns (62.136%))
  Logic Levels:           0  
  Clock Path Skew:        -0.259ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.456ns
    Source Clock Delay      (SCD):    1.714ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.778ns (routing 0.230ns, distribution 0.548ns)
  Clock Net Delay (Destination): 0.893ns (routing 0.255ns, distribution 0.638ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.778     1.714    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X92Y32         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[19]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y32         FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.039     1.753 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[19]/Q
                         net (fo=1, routed)           0.064     1.817    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[19]
    SLICE_X93Y32         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.893     1.456    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X93Y32         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[23].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.038ns (38.775%)  route 0.060ns (61.224%))
  Logic Levels:           0  
  Clock Path Skew:        -0.268ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.454ns
    Source Clock Delay      (SCD):    1.721ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.785ns (routing 0.230ns, distribution 0.555ns)
  Clock Net Delay (Destination): 0.891ns (routing 0.255ns, distribution 0.636ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.785     1.721    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X93Y37         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X93Y37         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.759 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[23]/Q
                         net (fo=1, routed)           0.060     1.819    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[31].sync_reg_reg[0]_0[23]
    SLICE_X93Y37         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[23].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.891     1.454    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[30].sync_reg_reg[1]_0
    SLICE_X93Y37         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[23].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[18]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[18].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.110ns  (logic 0.038ns (34.545%)  route 0.072ns (65.455%))
  Logic Levels:           0  
  Clock Path Skew:        -0.263ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.458ns
    Source Clock Delay      (SCD):    1.720ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.784ns (routing 0.230ns, distribution 0.554ns)
  Clock Net Delay (Destination): 0.895ns (routing 0.255ns, distribution 0.640ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.784     1.720    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X94Y35         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[18]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y35         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.758 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[18]/Q
                         net (fo=1, routed)           0.072     1.830    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[18]
    SLICE_X93Y35         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[18].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.895     1.458    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X93Y35         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[18].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_low_riuclk_int_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.101ns  (logic 0.039ns (38.445%)  route 0.062ns (61.555%))
  Logic Levels:           0  
  Clock Path Skew:        -0.266ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.464ns
    Source Clock Delay      (SCD):    1.729ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.793ns (routing 0.230ns, distribution 0.563ns)
  Clock Net Delay (Destination): 0.901ns (routing 0.255ns, distribution 0.646ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.793     1.729    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X81Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_low_riuclk_int_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X81Y69         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.768 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/phy2clb_fixdly_rdy_low_riuclk_int_reg[5]/Q
                         net (fo=2, routed)           0.062     1.831    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/phy2clb_fixdly_rdy_low_riuclk[5]
    SLICE_X81Y68         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.901     1.464    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[19].sync_reg_reg[1]_0
    SLICE_X81Y68         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_phy2clb_fixdly_rdy_low/SYNC[5].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[20]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[20].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.038ns (38.775%)  route 0.060ns (61.224%))
  Logic Levels:           0  
  Clock Path Skew:        -0.268ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.465ns
    Source Clock Delay      (SCD):    1.733ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.797ns (routing 0.230ns, distribution 0.567ns)
  Clock Net Delay (Destination): 0.902ns (routing 0.255ns, distribution 0.647ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.797     1.733    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X89Y20         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[20]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y20         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.771 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[20]/Q
                         net (fo=1, routed)           0.060     1.831    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[31].sync_reg_reg[0]_0[20]
    SLICE_X88Y20         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[20].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.902     1.465    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[30].sync_reg_reg[1]_0
    SLICE_X88Y20         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[20].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[25].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.102ns  (logic 0.037ns (36.388%)  route 0.065ns (63.612%))
  Logic Levels:           0  
  Clock Path Skew:        -0.255ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.475ns
    Source Clock Delay      (SCD):    1.730ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.794ns (routing 0.230ns, distribution 0.564ns)
  Clock Net Delay (Destination): 0.912ns (routing 0.255ns, distribution 0.657ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.794     1.730    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X89Y16         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y16         FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     1.767 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_address_riuclk_reg[25]/Q
                         net (fo=4, routed)           0.065     1.832    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[0]_0[25]
    SLICE_X88Y16         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[25].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.912     1.475    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[31].sync_reg_reg[1]_0
    SLICE_X88Y16         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_addr_sync/SYNC[25].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[27].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.038ns (31.405%)  route 0.083ns (68.595%))
  Logic Levels:           0  
  Clock Path Skew:        -0.268ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.453ns
    Source Clock Delay      (SCD):    1.720ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.784ns (routing 0.230ns, distribution 0.554ns)
  Clock Net Delay (Destination): 0.890ns (routing 0.255ns, distribution 0.635ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.784     1.720    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X89Y30         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y30         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.758 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/io_write_data_riuclk_reg[27]/Q
                         net (fo=1, routed)           0.083     1.841    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[31].sync_reg_reg[0]_0[27]
    SLICE_X89Y30         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[27].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.890     1.453    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[30].sync_reg_reg[1]_0
    SLICE_X89Y30         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_write_data_sync/SYNC[27].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[16]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[16].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.128ns  (logic 0.040ns (31.250%)  route 0.088ns (68.750%))
  Logic Levels:           0  
  Clock Path Skew:        -0.264ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.451ns
    Source Clock Delay      (SCD):    1.714ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.778ns (routing 0.230ns, distribution 0.548ns)
  Clock Net Delay (Destination): 0.888ns (routing 0.255ns, distribution 0.633ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.778     1.714    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/CLK
    SLICE_X92Y32         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[16]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y32         FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     1.754 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/riu2clb_valid_r1_riuclk_reg[16]/Q
                         net (fo=1, routed)           0.088     1.842    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[0]_0[16]
    SLICE_X92Y32         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[16].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     0.544    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.563 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.888     1.451    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[19].sync_reg_reg[1]_0
    SLICE_X92Y32         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_riu2clb_valid_sync/SYNC[16].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
  To Clock:  mmcm_clkout5

Max Delay            78 Endpoints
Min Delay            86 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAME_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.085ns  (logic 0.302ns (27.834%)  route 0.783ns (72.166%))
  Logic Levels:           0  
  Clock Path Skew:        -4.988ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.722ns
    Source Clock Delay      (SCD):    7.710ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.960ns (routing 1.068ns, distribution 0.892ns)
  Clock Net Delay (Destination): 1.050ns (routing 0.155ns, distribution 0.895ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.960     7.710    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X99Y63         RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAME_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y63         RAMD32 (Prop_E6LUT_SLICEM_CLK_O)
                                                      0.302     8.012 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAME_D1/O
                         net (fo=1, routed)           0.783     8.795    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[9]
    SLICE_X95Y69         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206     1.647    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.671 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.050     2.722    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X95Y69         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[9]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_en_1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.979ns  (logic 0.079ns (8.067%)  route 0.900ns (91.933%))
  Logic Levels:           0  
  Clock Path Skew:        -4.900ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.798ns
    Source Clock Delay      (SCD):    7.698ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.948ns (routing 1.068ns, distribution 0.880ns)
  Clock Net Delay (Destination): 1.127ns (routing 0.155ns, distribution 0.972ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.948     7.698    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X106Y71        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y71        FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     7.777 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/icn_cmd_en_temp_reg/Q
                         net (fo=29, routed)          0.900     8.678    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/icn_cmd_en_temp
    SLICE_X107Y68        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_en_1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206     1.647    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.671 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.127     2.798    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X107Y68        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_en_1_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.946ns  (logic 0.079ns (8.351%)  route 0.867ns (91.649%))
  Logic Levels:           0  
  Clock Path Skew:        -4.896ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.789ns
    Source Clock Delay      (SCD):    7.685ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.935ns (routing 1.068ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.118ns (routing 0.155ns, distribution 0.963ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.935     7.685    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y68        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y68        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.079     7.764 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[8]/Q
                         net (fo=2, routed)           0.867     8.631    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[8]
    SLICE_X105Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206     1.647    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.671 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.118     2.789    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X105Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[8]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.931ns  (logic 0.079ns (8.485%)  route 0.852ns (91.515%))
  Logic Levels:           0  
  Clock Path Skew:        -4.917ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.781ns
    Source Clock Delay      (SCD):    7.698ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.948ns (routing 1.068ns, distribution 0.880ns)
  Clock Net Delay (Destination): 1.110ns (routing 0.155ns, distribution 0.955ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.948     7.698    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y67        FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.079     7.777 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[23]/Q
                         net (fo=2, routed)           0.852     8.629    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[23]
    SLICE_X104Y68        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206     1.647    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.671 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.110     2.781    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X104Y68        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[23]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/DP/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[14]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.886ns  (logic 0.295ns (33.296%)  route 0.591ns (66.704%))
  Logic Levels:           0  
  Clock Path Skew:        -4.958ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.767ns
    Source Clock Delay      (SCD):    7.725ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.975ns (routing 1.068ns, distribution 0.907ns)
  Clock Net Delay (Destination): 1.096ns (routing 0.155ns, distribution 0.941ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.975     7.725    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/WCLK
    SLICE_X103Y63        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/DP/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y63        RAMD32 (Prop_G6LUT_SLICEM_CLK_O)
                                                      0.295     8.020 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15/DP/O
                         net (fo=1, routed)           0.591     8.611    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[14]
    SLICE_X102Y66        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[14]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206     1.647    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.671 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.096     2.767    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X102Y66        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[14]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.921ns  (logic 0.079ns (8.577%)  route 0.842ns (91.423%))
  Logic Levels:           0  
  Clock Path Skew:        -4.888ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.797ns
    Source Clock Delay      (SCD):    7.685ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.935ns (routing 1.068ns, distribution 0.867ns)
  Clock Net Delay (Destination): 1.126ns (routing 0.155ns, distribution 0.971ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.935     7.685    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y68        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y68        FDRE (Prop_BFF_SLICEL_C_Q)
                                                      0.079     7.764 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[7]/Q
                         net (fo=2, routed)           0.842     8.606    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[7]
    SLICE_X107Y68        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206     1.647    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.671 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.126     2.797    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X107Y68        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[7]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.726ns  (logic 0.292ns (40.220%)  route 0.434ns (59.780%))
  Logic Levels:           0  
  Clock Path Skew:        -4.993ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.717ns
    Source Clock Delay      (SCD):    7.710ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.960ns (routing 1.068ns, distribution 0.892ns)
  Clock Net Delay (Destination): 1.046ns (routing 0.155ns, distribution 0.891ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.960     7.710    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X99Y63         RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y63         RAMD32 (Prop_B5LUT_SLICEM_CLK_O)
                                                      0.292     8.002 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMB/O
                         net (fo=1, routed)           0.434     8.436    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[2]
    SLICE_X96Y63         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206     1.647    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.671 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.046     2.717    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X96Y63         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[2]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[15]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.710ns  (logic 0.281ns (39.577%)  route 0.429ns (60.423%))
  Logic Levels:           0  
  Clock Path Skew:        -4.958ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.767ns
    Source Clock Delay      (SCD):    7.725ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.975ns (routing 1.068ns, distribution 0.907ns)
  Clock Net Delay (Destination): 1.096ns (routing 0.155ns, distribution 0.941ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.975     7.725    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/WCLK
    SLICE_X103Y63        RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y63        RAMD32 (Prop_G5LUT_SLICEM_CLK_O)
                                                      0.281     8.006 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_14_15__0/DP/O
                         net (fo=1, routed)           0.429     8.435    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[15]
    SLICE_X102Y66        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[15]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206     1.647    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.671 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.096     2.767    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X102Y66        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[15]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
                            (rising edge-triggered cell RAMD32 clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.702ns  (logic 0.287ns (40.883%)  route 0.415ns (59.117%))
  Logic Levels:           0  
  Clock Path Skew:        -4.993ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.717ns
    Source Clock Delay      (SCD):    7.710ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.960ns (routing 1.068ns, distribution 0.892ns)
  Clock Net Delay (Destination): 1.046ns (routing 0.155ns, distribution 0.891ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.960     7.710    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/WCLK
    SLICE_X99Y63         RAMD32                                       r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X99Y63         RAMD32 (Prop_D5LUT_SLICEM_CLK_O)
                                                      0.287     7.997 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/RAM_reg_0_15_0_13/RAMD/O
                         net (fo=1, routed)           0.415     8.412    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/dout_i0[6]
    SLICE_X96Y63         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206     1.647    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.671 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.046     2.717    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/rd_clk
    SLICE_X96Y63         FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gdm.dm_gen.dm/gpr1.dout_i_reg[6]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_5_temp_reg/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.709ns  (logic 0.081ns (11.419%)  route 0.628ns (88.581%))
  Logic Levels:           0  
  Clock Path Skew:        -4.904ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.793ns
    Source Clock Delay      (SCD):    7.697ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.947ns (routing 1.068ns, distribution 0.879ns)
  Clock Net Delay (Destination): 1.122ns (routing 0.155ns, distribution 0.967ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           1.422     5.722    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     5.750 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.947     7.697    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/m_bscan_tck[0]
    SLICE_X106Y72        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y72        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     7.778 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_reg[5]/Q
                         net (fo=6, routed)           0.628     8.407    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/p_1_in1_in
    SLICE_X106Y61        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_5_temp_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.206     1.647    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.671 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         1.122     2.793    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/clk
    SLICE_X106Y61        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/icn_cmd_en_5_temp_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.097ns  (logic 0.039ns (40.206%)  route 0.058ns (59.794%))
  Logic Levels:           0  
  Clock Path Skew:        -0.937ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.364ns
    Source Clock Delay      (SCD):    2.301ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.064ns (routing 0.587ns, distribution 0.477ns)
  Clock Net Delay (Destination): 0.809ns (routing 0.108ns, distribution 0.701ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.064     2.301    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X102Y60        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y60        FDCE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     2.340 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[0]/Q
                         net (fo=1, routed)           0.058     2.398    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[0]
    SLICE_X102Y59        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.809     1.364    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X102Y59        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.041ns (41.837%)  route 0.057ns (58.163%))
  Logic Levels:           0  
  Clock Path Skew:        -0.933ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.368ns
    Source Clock Delay      (SCD):    2.301ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.064ns (routing 0.587ns, distribution 0.477ns)
  Clock Net Delay (Destination): 0.813ns (routing 0.108ns, distribution 0.705ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.064     2.301    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X102Y60        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y60        FDCE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     2.342 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[1]/Q
                         net (fo=1, routed)           0.057     2.399    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[1]
    SLICE_X102Y59        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.813     1.368    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X102Y59        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.108ns  (logic 0.040ns (37.146%)  route 0.068ns (62.854%))
  Logic Levels:           0  
  Clock Path Skew:        -0.918ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.384ns
    Source Clock Delay      (SCD):    2.303ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.066ns (routing 0.587ns, distribution 0.479ns)
  Clock Net Delay (Destination): 0.830ns (routing 0.108ns, distribution 0.722ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.066     2.303    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y68        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y68        FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[11]/Q
                         net (fo=2, routed)           0.068     2.410    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[11]
    SLICE_X105Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.830     1.384    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X105Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[11]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.040ns (38.579%)  route 0.064ns (61.421%))
  Logic Levels:           0  
  Clock Path Skew:        -0.931ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.377ns
    Source Clock Delay      (SCD):    2.308ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.071ns (routing 0.587ns, distribution 0.484ns)
  Clock Net Delay (Destination): 0.822ns (routing 0.108ns, distribution 0.714ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.071     2.308    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/m_bscan_tck[0]
    SLICE_X106Y72        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y72        FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     2.348 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[1]/Q
                         net (fo=2, routed)           0.064     2.411    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in[1]
    SLICE_X106Y74        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.822     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/clk
    SLICE_X106Y74        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[1]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/icn_cmd_en_temp_reg/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_ld_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.109ns  (logic 0.041ns (37.598%)  route 0.068ns (62.402%))
  Logic Levels:           0  
  Clock Path Skew:        -0.931ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.374ns
    Source Clock Delay      (SCD):    2.305ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.068ns (routing 0.587ns, distribution 0.481ns)
  Clock Net Delay (Destination): 0.819ns (routing 0.108ns, distribution 0.711ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.068     2.305    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/m_bscan_tck[0]
    SLICE_X105Y72        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/icn_cmd_en_temp_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y72        FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     2.346 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/icn_cmd_en_temp_reg/Q
                         net (fo=6, routed)           0.068     2.414    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/icn_cmd_en_temp
    SLICE_X105Y73        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_ld_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.819     1.374    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/clk
    SLICE_X105Y73        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD2/stat_reg_ld_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.112ns  (logic 0.038ns (34.025%)  route 0.074ns (65.975%))
  Logic Levels:           0  
  Clock Path Skew:        -0.939ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.367ns
    Source Clock Delay      (SCD):    2.306ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.069ns (routing 0.587ns, distribution 0.482ns)
  Clock Net Delay (Destination): 0.812ns (routing 0.108ns, distribution 0.704ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.069     2.306    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X103Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y69        FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     2.344 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[6]/Q
                         net (fo=2, routed)           0.074     2.417    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[6]
    SLICE_X103Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.812     1.367    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X103Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[6]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.113ns  (logic 0.040ns (35.498%)  route 0.073ns (64.502%))
  Logic Levels:           0  
  Clock Path Skew:        -0.931ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.377ns
    Source Clock Delay      (SCD):    2.308ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.071ns (routing 0.587ns, distribution 0.484ns)
  Clock Net Delay (Destination): 0.822ns (routing 0.108ns, distribution 0.714ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.071     2.308    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/m_bscan_tck[0]
    SLICE_X106Y72        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X106Y72        FDRE (Prop_AFF2_SLICEL_C_Q)
                                                      0.040     2.348 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in_reg[0]/Q
                         net (fo=2, routed)           0.073     2.420    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/shift_reg_in[0]
    SLICE_X106Y74        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.822     1.377    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/clk
    SLICE_X106Y74        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD7_CTL/ctl_reg_reg[0]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.114ns  (logic 0.039ns (34.306%)  route 0.075ns (65.694%))
  Logic Levels:           0  
  Clock Path Skew:        -0.934ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.373ns
    Source Clock Delay      (SCD):    2.307ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.070ns (routing 0.587ns, distribution 0.483ns)
  Clock Net Delay (Destination): 0.818ns (routing 0.108ns, distribution 0.710ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.070     2.307    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/m_bscan_tck[0]
    SLICE_X105Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X105Y67        FDRE (Prop_CFF_SLICEL_C_Q)
                                                      0.039     2.346 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in_reg[22]/Q
                         net (fo=2, routed)           0.075     2.421    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/shift_reg_in[22]
    SLICE_X104Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.818     1.373    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/clk
    SLICE_X104Y67        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD4/ctl_reg_reg[22]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.116ns  (logic 0.037ns (31.984%)  route 0.079ns (68.016%))
  Logic Levels:           0  
  Clock Path Skew:        -0.939ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.367ns
    Source Clock Delay      (SCD):    2.306ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.069ns (routing 0.587ns, distribution 0.482ns)
  Clock Net Delay (Destination): 0.812ns (routing 0.108ns, distribution 0.704ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.069     2.306    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/m_bscan_tck[0]
    SLICE_X103Y69        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X103Y69        FDRE (Prop_FFF_SLICEM_C_Q)
                                                      0.037     2.343 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in_reg[7]/Q
                         net (fo=2, routed)           0.079     2.421    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/shift_reg_in[7]
    SLICE_X103Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.812     1.367    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/clk
    SLICE_X103Y70        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD5/ctl_reg_reg[7]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
                            (rising edge-triggered cell FDCE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
                            (rising edge-triggered cell FDCE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.122ns  (logic 0.039ns (31.967%)  route 0.083ns (68.033%))
  Logic Levels:           0  
  Clock Path Skew:        -0.937ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.363ns
    Source Clock Delay      (SCD):    2.300ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.174ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.063ns (routing 0.587ns, distribution 0.476ns)
  Clock Net Delay (Destination): 0.808ns (routing 0.108ns, distribution 0.700ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.755     1.220    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     1.237 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.063     2.300    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_clk
    SLICE_X102Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X102Y62        FDCE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     2.339 r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.wr_pntr_gc_reg[3]/Q
                         net (fo=1, routed)           0.083     2.422    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q[3]
    SLICE_X102Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.808     1.363    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/rd_clk
    SLICE_X102Y62        FDCE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.UUT_MASTER/U_ICON_INTERFACE/U_CMD6_WR/U_WR_FIFO/SUBCORE_FIFO.xsdbm_v3_0_0_wrfifo_inst/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/gnxpm_cdc.gsync_stage[1].rd_stg_inst/Q_reg_reg[3]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout5

Max Delay             0 Endpoints
Min Delay            10 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.168ns  (logic 0.041ns (24.405%)  route 0.127ns (75.595%))
  Logic Levels:           0  
  Clock Path Skew:        -0.378ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.322ns
    Source Clock Delay      (SCD):    1.699ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.773ns (routing 0.230ns, distribution 0.543ns)
  Clock Net Delay (Destination): 0.767ns (routing 0.108ns, distribution 0.659ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.773     1.699    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X92Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y69         FDRE (Prop_DFF2_SLICEL_C_Q)
                                                      0.041     1.740 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[4]/Q
                         net (fo=1, routed)           0.127     1.867    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[4]
    SLICE_X92Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.767     1.322    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X92Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[4].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.167ns  (logic 0.040ns (23.952%)  route 0.127ns (76.048%))
  Logic Levels:           0  
  Clock Path Skew:        -0.381ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.323ns
    Source Clock Delay      (SCD):    1.703ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.777ns (routing 0.230ns, distribution 0.547ns)
  Clock Net Delay (Destination): 0.768ns (routing 0.108ns, distribution 0.660ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.777     1.703    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X92Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y67         FDRE (Prop_GFF2_SLICEL_C_Q)
                                                      0.040     1.743 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[8]/Q
                         net (fo=1, routed)           0.127     1.870    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[8]
    SLICE_X95Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.768     1.323    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X95Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[8].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.173ns  (logic 0.040ns (23.121%)  route 0.133ns (76.879%))
  Logic Levels:           0  
  Clock Path Skew:        -0.381ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.323ns
    Source Clock Delay      (SCD):    1.703ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.777ns (routing 0.230ns, distribution 0.547ns)
  Clock Net Delay (Destination): 0.768ns (routing 0.108ns, distribution 0.660ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.777     1.703    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X92Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y67         FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.040     1.743 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[1]/Q
                         net (fo=1, routed)           0.133     1.876    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[1]
    SLICE_X95Y68         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.768     1.323    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X95Y68         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.178ns  (logic 0.040ns (22.472%)  route 0.138ns (77.528%))
  Logic Levels:           0  
  Clock Path Skew:        -0.378ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.322ns
    Source Clock Delay      (SCD):    1.699ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.773ns (routing 0.230ns, distribution 0.543ns)
  Clock Net Delay (Destination): 0.767ns (routing 0.108ns, distribution 0.659ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.773     1.699    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X92Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y69         FDRE (Prop_BFF2_SLICEL_C_Q)
                                                      0.040     1.739 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[7]/Q
                         net (fo=1, routed)           0.138     1.877    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[7]
    SLICE_X95Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.767     1.322    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X95Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[7].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.177ns  (logic 0.039ns (22.034%)  route 0.138ns (77.966%))
  Logic Levels:           0  
  Clock Path Skew:        -0.381ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.323ns
    Source Clock Delay      (SCD):    1.703ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.777ns (routing 0.230ns, distribution 0.547ns)
  Clock Net Delay (Destination): 0.768ns (routing 0.108ns, distribution 0.660ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.777     1.703    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X92Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y67         FDRE (Prop_FFF_SLICEL_C_Q)
                                                      0.039     1.742 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[2]/Q
                         net (fo=1, routed)           0.138     1.880    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[2]
    SLICE_X95Y65         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.768     1.323    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X95Y65         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[2].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.194ns  (logic 0.040ns (20.619%)  route 0.154ns (79.381%))
  Logic Levels:           0  
  Clock Path Skew:        -0.360ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.339ns
    Source Clock Delay      (SCD):    1.699ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.773ns (routing 0.230ns, distribution 0.543ns)
  Clock Net Delay (Destination): 0.785ns (routing 0.108ns, distribution 0.677ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.773     1.699    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X92Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y69         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.739 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[5]/Q
                         net (fo=1, routed)           0.154     1.893    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[5]
    SLICE_X94Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.785     1.339    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X94Y69         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[5].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.203ns  (logic 0.040ns (19.704%)  route 0.163ns (80.296%))
  Logic Levels:           0  
  Clock Path Skew:        -0.386ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.318ns
    Source Clock Delay      (SCD):    1.703ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.777ns (routing 0.230ns, distribution 0.547ns)
  Clock Net Delay (Destination): 0.763ns (routing 0.108ns, distribution 0.655ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.777     1.703    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X92Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y67         FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.040     1.743 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[3]/Q
                         net (fo=1, routed)           0.163     1.906    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[3]
    SLICE_X92Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.763     1.318    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X92Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[3].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.339ns  (logic 0.039ns (11.504%)  route 0.300ns (88.496%))
  Logic Levels:           0  
  Clock Path Skew:        -0.386ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.318ns
    Source Clock Delay      (SCD):    1.703ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.777ns (routing 0.230ns, distribution 0.547ns)
  Clock Net Delay (Destination): 0.763ns (routing 0.108ns, distribution 0.655ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.777     1.703    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X92Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y67         FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.742 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[0]/Q
                         net (fo=1, routed)           0.300     2.042    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[0]
    SLICE_X92Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.763     1.318    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X92Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.480ns  (logic 0.039ns (8.130%)  route 0.441ns (91.870%))
  Logic Levels:           0  
  Clock Path Skew:        -0.369ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.327ns
    Source Clock Delay      (SCD):    1.696ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.770ns (routing 0.230ns, distribution 0.540ns)
  Clock Net Delay (Destination): 0.772ns (routing 0.108ns, distribution 0.664ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.770     1.696    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X96Y93         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y93         FDRE (Prop_EFF2_SLICEM_C_Q)
                                                      0.039     1.735 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_rdy_lvl_fclk_reg/Q
                         net (fo=2, routed)           0.441     2.176    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/D[0]
    SLICE_X96Y72         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.772     1.327    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/CLK
    SLICE_X96Y72         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_rdy_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout5  {rise@0.000ns fall@6.001ns period=12.002ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.747ns  (logic 0.039ns (5.221%)  route 0.708ns (94.779%))
  Logic Levels:           0  
  Clock Path Skew:        -0.378ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.326ns
    Source Clock Delay      (SCD):    1.703ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.196ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.134ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.777ns (routing 0.230ns, distribution 0.547ns)
  Clock Net Delay (Destination): 0.771ns (routing 0.108ns, distribution 0.663ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.777     1.703    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/SYNC[0].sync_reg_reg[0]
    SLICE_X92Y67         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X92Y67         FDRE (Prop_GFF_SLICEL_C_Q)
                                                      0.039     1.742 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/slave_do_fclk_reg[6]/Q
                         net (fo=1, routed)           0.708     2.450    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/out[6]
    SLICE_X95Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout5 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT5)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT5
                         net (fo=1, routed)           0.158     0.536    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout5
    BUFGCE_X0Y32         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.555 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_dbg_clk/O
    X4Y1 (CLOCK_ROOT)    net (fo=568, routed)         0.771     1.326    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/CLK
    SLICE_X95Y70         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_xsdb_arbiter/u_slave_do_sync/SYNC[6].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  default_sysclk_c0_300mhz_clk_p
  To Clock:  mmcm_clkout6

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.464ns  (logic 0.080ns (17.241%)  route 0.384ns (82.759%))
  Logic Levels:           0  
  Clock Path Skew:        1.229ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.932ns
    Source Clock Delay      (SCD):    1.704ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.771ns (routing 0.001ns, distribution 0.770ns)
  Clock Net Delay (Destination): 1.239ns (routing 0.379ns, distribution 0.860ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     0.905    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     0.933 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.771     1.704    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X89Y77         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y77         FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     1.784 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/Q
                         net (fo=1, routed)           0.384     2.168    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb
    SLICE_X89Y78         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     1.669    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.693 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.239     2.932    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X89Y78         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.403ns  (logic 0.080ns (19.851%)  route 0.323ns (80.149%))
  Logic Levels:           0  
  Clock Path Skew:        1.235ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.936ns
    Source Clock Delay      (SCD):    1.702ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.769ns (routing 0.001ns, distribution 0.768ns)
  Clock Net Delay (Destination): 1.243ns (routing 0.379ns, distribution 0.864ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.336     0.905    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     0.933 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.769     1.702    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X89Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y79         FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     1.782 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.323     2.105    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X86Y80         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     1.669    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.693 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.243     2.936    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X86Y80         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.183ns  (logic 0.039ns (21.286%)  route 0.144ns (78.714%))
  Logic Levels:           0  
  Clock Path Skew:        0.495ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.458ns
    Source Clock Delay      (SCD):    0.962ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.434ns (routing 0.000ns, distribution 0.434ns)
  Clock Net Delay (Destination): 0.884ns (routing 0.255ns, distribution 0.629ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.511    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.528 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.434     0.962    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X89Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y79         FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.001 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/Q
                         net (fo=2, routed)           0.144     1.146    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div
    SLICE_X86Y80         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.884     1.458    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X86Y80         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_riu_sync_r_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.200ns  (logic 0.039ns (19.500%)  route 0.161ns (80.500%))
  Logic Levels:           0  
  Clock Path Skew:        0.492ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.456ns
    Source Clock Delay      (SCD):    0.963ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.167ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.435ns (routing 0.000ns, distribution 0.435ns)
  Clock Net Delay (Destination): 0.882ns (routing 0.255ns, distribution 0.627ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.194     0.511    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.528 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.435     0.963    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X89Y77         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y77         FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.002 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/Q
                         net (fo=1, routed)           0.161     1.163    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb
    SLICE_X89Y78         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.882     1.456    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X89Y78         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_sync_r_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  mmcm_clkout6

Max Delay             0 Endpoints
Min Delay            35 Endpoints
--------------------------------------------------------------------------------------


Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[27]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[27].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.105ns  (logic 0.040ns (38.095%)  route 0.065ns (61.905%))
  Logic Levels:           0  
  Clock Path Skew:        -0.244ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.470ns
    Source Clock Delay      (SCD):    1.714ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.788ns (routing 0.230ns, distribution 0.558ns)
  Clock Net Delay (Destination): 0.896ns (routing 0.255ns, distribution 0.641ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.788     1.714    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X90Y34         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y34         FDRE (Prop_FFF2_SLICEM_C_Q)
                                                      0.040     1.754 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[27]/Q
                         net (fo=1, routed)           0.065     1.819    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[27]
    SLICE_X90Y35         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[27].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.896     1.470    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X90Y35         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[27].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[8].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.104ns  (logic 0.038ns (36.538%)  route 0.066ns (63.462%))
  Logic Levels:           0  
  Clock Path Skew:        -0.245ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.472ns
    Source Clock Delay      (SCD):    1.717ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.791ns (routing 0.230ns, distribution 0.561ns)
  Clock Net Delay (Destination): 0.898ns (routing 0.255ns, distribution 0.643ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.791     1.717    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X89Y36         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y36         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.755 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[8]/Q
                         net (fo=1, routed)           0.066     1.821    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[8]
    SLICE_X89Y35         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[8].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.898     1.472    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X89Y35         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[8].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[15].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.108ns  (logic 0.039ns (36.111%)  route 0.069ns (63.889%))
  Logic Levels:           0  
  Clock Path Skew:        -0.245ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.469ns
    Source Clock Delay      (SCD):    1.714ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.788ns (routing 0.230ns, distribution 0.558ns)
  Clock Net Delay (Destination): 0.895ns (routing 0.255ns, distribution 0.640ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.788     1.714    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X90Y34         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y34         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.753 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[15]/Q
                         net (fo=1, routed)           0.069     1.822    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[15]
    SLICE_X90Y36         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[15].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.895     1.469    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X90Y36         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[15].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[4].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.100ns  (logic 0.039ns (39.000%)  route 0.061ns (61.000%))
  Logic Levels:           0  
  Clock Path Skew:        -0.250ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.473ns
    Source Clock Delay      (SCD):    1.723ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.796ns (routing 0.230ns, distribution 0.566ns)
  Clock Net Delay (Destination): 0.899ns (routing 0.255ns, distribution 0.644ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.796     1.723    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X90Y42         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y42         FDRE (Prop_HFF_SLICEM_C_Q)
                                                      0.039     1.762 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[4]/Q
                         net (fo=1, routed)           0.061     1.823    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[4]
    SLICE_X90Y42         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[4].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.899     1.473    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X90Y42         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[4].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[22]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[22].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.121ns  (logic 0.040ns (33.058%)  route 0.081ns (66.942%))
  Logic Levels:           0  
  Clock Path Skew:        -0.250ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.469ns
    Source Clock Delay      (SCD):    1.719ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.792ns (routing 0.230ns, distribution 0.562ns)
  Clock Net Delay (Destination): 0.895ns (routing 0.255ns, distribution 0.640ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.792     1.719    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X91Y38         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[22]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X91Y38         FDRE (Prop_CFF2_SLICEL_C_Q)
                                                      0.040     1.759 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[22]/Q
                         net (fo=1, routed)           0.081     1.840    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[22]
    SLICE_X91Y38         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[22].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.895     1.469    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X91Y38         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[22].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[11].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.124ns  (logic 0.038ns (30.645%)  route 0.086ns (69.355%))
  Logic Levels:           0  
  Clock Path Skew:        -0.251ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.466ns
    Source Clock Delay      (SCD):    1.717ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.790ns (routing 0.230ns, distribution 0.560ns)
  Clock Net Delay (Destination): 0.892ns (routing 0.255ns, distribution 0.637ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.790     1.717    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X94Y35         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X94Y35         FDRE (Prop_EFF_SLICEM_C_Q)
                                                      0.038     1.755 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[11]/Q
                         net (fo=1, routed)           0.086     1.841    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[11]
    SLICE_X94Y35         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[11].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.892     1.466    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X94Y35         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[11].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[1].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.131ns  (logic 0.039ns (29.771%)  route 0.092ns (70.229%))
  Logic Levels:           0  
  Clock Path Skew:        -0.244ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.472ns
    Source Clock Delay      (SCD):    1.715ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.789ns (routing 0.230ns, distribution 0.559ns)
  Clock Net Delay (Destination): 0.898ns (routing 0.255ns, distribution 0.643ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.789     1.715    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X89Y38         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y38         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.754 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[1]/Q
                         net (fo=1, routed)           0.092     1.846    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[1]
    SLICE_X89Y38         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[1].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.898     1.472    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X89Y38         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[1].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[23]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[23].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.143ns  (logic 0.039ns (27.273%)  route 0.104ns (72.727%))
  Logic Levels:           0  
  Clock Path Skew:        -0.243ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.471ns
    Source Clock Delay      (SCD):    1.714ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.788ns (routing 0.230ns, distribution 0.558ns)
  Clock Net Delay (Destination): 0.897ns (routing 0.255ns, distribution 0.642ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.788     1.714    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X90Y34         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[23]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y34         FDRE (Prop_GFF2_SLICEM_C_Q)
                                                      0.039     1.753 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[23]/Q
                         net (fo=1, routed)           0.104     1.857    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[23]
    SLICE_X90Y34         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[23].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.897     1.471    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X90Y34         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[23].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.139ns  (logic 0.039ns (28.058%)  route 0.100ns (71.942%))
  Logic Levels:           0  
  Clock Path Skew:        -0.250ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.470ns
    Source Clock Delay      (SCD):    1.720ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.793ns (routing 0.230ns, distribution 0.563ns)
  Clock Net Delay (Destination): 0.896ns (routing 0.255ns, distribution 0.641ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.793     1.720    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X90Y37         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X90Y37         FDRE (Prop_HFF2_SLICEM_C_Q)
                                                      0.039     1.759 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_read_data_reg[0]/Q
                         net (fo=1, routed)           0.100     1.859    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[31].sync_reg_reg[0]_0[0]
    SLICE_X90Y37         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.896     1.470    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/CLK
    SLICE_X90Y37         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_read_data_sync/SYNC[0].sync_reg_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_ready_lvl_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/SYNC[0].sync_reg_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.153ns  (logic 0.041ns (26.879%)  route 0.112ns (73.121%))
  Logic Levels:           0  
  Clock Path Skew:        -0.230ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.492ns
    Source Clock Delay      (SCD):    1.722ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.188ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.120ns
  Clock Net Delay (Source):      0.796ns (routing 0.230ns, distribution 0.566ns)
  Clock Net Delay (Destination): 0.919ns (routing 0.255ns, distribution 0.664ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.796     1.722    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/odt_shift_reg[0][17]
    SLICE_X89Y17         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_ready_lvl_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X89Y17         FDRE (Prop_DFF2_SLICEM_C_Q)
                                                      0.041     1.763 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/u_ddr_cal/u_ddr_cal_addr_decode/io_ready_lvl_reg/Q
                         net (fo=2, routed)           0.112     1.875    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/D[0]
    SLICE_X88Y15         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/SYNC[0].sync_reg_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.919     1.492    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/CLK
    SLICE_X88Y15         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_io_ready_lvl_sync/SYNC[0].sync_reg_reg[0]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout6
  To Clock:  mmcm_clkout6

Max Delay             2 Endpoints
Min Delay           332 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.837ns  (logic 0.077ns (9.194%)  route 0.760ns (90.806%))
  Logic Levels:           0  
  Clock Path Skew:        0.416ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.960ns
    Source Clock Delay      (SCD):    2.545ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.411ns (routing 0.415ns, distribution 0.996ns)
  Clock Net Delay (Destination): 1.267ns (routing 0.379ns, distribution 0.888ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.411     2.545    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X96Y40         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y40         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.077     2.622 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/Q
                         net (fo=5, routed)           0.760     3.382    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X95Y2          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     1.669    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.693 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.267     2.960    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X95Y2          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        0.239ns  (logic 0.079ns (33.054%)  route 0.160ns (66.946%))
  Logic Levels:           0  
  Clock Path Skew:        0.373ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    2.962ns
    Source Clock Delay      (SCD):    2.590ns
    Clock Pessimism Removal (CPR):    0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.456ns (routing 0.415ns, distribution 1.041ns)
  Clock Net Delay (Destination): 1.269ns (routing 0.379ns, distribution 0.890ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.262     1.106    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.134 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.456     2.590    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/slowest_sync_clk
    SLICE_X95Y1          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y1          FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.079     2.669 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/Q
                         net (fo=1, routed)           0.160     2.829    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Reset
    SLICE_X95Y1          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.349     0.811    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.630     1.441 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.228     1.669    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.693 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        1.269     2.962    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Clk
    SLICE_X95Y1          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.098ns  (logic 0.039ns (39.796%)  route 0.059ns (60.204%))
  Logic Levels:           0  
  Clock Path Skew:        -0.252ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.489ns
    Source Clock Delay      (SCD):    1.741ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.805ns (routing 0.230ns, distribution 0.575ns)
  Clock Net Delay (Destination): 0.916ns (routing 0.255ns, distribution 0.661ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.805     1.741    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/slowest_sync_clk
    SLICE_X95Y1          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/C
  -------------------------------------------------------------------    -------------------
    SLICE_X95Y1          FDRE (Prop_EFF_SLICEL_C_Q)
                                                      0.039     1.780 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/FDRE_inst/Q
                         net (fo=1, routed)           0.059     1.839    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Reset
    SLICE_X95Y1          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.916     1.489    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Clk
    SLICE_X95Y1          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/microblaze_I/U0/MicroBlaze_Core_I/Reset_DFF/Synchronize.use_sync_reset.sync_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[10]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.379ns  (logic 0.038ns (10.034%)  route 0.341ns (89.966%))
  Logic Levels:           0  
  Clock Path Skew:        -0.188ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.554ns
    Source Clock Delay      (SCD):    1.741ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.805ns (routing 0.230ns, distribution 0.575ns)
  Clock Net Delay (Destination): 0.980ns (routing 0.255ns, distribution 0.725ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.805     1.741    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y20         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y20         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.779 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[10]/Q
                         net (fo=15, routed)          0.341     2.120    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_2[10]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[10]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.980     1.554    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[10]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.379ns  (logic 0.038ns (10.034%)  route 0.341ns (89.966%))
  Logic Levels:           0  
  Clock Path Skew:        -0.192ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.550ns
    Source Clock Delay      (SCD):    1.741ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.805ns (routing 0.230ns, distribution 0.575ns)
  Clock Net Delay (Destination): 0.976ns (routing 0.255ns, distribution 0.721ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.805     1.741    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y20         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y20         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.779 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[10]/Q
                         net (fo=15, routed)          0.341     2.120    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_4[10]
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[10]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.976     1.550    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.390ns  (logic 0.039ns (9.997%)  route 0.351ns (90.003%))
  Logic Levels:           0  
  Clock Path Skew:        -0.183ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.554ns
    Source Clock Delay      (SCD):    1.737ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.801ns (routing 0.230ns, distribution 0.571ns)
  Clock Net Delay (Destination): 0.980ns (routing 0.255ns, distribution 0.725ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.801     1.737    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X85Y17         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y17         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.776 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/Q
                         net (fo=15, routed)          0.351     2.127    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_2[12]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.980     1.554    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.390ns  (logic 0.039ns (9.997%)  route 0.351ns (90.003%))
  Logic Levels:           0  
  Clock Path Skew:        -0.187ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.550ns
    Source Clock Delay      (SCD):    1.737ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.801ns (routing 0.230ns, distribution 0.571ns)
  Clock Net Delay (Destination): 0.976ns (routing 0.255ns, distribution 0.721ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.801     1.737    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X85Y17         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X85Y17         FDRE (Prop_DFF_SLICEL_C_Q)
                                                      0.039     1.776 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[12]/Q
                         net (fo=15, routed)          0.351     2.127    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_4[12]
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[12]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.976     1.550    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.405ns  (logic 0.038ns (9.386%)  route 0.367ns (90.614%))
  Logic Levels:           0  
  Clock Path Skew:        -0.239ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.485ns
    Source Clock Delay      (SCD):    1.724ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.788ns (routing 0.230ns, distribution 0.558ns)
  Clock Net Delay (Destination): 0.912ns (routing 0.255ns, distribution 0.657ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.788     1.724    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/c0_riu_clk
    SLICE_X96Y40         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X96Y40         FDRE (Prop_AFF_SLICEM_C_Q)
                                                      0.038     1.762 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_mb_logic_r1_reg/Q
                         net (fo=5, routed)           0.367     2.129    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/ext_reset_in
    SLICE_X95Y2          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/D
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.912     1.485    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/slowest_sync_clk
    SLICE_X95Y2          FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_riu/mcs0/inst/rst_0/U0/EXT_LPF/ACTIVE_HIGH_EXT.ACT_HI_EXT/GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[13]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.390ns  (logic 0.038ns (9.737%)  route 0.352ns (90.263%))
  Logic Levels:           0  
  Clock Path Skew:        -0.188ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.554ns
    Source Clock Delay      (SCD):    1.741ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.805ns (routing 0.230ns, distribution 0.575ns)
  Clock Net Delay (Destination): 0.980ns (routing 0.255ns, distribution 0.725ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.805     1.741    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y20         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y20         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     1.779 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[13]/Q
                         net (fo=15, routed)          0.352     2.132    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_2[13]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[13]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.980     1.554    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[13]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.390ns  (logic 0.038ns (9.737%)  route 0.352ns (90.263%))
  Logic Levels:           0  
  Clock Path Skew:        -0.192ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.550ns
    Source Clock Delay      (SCD):    1.741ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.805ns (routing 0.230ns, distribution 0.575ns)
  Clock Net Delay (Destination): 0.976ns (routing 0.255ns, distribution 0.721ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.805     1.741    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X82Y20         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[13]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X82Y20         FDRE (Prop_BFF_SLICEM_C_Q)
                                                      0.038     1.779 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[13]/Q
                         net (fo=15, routed)          0.352     2.132    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_4[13]
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[13]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.976     1.550    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.392ns  (logic 0.039ns (9.947%)  route 0.353ns (90.053%))
  Logic Levels:           0  
  Clock Path Skew:        -0.189ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.554ns
    Source Clock Delay      (SCD):    1.742ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.806ns (routing 0.230ns, distribution 0.576ns)
  Clock Net Delay (Destination): 0.980ns (routing 0.255ns, distribution 0.725ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.806     1.742    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X83Y14         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y14         FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.781 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[2]/Q
                         net (fo=15, routed)          0.353     2.135    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control_2[2]
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[2]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.980     1.554    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y2
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[0].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[2]
                            (rising edge-triggered cell BITSLICE_CONTROL clocked by mmcm_clkout6  {rise@0.000ns fall@3.001ns period=6.001ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.392ns  (logic 0.039ns (9.947%)  route 0.353ns (90.053%))
  Logic Levels:           0  
  Clock Path Skew:        -0.193ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.550ns
    Source Clock Delay      (SCD):    1.742ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Uncertainty:      0.068ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.117ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      0.806ns (routing 0.230ns, distribution 0.576ns)
  Clock Net Delay (Destination): 0.976ns (routing 0.255ns, distribution 0.721ns)
  Timing Exception:       False Path

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.156     0.919    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.936 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.806     1.742    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/riu_clk
    SLICE_X83Y14         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X83Y14         FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.039     1.781 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/clb2riu_wr_data_reg[2]/Q
                         net (fo=15, routed)          0.353     2.135    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control_4[2]
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_WR_DATA[2]
  -------------------------------------------------------------------    -------------------

                         (clock mmcm_clkout6 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.247     0.673    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT6)
                                                     -0.295     0.378 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT6
                         net (fo=1, routed)           0.177     0.555    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout6
    BUFGCE_X0Y41         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.574 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_riuClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=1657, routed)        0.976     1.550    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/riu_clk
    BITSLICE_CONTROL_X0Y3
                         BITSLICE_CONTROL                             r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/generate_block1.u_ddr_xiphy/byte_num[1].xiphy_byte_wrapper.u_xiphy_byte_wrapper/I_CONTROL[1].GEN_I_CONTROL.u_xiphy_control/xiphy_control/RIU_CLK





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_0
  To Clock:  

Max Delay            44 Endpoints
Min Delay            44 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/brd_sel_gpio/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[0]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            DB_1V8_BRD_SEL
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        5.928ns  (logic 2.393ns (40.367%)  route 3.535ns (59.633%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.141ns (routing 0.670ns, distribution 1.471ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.141     2.367    d_1_i/brd_sel_gpio/U0/gpio_core_1/s_axi_aclk
    SLICE_X30Y123        FDRE                                         r  d_1_i/brd_sel_gpio/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[0]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y123        FDRE (Prop_AFF2_SLICEM_C_Q)
                                                      0.080     2.447 r  d_1_i/brd_sel_gpio/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[0]_lopt_replica/Q
                         net (fo=1, routed)           3.535     5.982    lopt
    AU10                 OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      2.313     8.295 r  DB_1V8_BRD_SEL_OBUF_inst/O
                         net (fo=0)                   0.000     8.295    DB_1V8_BRD_SEL
    AU10                                                              r  DB_1V8_BRD_SEL (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/brd_sel_gpio/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[2]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            DB_1V8_BRD_SEL_SEL1
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        5.515ns  (logic 2.400ns (43.521%)  route 3.115ns (56.479%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.141ns (routing 0.670ns, distribution 1.471ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.141     2.367    d_1_i/brd_sel_gpio/U0/gpio_core_1/s_axi_aclk
    SLICE_X30Y123        FDRE                                         r  d_1_i/brd_sel_gpio/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[2]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y123        FDRE (Prop_CFF2_SLICEM_C_Q)
                                                      0.077     2.444 r  d_1_i/brd_sel_gpio/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[2]_lopt_replica/Q
                         net (fo=1, routed)           3.115     5.559    lopt_2
    AV9                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      2.323     7.883 r  DB_1V8_BRD_SEL_SEL1_OBUF_inst/O
                         net (fo=0)                   0.000     7.883    DB_1V8_BRD_SEL_SEL1
    AV9                                                               r  DB_1V8_BRD_SEL_SEL1 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/brd_sel_gpio/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[1]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            DB_1V8_BRD_SEL_SEL2
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        5.457ns  (logic 2.395ns (43.884%)  route 3.062ns (56.116%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.141ns (routing 0.670ns, distribution 1.471ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.141     2.367    d_1_i/brd_sel_gpio/U0/gpio_core_1/s_axi_aclk
    SLICE_X30Y123        FDRE                                         r  d_1_i/brd_sel_gpio/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[1]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X30Y123        FDRE (Prop_BFF2_SLICEM_C_Q)
                                                      0.080     2.447 r  d_1_i/brd_sel_gpio/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[1]_lopt_replica/Q
                         net (fo=1, routed)           3.062     5.509    lopt_3
    AW11                 OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      2.315     7.824 r  DB_1V8_BRD_SEL_SEL2_OBUF_inst/O
                         net (fo=0)                   0.000     7.824    DB_1V8_BRD_SEL_SEL2
    AW11                                                              r  DB_1V8_BRD_SEL_SEL2 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Serial_Dout_reg/C
                            (rising edge-triggered cell FDSE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            DAC_1V8_BIAS_SDIN
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        5.473ns  (logic 2.448ns (44.739%)  route 3.024ns (55.261%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.109ns (routing 0.670ns, distribution 1.439ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.109     2.335    d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/ext_spi_clk
    SLICE_X56Y119        FDSE                                         r  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Serial_Dout_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X56Y119        FDSE (Prop_HFF_SLICEM_C_Q)
                                                      0.079     2.414 r  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/OTHER_RATIO_GENERATE.Serial_Dout_reg/Q
                         net (fo=3, routed)           3.024     5.438    DAC_1V8_BIAS_SDIN_OBUF
    F14                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      2.369     7.808 r  DAC_1V8_BIAS_SDIN_OBUF_inst/O
                         net (fo=0)                   0.000     7.808    DAC_1V8_BIAS_SDIN
    F14                                                               r  DAC_1V8_BIAS_SDIN (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.779ns  (logic 0.028ns (1.008%)  route 2.751ns (98.992%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.553     7.779    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFDAC_X0Y3           RFDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.758ns  (logic 0.028ns (1.015%)  route 2.730ns (98.985%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.532     7.758    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFDAC_X0Y2           RFDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.751ns  (logic 0.028ns (1.018%)  route 2.723ns (98.982%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.525     7.751    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFDAC_X0Y1           RFDAC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/pmod_led_gpio/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[4]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            PMOD_LED3
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        5.440ns  (logic 2.443ns (44.905%)  route 2.997ns (55.095%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.080ns (routing 0.670ns, distribution 1.410ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.080     2.306    d_1_i/pmod_led_gpio/U0/gpio_core_1/s_axi_aclk
    SLICE_X57Y142        FDRE                                         r  d_1_i/pmod_led_gpio/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[4]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y142        FDRE (Prop_FFF2_SLICEL_C_Q)
                                                      0.081     2.387 r  d_1_i/pmod_led_gpio/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[4]_lopt_replica/Q
                         net (fo=1, routed)           2.997     5.384    lopt_15
    G16                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      2.362     7.746 r  PMOD_LED3_OBUF_inst/O
                         net (fo=0)                   0.000     7.746    PMOD_LED3
    G16                                                               r  PMOD_LED3 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/pmod_led_gpio/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[1]_lopt_replica/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            PMOD_LED6
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        5.434ns  (logic 2.466ns (45.383%)  route 2.968ns (54.617%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      2.080ns (routing 0.670ns, distribution 1.410ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     0.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     0.226 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.080     2.306    d_1_i/pmod_led_gpio/U0/gpio_core_1/s_axi_aclk
    SLICE_X57Y142        FDRE                                         r  d_1_i/pmod_led_gpio/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[1]_lopt_replica/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y142        FDRE (Prop_EFF2_SLICEL_C_Q)
                                                      0.081     2.387 r  d_1_i/pmod_led_gpio/U0/gpio_core_1/Not_Dual.gpio_Data_Out_reg[1]_lopt_replica/Q
                         net (fo=1, routed)           2.968     5.355    lopt_18
    J14                  OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      2.385     7.740 r  PMOD_LED6_OBUF_inst/O
                         net (fo=0)                   0.000     7.740    PMOD_LED6
    J14                                                               r  PMOD_LED6 (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.732ns  (logic 0.028ns (1.025%)  route 2.704ns (98.975%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 fall edge)
                                                      5.000     5.000 f  
    PS8_X0Y0             PS8                          0.000     5.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.198     5.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028     5.226 f  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       2.506     7.732    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFADC_X0Y0           RFADC                                        f  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.451ns  (logic 0.017ns (1.172%)  route 1.434ns (98.828%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.331     1.451    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFADC_X0Y3           RFADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.456ns  (logic 0.017ns (1.168%)  route 1.439ns (98.832%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.336     1.456    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFADC_X0Y2           RFADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.469ns  (logic 0.017ns (1.157%)  route 1.452ns (98.843%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.349     1.469    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFADC_X0Y1           RFADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx1_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.469ns  (logic 0.017ns (1.157%)  route 1.452ns (98.843%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.349     1.469    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFDAC_X0Y0           RFDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.482ns  (logic 0.017ns (1.147%)  route 1.465ns (98.853%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.362     1.482    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFDAC_X0Y1           RFDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx1_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.486ns  (logic 0.017ns (1.144%)  route 1.469ns (98.856%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.366     1.486    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFADC_X0Y0           RFADC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.495ns  (logic 0.017ns (1.137%)  route 1.478ns (98.863%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.375     1.495    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFDAC_X0Y2           RFDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx2_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                            (clock source 'clk_pl_0'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/PLL_MONCLK
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.511ns  (logic 0.017ns (1.125%)  route 1.494ns (98.875%))
  Logic Levels:           1  (BUFG_PS=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.391     1.511    d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/s_axi_aclk
    RFDAC_X0Y3           RFDAC                                        r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/PLL_MONCLK
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            DB_1V8_PE_CLK
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.231ns  (logic 1.229ns (99.838%)  route 0.002ns (0.162%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.353ns (routing 0.363ns, distribution 0.990ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.353     1.473    d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/ext_spi_clk
    HDIOLOGIC_S_X0Y6     FDRE                                         r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
  -------------------------------------------------------------------    -------------------
    HDIOLOGIC_S_X0Y6     FDRE (Prop_OPFF_HDIOLOGIC_S_C_Q)
                                                      0.173     1.646 r  d_1_i/attn_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/Q
                         net (fo=1, routed)           0.002     1.648    DB_1V8_PE_CLK_OBUF
    AV10                 OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      1.056     2.704 r  DB_1V8_PE_CLK_OBUF_inst/O
                         net (fo=0)                   0.000     2.704    DB_1V8_PE_CLK
    AV10                                                              r  DB_1V8_PE_CLK (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            DB_1V8_SER_CLK
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.229ns  (logic 1.227ns (99.837%)  route 0.002ns (0.163%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Source):      1.361ns (routing 0.363ns, distribution 0.998ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.361     1.481    d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/ext_spi_clk
    HDIOLOGIC_S_X0Y11    FDRE                                         r  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/C
  -------------------------------------------------------------------    -------------------
    HDIOLOGIC_S_X0Y11    FDRE (Prop_OPFF_HDIOLOGIC_S_C_Q)
                                                      0.173     1.654 r  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/QSPI_LEGACY_MD_GEN.QSPI_CORE_INTERFACE_I/LOGIC_FOR_MD_0_GEN.SPI_MODULE_I/RATIO_NOT_EQUAL_4_GENERATE.SCK_O_NQ_4_NO_STARTUP_USED.SCK_O_NE_4_FDRE_INST/Q
                         net (fo=1, routed)           0.002     1.656    DB_1V8_SER_CLK_OBUF
    AP10                 OBUF (Prop_OUTBUF_HDIOB_S_I_O)
                                                      1.054     2.710 r  DB_1V8_SER_CLK_OBUF_inst/O
                         net (fo=0)                   0.000     2.710    DB_1V8_SER_CLK
    AP10                                                              r  DB_1V8_SER_CLK (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk_pl_1
  To Clock:  

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[1]
                            (clock source 'clk_pl_1'  {rise@0.000ns fall@250.000ns period=500.000ns})
  Destination:            TWOMHZ_1V8_PWR_SYNC
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.853ns  (logic 2.333ns (48.070%)  route 2.520ns (51.930%))
  Logic Levels:           2  (BUFG_PS=1 OBUF=1)
  Clock Uncertainty:      0.683ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    1.365ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_1 fall edge)
                                                    250.000   250.000 f  
    PS8_X0Y0             PS8                          0.000   250.000 f  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[1]
                         net (fo=1, routed)           0.198   250.198    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk1
    BUFG_PS_X0Y57        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.028   250.226 f  d_1_i/zynq_ultra_ps_e_0/inst/pl_clk1_BUFG_inst/O
                         net (fo=1, routed)           2.322   252.548    TWOMHZ_1V8_PWR_SYNC_OBUF
    AU12                 OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      2.305   254.853 f  TWOMHZ_1V8_PWR_SYNC_OBUF_inst/O
                         net (fo=0)                   0.000   254.853    TWOMHZ_1V8_PWR_SYNC
    AU12                                                              f  TWOMHZ_1V8_PWR_SYNC (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[1]
                            (clock source 'clk_pl_1'  {rise@0.000ns fall@250.000ns period=500.000ns})
  Destination:            TWOMHZ_1V8_PWR_SYNC
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.440ns  (logic 1.065ns (43.639%)  route 1.375ns (56.361%))
  Logic Levels:           2  (BUFG_PS=1 OBUF=1)
  Clock Uncertainty:      0.683ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    1.365ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk_pl_1 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[1]
                         net (fo=1, routed)           0.103     0.103    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk1
    BUFG_PS_X0Y57        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.017     0.120 r  d_1_i/zynq_ultra_ps_e_0/inst/pl_clk1_BUFG_inst/O
                         net (fo=1, routed)           1.272     1.392    TWOMHZ_1V8_PWR_SYNC_OBUF
    AU12                 OBUF (Prop_OUTBUF_HDIOB_M_I_O)
                                                      1.048     2.440 r  TWOMHZ_1V8_PWR_SYNC_OBUF_inst/O
                         net (fo=0)                   0.000     2.440    TWOMHZ_1V8_PWR_SYNC
    AU12                                                              r  TWOMHZ_1V8_PWR_SYNC (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  mmcm_clkout0
  To Clock:  

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            ddr4_sdram_c0_reset_n
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        2.202ns  (logic 0.887ns (40.282%)  route 1.315ns (59.718%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.156ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      1.453ns (routing 0.415ns, distribution 1.038ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.519     0.519 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.569    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.569 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.402     0.971    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.127     0.844 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.245     1.089    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.028     1.117 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       1.453     2.570    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X84Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y79         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.080     2.650 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/Q
                         net (fo=1, routed)           1.315     3.965    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/cal_RESET_n[0]
    AH20                 OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.807     4.772 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/OBUF_reset_n/O
                         net (fo=0)                   0.000     4.772    ddr4_sdram_c0_reset_n
    AH20                                                              r  ddr4_sdram_c0_reset_n (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by mmcm_clkout0  {rise@0.000ns fall@1.500ns period=3.001ns})
  Destination:            ddr4_sdram_c0_reset_n
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.015ns  (logic 0.420ns (41.382%)  route 0.595ns (58.618%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.156ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.103ns
    Phase Error              (PE):    0.099ns
  Clock Net Delay (Source):      0.797ns (routing 0.230ns, distribution 0.567ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock mmcm_clkout0 rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.277     0.277 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.317    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.317 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.216     0.533    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clk_in
    MMCM_X0Y1            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.230     0.763 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.146     0.909    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_clkout0
    BUFGCE_X0Y39         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.017     0.926 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_divClk/O
    X4Y1 (CLOCK_ROOT)    net (fo=27067, routed)       0.797     1.723    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/dReg_reg[13]
    SLICE_X84Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X84Y79         FDRE (Prop_HFF2_SLICEL_C_Q)
                                                      0.039     1.762 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/Q
                         net (fo=1, routed)           0.595     2.357    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/cal_RESET_n[0]
    AH20                 OBUF (Prop_OUTBUF_HPIOB_M_I_O)
                                                      0.381     2.738 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/OBUF_reset_n/O
                         net (fo=0)                   0.000     2.738    ddr4_sdram_c0_reset_n
    AH20                                                              r  ddr4_sdram_c0_reset_n (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_out1_d_1_clk_core_0

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.313ns  (logic 0.037ns (2.818%)  route 1.276ns (97.182%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 1.683ns (routing 0.863ns, distribution 0.820ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y2            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           1.210     1.210    d_1_i/rst_core/U0/EXT_LPF/dcm_locked
    SLICE_X75Y222        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.037     1.247 r  d_1_i/rst_core/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.066     1.313    d_1_i/rst_core/U0/EXT_LPF/lpf_int0__0
    SLICE_X75Y222        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.884     2.066    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                      0.630     2.696 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.215     2.911    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     2.935 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.683     4.618    d_1_i/rst_core/U0/EXT_LPF/slowest_sync_clk
    SLICE_X75Y222        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
                            (rising edge-triggered cell FDRE clocked by clk_out1_d_1_clk_core_0  {rise@0.000ns fall@2.500ns period=5.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.651ns  (logic 0.014ns (2.151%)  route 0.637ns (97.849%))
  Logic Levels:           1  (LUT4=1)
  Clock Uncertainty:      0.143ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.100ns
    Phase Error              (PE):    0.087ns
  Clock Net Delay (Destination): 1.180ns (routing 0.574ns, distribution 0.606ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y2            MMCME4_ADV                   0.000     0.000 f  d_1_i/clk_core/inst/mmcme4_adv_inst/LOCKED
                         net (fo=1, routed)           0.613     0.613    d_1_i/rst_core/U0/EXT_LPF/dcm_locked
    SLICE_X75Y222        LUT4 (Prop_C6LUT_SLICEM_I0_O)
                                                      0.014     0.627 r  d_1_i/rst_core/U0/EXT_LPF/lpf_int0/O
                         net (fo=1, routed)           0.024     0.651    d_1_i/rst_core/U0/EXT_LPF/lpf_int0__0
    SLICE_X75Y222        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_out1_d_1_clk_core_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
                         net (fo=81110, routed)       1.280     1.427    d_1_i/clk_core/inst/clk_in1
    MMCM_X0Y2            MMCME4_ADV (Prop_MMCM_CLKIN1_CLKOUT0)
                                                     -0.295     1.132 r  d_1_i/clk_core/inst/mmcme4_adv_inst/CLKOUT0
                         net (fo=1, routed)           0.166     1.298    d_1_i/clk_core/inst/clk_out1_d_1_clk_core_0
    BUFGCE_X0Y54         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     1.317 r  d_1_i/clk_core/inst/clkout1_buf/O
    X2Y3 (CLOCK_ROOT)    net (fo=3281, routed)        1.180     2.497    d_1_i/rst_core/U0/EXT_LPF/slowest_sync_clk
    SLICE_X75Y222        FDRE                                         r  d_1_i/rst_core/U0/EXT_LPF/lpf_int_reg/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  clk_pl_0

Max Delay            17 Endpoints
Min Delay            17 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[1]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.265ns  (logic 0.345ns (8.089%)  route 3.920ns (91.911%))
  Logic Levels:           3  (LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.094ns (routing 0.606ns, distribution 1.488ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[1]
                         net (fo=2, routed)           3.231     3.231    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[1]
    SLICE_X105Y218       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.123     3.354 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_14/O
                         net (fo=1, routed)           0.138     3.492    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_14_n_0
    SLICE_X106Y218       LUT6 (Prop_B6LUT_SLICEL_I3_O)
                                                      0.124     3.616 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_4/O
                         net (fo=1, routed)           0.485     4.101    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_4_n_0
    SLICE_X103Y209       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.098     4.199 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[1]_i_1/O
                         net (fo=1, routed)           0.066     4.265    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_83
    SLICE_X103Y209       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.094     2.276    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y209       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[1]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[2]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.228ns  (logic 0.481ns (11.377%)  route 3.747ns (88.623%))
  Logic Levels:           5  (LUT6=5)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.101ns (routing 0.606ns, distribution 1.495ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[2]
                         net (fo=1, routed)           2.794     2.794    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[2]
    SLICE_X100Y222       LUT6 (Prop_C6LUT_SLICEL_I0_O)
                                                      0.146     2.940 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_121/O
                         net (fo=1, routed)           0.135     3.075    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_121_n_0
    SLICE_X100Y217       LUT6 (Prop_E6LUT_SLICEL_I4_O)
                                                      0.051     3.126 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_58/O
                         net (fo=1, routed)           0.269     3.395    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_58_n_0
    SLICE_X105Y219       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.089     3.484 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_20/O
                         net (fo=1, routed)           0.134     3.618    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_20_n_0
    SLICE_X106Y219       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.097     3.715 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_6/O
                         net (fo=1, routed)           0.349     4.064    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_6_n_0
    SLICE_X103Y204       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.098     4.162 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[2]_i_1/O
                         net (fo=1, routed)           0.066     4.228    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_82
    SLICE_X103Y204       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.101     2.283    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y204       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[2]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[22]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.911ns  (logic 0.421ns (10.764%)  route 3.490ns (89.236%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.100ns (routing 0.606ns, distribution 1.494ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[22]
                         net (fo=2, routed)           2.746     2.746    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[22]
    SLICE_X102Y219       LUT4 (Prop_D6LUT_SLICEL_I3_O)
                                                      0.099     2.845 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_80/O
                         net (fo=1, routed)           0.091     2.936    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_80_n_0
    SLICE_X103Y219       LUT5 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.100     3.036 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_32/O
                         net (fo=1, routed)           0.241     3.277    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_32_n_0
    SLICE_X105Y216       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.097     3.374 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_11/O
                         net (fo=1, routed)           0.092     3.466    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_11_n_0
    SLICE_X105Y214       LUT5 (Prop_G6LUT_SLICEL_I3_O)
                                                      0.035     3.501 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_3/O
                         net (fo=1, routed)           0.262     3.763    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_3_n_0
    SLICE_X104Y207       LUT6 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.090     3.853 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[0]_i_1/O
                         net (fo=1, routed)           0.058     3.911    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_84
    SLICE_X104Y207       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.100     2.282    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y207       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[0]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[22]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.664ns  (logic 0.313ns (8.542%)  route 3.351ns (91.458%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.106ns (routing 0.606ns, distribution 1.500ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[22]
                         net (fo=2, routed)           2.801     2.801    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[22]
    SLICE_X100Y215       LUT6 (Prop_G6LUT_SLICEL_I2_O)
                                                      0.123     2.924 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[22]_i_29/O
                         net (fo=1, routed)           0.044     2.968    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[22]_i_29_n_0
    SLICE_X100Y215       LUT6 (Prop_H6LUT_SLICEL_I2_O)
                                                      0.051     3.019 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[22]_i_15/O
                         net (fo=1, routed)           0.142     3.161    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[22]_i_15_n_0
    SLICE_X101Y215       LUT5 (Prop_C6LUT_SLICEL_I3_O)
                                                      0.050     3.211 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[22]_i_6/O
                         net (fo=1, routed)           0.315     3.526    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[22]_i_6_n_0
    SLICE_X102Y199       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.089     3.615 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[22]_i_1/O
                         net (fo=1, routed)           0.049     3.664    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_62
    SLICE_X102Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.106     2.288    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X102Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[22]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[4]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.522ns  (logic 0.321ns (9.114%)  route 3.201ns (90.886%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.104ns (routing 0.606ns, distribution 1.498ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[4]
                         net (fo=1, routed)           2.385     2.385    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[4]
    SLICE_X106Y220       LUT6 (Prop_C6LUT_SLICEL_I1_O)
                                                      0.035     2.420 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_38/O
                         net (fo=1, routed)           0.190     2.610    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_38_n_0
    SLICE_X105Y220       LUT6 (Prop_G6LUT_SLICEL_I1_O)
                                                      0.050     2.660 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_15/O
                         net (fo=1, routed)           0.239     2.899    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_15_n_0
    SLICE_X104Y217       LUT6 (Prop_E6LUT_SLICEM_I4_O)
                                                      0.091     2.990 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_3/O
                         net (fo=1, routed)           0.321     3.311    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_3_n_0
    SLICE_X104Y205       LUT6 (Prop_C6LUT_SLICEM_I1_O)
                                                      0.145     3.456 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/O
                         net (fo=1, routed)           0.066     3.522    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_80
    SLICE_X104Y205       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.104     2.286    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y205       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[7]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.485ns  (logic 0.428ns (12.281%)  route 3.057ns (87.719%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.115ns (routing 0.606ns, distribution 1.509ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[7]
                         net (fo=1, routed)           2.389     2.389    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[7]
    SLICE_X105Y219       LUT6 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.123     2.512 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_46/O
                         net (fo=1, routed)           0.139     2.651    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_46_n_0
    SLICE_X104Y219       LUT6 (Prop_G6LUT_SLICEM_I3_O)
                                                      0.090     2.741 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_25/O
                         net (fo=1, routed)           0.050     2.791    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_25_n_0
    SLICE_X104Y219       LUT6 (Prop_B6LUT_SLICEM_I1_O)
                                                      0.125     2.916 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_6/O
                         net (fo=1, routed)           0.428     3.344    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_6_n_0
    SLICE_X106Y202       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.090     3.434 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/O
                         net (fo=1, routed)           0.051     3.485    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_77
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.115     2.297    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[16]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.417ns  (logic 0.412ns (12.057%)  route 3.005ns (87.943%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.080ns (routing 0.606ns, distribution 1.474ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[16]
                         net (fo=1, routed)           2.516     2.516    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[16]
    SLICE_X99Y218        LUT6 (Prop_H6LUT_SLICEM_I4_O)
                                                      0.152     2.668 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_12/O
                         net (fo=1, routed)           0.105     2.773    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_12_n_0
    SLICE_X100Y219       LUT6 (Prop_H6LUT_SLICEL_I5_O)
                                                      0.150     2.923 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_4/O
                         net (fo=1, routed)           0.369     3.292    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_4_n_0
    SLICE_X100Y207       LUT5 (Prop_D5LUT_SLICEL_I2_O)
                                                      0.110     3.402 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_1/O
                         net (fo=1, routed)           0.015     3.417    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X100Y207       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[16]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.080     2.262    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X100Y207       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[16]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[20]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.410ns  (logic 0.335ns (9.824%)  route 3.075ns (90.176%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.126ns (routing 0.606ns, distribution 1.520ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[20]
                         net (fo=1, routed)           2.454     2.454    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[20]
    SLICE_X100Y218       LUT5 (Prop_E6LUT_SLICEL_I1_O)
                                                      0.147     2.601 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_8/O
                         net (fo=1, routed)           0.040     2.641    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_8_n_0
    SLICE_X100Y218       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.089     2.730 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_2/O
                         net (fo=1, routed)           0.509     3.239    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_2_n_0
    SLICE_X104Y191       LUT6 (Prop_D6LUT_SLICEM_I0_O)
                                                      0.099     3.338 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_1/O
                         net (fo=1, routed)           0.072     3.410    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_64
    SLICE_X104Y191       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.126     2.308    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y191       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[20]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[19]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[19]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.407ns  (logic 0.408ns (11.975%)  route 2.999ns (88.025%))
  Logic Levels:           4  (LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.100ns (routing 0.606ns, distribution 1.494ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y3           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx3_u_dac/STATUS_COMMON[19]
                         net (fo=1, routed)           2.420     2.420    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_6_1[19]
    SLICE_X99Y218        LUT6 (Prop_F6LUT_SLICEM_I2_O)
                                                      0.088     2.508 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_33/O
                         net (fo=1, routed)           0.041     2.549    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_33_n_0
    SLICE_X99Y218        LUT6 (Prop_G6LUT_SLICEM_I2_O)
                                                      0.052     2.601 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_16/O
                         net (fo=1, routed)           0.146     2.747    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_16_n_0
    SLICE_X101Y219       LUT6 (Prop_G6LUT_SLICEL_I0_O)
                                                      0.123     2.870 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_6/O
                         net (fo=1, routed)           0.320     3.190    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_6_n_0
    SLICE_X103Y205       LUT6 (Prop_D6LUT_SLICEM_I5_O)
                                                      0.145     3.335 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[19]_i_1/O
                         net (fo=1, routed)           0.072     3.407    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_65
    SLICE_X103Y205       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[19]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.100     2.282    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X103Y205       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[19]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[3]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        3.381ns  (logic 0.419ns (12.393%)  route 2.962ns (87.607%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 2.118ns (routing 0.606ns, distribution 1.512ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y0           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx0_u_adc/STATUS_COMMON[3]
                         net (fo=1, routed)           1.999     1.999    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/STATUS_COMMON[3]
    SLICE_X105Y186       LUT6 (Prop_H6LUT_SLICEL_I0_O)
                                                      0.090     2.089 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_108/O
                         net (fo=1, routed)           0.242     2.331    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_108_n_0
    SLICE_X105Y186       LUT6 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.089     2.420 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_47/O
                         net (fo=1, routed)           0.237     2.657    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_47_n_0
    SLICE_X103Y186       LUT6 (Prop_C6LUT_SLICEM_I2_O)
                                                      0.098     2.755 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_14/O
                         net (fo=1, routed)           0.039     2.794    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_14_n_0
    SLICE_X103Y186       LUT5 (Prop_B6LUT_SLICEM_I2_O)
                                                      0.089     2.883 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_4/O
                         net (fo=1, routed)           0.387     3.270    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_4_n_0
    SLICE_X104Y196       LUT6 (Prop_H6LUT_SLICEM_I2_O)
                                                      0.053     3.323 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[3]_i_1/O
                         net (fo=1, routed)           0.058     3.381    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_81
    SLICE_X104Y196       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.157     0.157    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.025     0.182 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       2.118     2.300    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y196       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[3]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 DB_1V8_SDO
                            (input port)
  Destination:            d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.401ns  (logic 0.351ns (87.532%)  route 0.050ns (12.468%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        1.703ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.703ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.556ns (routing 0.408ns, distribution 1.148ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    AR11                                              0.000     0.000 r  DB_1V8_SDO (IN)
                         net (fo=0)                   0.000     0.000    DB_1V8_SDO_IBUF_inst/I
    AR11                 INBUF (Prop_INBUF_HDIOB_S_PAD_O)
                                                      0.351     0.351 r  DB_1V8_SDO_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.351    DB_1V8_SDO_IBUF_inst/OUT
    AR11                 IBUFCTRL (Prop_IBUFCTRL_HDIOB_S_I_O)
                                                      0.000     0.351 r  DB_1V8_SDO_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.050     0.401    d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/io1_i
    HDIOLOGIC_S_X0Y10    FDRE                                         r  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.556     1.703    d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/ext_spi_clk
    HDIOLOGIC_S_X0Y10    FDRE                                         r  d_1_i/filter_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C

Slack:                    inf
  Source:                 DAC_1V8_BIAS_SDO
                            (input port)
  Destination:            d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.491ns  (logic 0.441ns (89.822%)  route 0.050ns (10.178%))
  Logic Levels:           2  (IBUFCTRL=1 INBUF=1)
  Clock Path Skew:        1.657ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.657ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns
  Clock Net Delay (Destination): 1.510ns (routing 0.408ns, distribution 1.102ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    A14                                               0.000     0.000 r  DAC_1V8_BIAS_SDO (IN)
                         net (fo=0)                   0.000     0.000    DAC_1V8_BIAS_SDO_IBUF_inst/I
    A14                  INBUF (Prop_INBUF_HDIOB_S_PAD_O)
                                                      0.441     0.441 r  DAC_1V8_BIAS_SDO_IBUF_inst/INBUF_INST/O
                         net (fo=1, routed)           0.000     0.441    DAC_1V8_BIAS_SDO_IBUF_inst/OUT
    A14                  IBUFCTRL (Prop_IBUFCTRL_HDIOB_S_I_O)
                                                      0.000     0.441 r  DAC_1V8_BIAS_SDO_IBUF_inst/IBUFCTRL_INST/O
                         net (fo=1, routed)           0.050     0.491    d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/io1_i
    HDIOLOGIC_S_X0Y22    FDRE                                         r  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.510     1.657    d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/ext_spi_clk
    HDIOLOGIC_S_X0Y22    FDRE                                         r  d_1_i/bias_spi/U0/NO_DUAL_QUAD_MODE.QSPI_NORMAL/IO1_I_REG/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[7]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.654ns  (logic 0.104ns (15.902%)  route 0.550ns (84.098%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.459ns (routing 0.408ns, distribution 1.051ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[7]
                         net (fo=1, routed)           0.341     0.341    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[7]
    SLICE_X107Y202       LUT5 (Prop_B6LUT_SLICEM_I4_O)
                                                      0.014     0.355 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_38/O
                         net (fo=1, routed)           0.044     0.399    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_38_n_0
    SLICE_X107Y202       LUT6 (Prop_C6LUT_SLICEM_I4_O)
                                                      0.014     0.413 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_15/O
                         net (fo=1, routed)           0.049     0.462    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_15_n_0
    SLICE_X107Y199       LUT6 (Prop_E6LUT_SLICEM_I5_O)
                                                      0.035     0.497 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_3/O
                         net (fo=1, routed)           0.099     0.596    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_3_n_0
    SLICE_X106Y202       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.041     0.637 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[7]_i_1/O
                         net (fo=1, routed)           0.017     0.654    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_77
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.459     1.606    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X106Y202       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[7]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[16]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[16]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.708ns  (logic 0.048ns (6.780%)  route 0.660ns (93.220%))
  Logic Levels:           2  (LUT5=1 LUT6=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.434ns (routing 0.408ns, distribution 1.026ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[16]
                         net (fo=1, routed)           0.546     0.546    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][16]
    SLICE_X99Y211        LUT6 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.015     0.561 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_3/O
                         net (fo=1, routed)           0.108     0.669    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_3_n_0
    SLICE_X100Y207       LUT5 (Prop_D5LUT_SLICEL_I1_O)
                                                      0.033     0.702 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[16]_i_1/O
                         net (fo=1, routed)           0.006     0.708    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_68
    SLICE_X100Y207       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[16]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.434     1.581    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X100Y207       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[16]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[17]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[17]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.716ns  (logic 0.131ns (18.296%)  route 0.585ns (81.704%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.464ns (routing 0.408ns, distribution 1.056ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[17]
                         net (fo=1, routed)           0.493     0.493    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[17]
    SLICE_X104Y204       LUT6 (Prop_H6LUT_SLICEM_I5_O)
                                                      0.061     0.554 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[17]_i_11/O
                         net (fo=1, routed)           0.024     0.578    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[17]_i_11_n_0
    SLICE_X104Y204       LUT5 (Prop_F6LUT_SLICEM_I0_O)
                                                      0.035     0.613 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[17]_i_4/O
                         net (fo=1, routed)           0.042     0.655    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[17]_i_4_n_0
    SLICE_X104Y204       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.035     0.690 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[17]_i_1/O
                         net (fo=1, routed)           0.026     0.716    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_67
    SLICE_X104Y204       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[17]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.464     1.611    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y204       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[17]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[23]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[23]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.720ns  (logic 0.051ns (7.083%)  route 0.669ns (92.917%))
  Logic Levels:           3  (LUT6=3)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.456ns (routing 0.408ns, distribution 1.048ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[23]
                         net (fo=1, routed)           0.405     0.405    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[23]
    SLICE_X105Y202       LUT6 (Prop_H6LUT_SLICEL_I1_O)
                                                      0.015     0.420 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_12/O
                         net (fo=1, routed)           0.155     0.575    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_12_n_0
    SLICE_X102Y197       LUT6 (Prop_G6LUT_SLICEL_I5_O)
                                                      0.014     0.589 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3/O
                         net (fo=1, routed)           0.093     0.682    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_n_0
    SLICE_X101Y194       LUT6 (Prop_D6LUT_SLICEL_I1_O)
                                                      0.022     0.704 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_1/O
                         net (fo=1, routed)           0.016     0.720    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_61
    SLICE_X101Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[23]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.456     1.603    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X101Y194       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[23]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[20]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[20]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.747ns  (logic 0.090ns (12.048%)  route 0.657ns (87.952%))
  Logic Levels:           2  (LUT5=1 LUT6=1)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.471ns (routing 0.408ns, distribution 1.063ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y2           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx2_u_adc/STATUS_COMMON[20]
                         net (fo=1, routed)           0.524     0.524    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23]_0[20]
    SLICE_X104Y190       LUT5 (Prop_C6LUT_SLICEM_I3_O)
                                                      0.040     0.564 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_4/O
                         net (fo=1, routed)           0.107     0.671    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_4_n_0
    SLICE_X104Y191       LUT6 (Prop_D6LUT_SLICEM_I2_O)
                                                      0.050     0.721 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[20]_i_1/O
                         net (fo=1, routed)           0.026     0.747    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_64
    SLICE_X104Y191       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[20]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.471     1.618    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y191       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[20]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[22]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[22]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.751ns  (logic 0.149ns (19.836%)  route 0.602ns (80.164%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.454ns (routing 0.408ns, distribution 1.046ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[22]
                         net (fo=2, routed)           0.413     0.413    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[22]
    SLICE_X104Y204       LUT6 (Prop_G6LUT_SLICEM_I5_O)
                                                      0.050     0.463 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[22]_i_7/O
                         net (fo=1, routed)           0.026     0.489    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[22]_i_7_n_0
    SLICE_X104Y204       LUT5 (Prop_E6LUT_SLICEM_I0_O)
                                                      0.040     0.529 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[22]_i_2/O
                         net (fo=1, routed)           0.147     0.676    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[22]_i_2_n_0
    SLICE_X102Y199       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.059     0.735 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[22]_i_1/O
                         net (fo=1, routed)           0.016     0.751    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_62
    SLICE_X102Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[22]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.454     1.601    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X102Y199       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[22]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[4]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.776ns  (logic 0.085ns (10.954%)  route 0.691ns (89.046%))
  Logic Levels:           2  (LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.454ns (routing 0.408ns, distribution 1.046ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFDAC_X0Y0           RFDAC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/tx0_u_dac/STATUS_COMMON[4]
                         net (fo=1, routed)           0.576     0.576    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data_reg[23][4]
    SLICE_X104Y208       LUT6 (Prop_F6LUT_SLICEM_I1_O)
                                                      0.050     0.626 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_7/O
                         net (fo=1, routed)           0.091     0.717    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_7_n_0
    SLICE_X104Y205       LUT6 (Prop_C6LUT_SLICEM_I5_O)
                                                      0.035     0.752 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[4]_i_1/O
                         net (fo=1, routed)           0.024     0.776    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_80
    SLICE_X104Y205       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.454     1.601    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X104Y205       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[4]/C

Slack:                    inf
  Source:                 d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[21]
                            (internal pin)
  Destination:            d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[21]/D
                            (rising edge-triggered cell FDRE clocked by clk_pl_0  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.816ns  (logic 0.131ns (16.054%)  route 0.685ns (83.946%))
  Logic Levels:           3  (LUT5=1 LUT6=2)
  Clock Uncertainty:      0.127ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.250ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.451ns (routing 0.408ns, distribution 1.043ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    RFADC_X0Y3           RFADC                        0.000     0.000 r  d_1_i/usp_rf_data_converter_0/inst/d_1_usp_rf_data_converter_0_0_rf_wrapper_i/rx3_u_adc/STATUS_COMMON[21]
                         net (fo=1, routed)           0.464     0.464    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[23]_i_3_0[21]
    SLICE_X105Y201       LUT6 (Prop_D6LUT_SLICEL_I5_O)
                                                      0.050     0.514 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[21]_i_7/O
                         net (fo=1, routed)           0.046     0.560    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[21]_i_7_n_0
    SLICE_X104Y201       LUT5 (Prop_G6LUT_SLICEM_I0_O)
                                                      0.022     0.582 f  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[21]_i_2/O
                         net (fo=1, routed)           0.159     0.741    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[21]_i_2_n_0
    SLICE_X102Y193       LUT6 (Prop_D6LUT_SLICEL_I0_O)
                                                      0.059     0.800 r  d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif/I_SLAVE_ATTACHMENT/I_DECODER/IP2Bus_Data[21]_i_1/O
                         net (fo=1, routed)           0.016     0.816    d_1_i/usp_rf_data_converter_0/inst/i_axi_lite_ipif_n_63
    SLICE_X102Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[21]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk_pl_0 rise edge)
                                                      0.000     0.000 r  
    PS8_X0Y0             PS8                          0.000     0.000 r  d_1_i/zynq_ultra_ps_e_0/inst/PS8_i/PLCLK[0]
                         net (fo=1, routed)           0.129     0.129    d_1_i/zynq_ultra_ps_e_0/inst/pl_clk_unbuffered[0]
    BUFG_PS_X0Y52        BUFG_PS (Prop_BUFG_PS_I_O)
                                                      0.018     0.147 r  d_1_i/zynq_ultra_ps_e_0/inst/buffer_pl_clk_0.PL_CLK_0_BUFG/O
    X2Y3 (CLOCK_ROOT)    net (fo=81110, routed)       1.451     1.598    d_1_i/usp_rf_data_converter_0/inst/s_axi_aclk
    SLICE_X102Y193       FDRE                                         r  d_1_i/usp_rf_data_converter_0/inst/IP2Bus_Data_reg[21]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK

Max Delay             4 Endpoints
Min Delay             4 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.010ns  (logic 4.353ns (86.890%)  route 0.657ns (13.110%))
  Logic Levels:           2  (BSCANE2=1 LUT4=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.716ns (routing 0.968ns, distribution 0.748ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.599     4.899    dbg_hub/inst/BSCANID.u_xsdbm_id/TDI
    SLICE_X107Y80        LUT4 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.053     4.952 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid[31]_i_1/O
                         net (fo=1, routed)           0.058     5.010    dbg_hub/inst/BSCANID.u_xsdbm_id/p_2_in[31]
    SLICE_X107Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.716     3.187    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X107Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.944ns  (logic 4.448ns (89.963%)  route 0.496ns (10.037%))
  Logic Levels:           2  (BSCANE2=1 LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.705ns (routing 0.968ns, distribution 0.737ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.447     4.747    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X106Y86        LUT2 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.148     4.895 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2/O
                         net (fo=1, routed)           0.049     4.944    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2_n_0
    SLICE_X106Y86        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.705     3.176    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y86        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.938ns  (logic 4.300ns (87.072%)  route 0.638ns (12.928%))
  Logic Levels:           1  (BSCANE2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.714ns (routing 0.968ns, distribution 0.746ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.638     4.938    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/out
    SLICE_X106Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.714     3.185    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X106Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        4.934ns  (logic 4.423ns (89.646%)  route 0.511ns (10.354%))
  Logic Levels:           2  (BSCANE2=1 LUT5=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.711ns (routing 0.968ns, distribution 0.743ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.460     4.760    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X106Y83        LUT5 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.123     4.883 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2/O
                         net (fo=1, routed)           0.051     4.934    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2_n_0
    SLICE_X106Y83        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.982     1.447    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     1.471 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.711     3.182    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y83        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.781ns  (logic 0.525ns (67.196%)  route 0.256ns (32.804%))
  Logic Levels:           2  (BSCANE2=1 LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.207ns (routing 0.658ns, distribution 0.549ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.241     0.706    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X106Y86        LUT2 (Prop_B6LUT_SLICEL_I1_O)
                                                      0.060     0.766 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2/O
                         net (fo=1, routed)           0.015     0.781    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid[31]_i_2_n_0
    SLICE_X106Y86        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.207     6.518    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y86        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/bscanid_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.782ns  (logic 0.465ns (59.485%)  route 0.317ns (40.515%))
  Logic Levels:           1  (BSCANE2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.215ns (routing 0.658ns, distribution 0.557ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.317     0.782    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/out
    SLICE_X106Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.215     6.526    dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/m_bscan_tck[0]
    SLICE_X106Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/CORE_XSDB.U_ICON/iTDI_reg_reg/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.783ns  (logic 0.515ns (65.743%)  route 0.268ns (34.257%))
  Logic Levels:           2  (BSCANE2=1 LUT5=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.213ns (routing 0.658ns, distribution 0.555ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.250     0.715    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tdi
    SLICE_X106Y83        LUT5 (Prop_F6LUT_SLICEL_I2_O)
                                                      0.050     0.765 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2/O
                         net (fo=1, routed)           0.018     0.783    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg[31]_i_2_n_0
    SLICE_X106Y83        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.213     6.524    dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/s_bscan_tck
    SLICE_X106Y83        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_switch/shiftreg_reg[31]/C

Slack:                    inf
  Source:                 dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
                            (internal pin)
  Destination:            dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
                            (rising edge-triggered cell FDRE clocked by dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK  {rise@0.000ns fall@25.000ns period=50.000ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.832ns  (logic 0.488ns (58.667%)  route 0.344ns (41.333%))
  Logic Levels:           2  (BSCANE2=1 LUT4=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 1.216ns (routing 0.658ns, distribution 0.558ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TDI
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TDI_TDI)
                                                      0.465     0.465 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TDI
                         net (fo=4, routed)           0.323     0.788    dbg_hub/inst/BSCANID.u_xsdbm_id/TDI
    SLICE_X107Y80        LUT4 (Prop_H6LUT_SLICEM_I3_O)
                                                      0.023     0.811 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid[31]_i_1/O
                         net (fo=1, routed)           0.021     0.832    dbg_hub/inst/BSCANID.u_xsdbm_id/p_2_in[31]
    SLICE_X107Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/D
  -------------------------------------------------------------------    -------------------

                         (clock dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK rise edge)
                                                      0.000     0.000 r  
    CONFIG_SITE_X0Y0     BSCANE2                      0.000     0.000 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/INTERNAL_TCK
    CONFIG_SITE_X0Y0     BSCANE2 (Prop_BSCAN1_CONFIG_SITE_INTERNAL_TCK_TCK)
                                                      4.300     4.300 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscan_inst/SERIES7_BSCAN.bscan_inst/TCK
                         net (fo=1, routed)           0.992     5.292    dbg_hub/inst/BSCANID.u_xsdbm_id/tck_bs
    BUFGCE_X0Y49         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     5.311 r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.u_bufg_icon_tck/O
    X5Y0 (CLOCK_ROOT)    net (fo=478, routed)         1.216     6.527    dbg_hub/inst/BSCANID.u_xsdbm_id/itck_i
    SLICE_X107Y80        FDRE                                         r  dbg_hub/inst/BSCANID.u_xsdbm_id/SWITCH_N_EXT_BSCAN.bscanid_reg[31]/C





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  default_sysclk_c0_300mhz_clk_p

Max Delay             2 Endpoints
Min Delay             2 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.622ns  (logic 0.251ns (15.475%)  route 1.371ns (84.525%))
  Logic Levels:           2  (LUT2=1 LUT3=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 0.671ns (routing 0.001ns, distribution 0.670ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    PLL_X0Y0             PLLE4_ADV                    0.000     0.000 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/plle_loop[0].gen_plle4.PLLE4_BASE_INST_OTHER/LOCKED
                         net (fo=1, routed)           0.737     0.737    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/pll_lock_i[0]
    SLICE_X81Y73         LUT2 (Prop_E6LUT_SLICEL_I0_O)
                                                      0.090     0.827 f  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/pll_lock_INST_0/O
                         net (fo=1, routed)           0.371     1.198    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/pll_lock
    SLICE_X89Y79         LUT3 (Prop_H5LUT_SLICEM_I2_O)
                                                      0.161     1.359 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.263     1.622    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X89Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     0.762    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.786 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.671     1.457    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X89Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        1.116ns  (logic 0.053ns (4.751%)  route 1.063ns (95.249%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 0.673ns (routing 0.001ns, distribution 0.672ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y1            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.668     0.668    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X89Y79         LUT2 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.053     0.721 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_i_1/O
                         net (fo=1, routed)           0.395     1.116    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg0
    SLICE_X89Y77         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.422     0.422 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.040     0.462    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.462 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.300     0.762    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.024     0.786 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.673     1.459    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X89Y77         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.475ns  (logic 0.021ns (4.421%)  route 0.454ns (95.579%))
  Logic Levels:           1  (LUT3=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 0.497ns (routing 0.001ns, distribution 0.496ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y1            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.343     0.343    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X89Y79         LUT3 (Prop_H5LUT_SLICEM_I0_O)
                                                      0.021     0.364 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_i_1/O
                         net (fo=1, routed)           0.111     0.475    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg0
    SLICE_X89Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.497     1.177    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X89Y79         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_riu_div_reg/C

Slack:                    inf
  Source:                 d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                            (internal pin)
  Destination:            d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
                            (rising edge-triggered cell FDRE clocked by default_sysclk_c0_300mhz_clk_p  {rise@0.000ns fall@1.667ns period=3.334ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.520ns  (logic 0.023ns (4.423%)  route 0.497ns (95.577%))
  Logic Levels:           1  (LUT2=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns
  Clock Net Delay (Destination): 0.498ns (routing 0.001ns, distribution 0.497ns)

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    MMCM_X0Y1            MMCME4_ADV                   0.000     0.000 f  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/gen_mmcme4.u_mmcme_adv_inst/LOCKED
                         net (fo=3, routed)           0.343     0.343    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/mmcm_lock
    SLICE_X89Y79         LUT2 (Prop_H6LUT_SLICEM_I1_O)
                                                      0.023     0.366 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_i_1/O
                         net (fo=1, routed)           0.154     0.520    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg0
    SLICE_X89Y77         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock default_sysclk_c0_300mhz_clk_p rise edge)
                                                      0.000     0.000 r  
    AR20                                              0.000     0.000 r  default_sysclk_c0_300mhz_clk_p (IN)
                         net (fo=0)                   0.000     0.000    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/I
    HPIOBDIFFINBUF_X0Y35 DIFFINBUF (Prop_DIFFINBUF_HPIOBDIFFINBUF_DIFF_IN_P_O)
                                                      0.376     0.376 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/DIFFINBUF_INST/O
                         net (fo=1, routed)           0.050     0.426    d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/OUT
    AR20                 IBUFCTRL (Prop_IBUFCTRL_HPIOB_M_I_O)
                                                      0.000     0.426 r  d_1_i/ddr4_0/inst/u_ddr4_mem_intfc/u_mig_ddr4_phy/inst/u_ddr4_phy_pll/diff_input_clk.u_ibufg_sys_clk/IBUFCTRL_INST/O
                         net (fo=2, routed)           0.235     0.661    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in
    BUFGCE_X0Y46         BUFGCE (Prop_BUFCE_BUFGCE_I_O)
                                                      0.019     0.680 r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/u_bufg_inst/O
    X4Y1 (CLOCK_ROOT)    net (fo=17, routed)          0.498     1.178    d_1_i/ddr4_0/inst/u_ddr4_infrastructure/sys_clk_in_bufg
    SLICE_X89Y77         FDRE                                         r  d_1_i/ddr4_0/inst/u_ddr4_infrastructure/rst_async_mb_reg/C





