move generator channels to match user's daughterboard configuration

QICK running on ZCU216, software version 0.2.282

Firmware configuration (built Fri Sep  6 14:06:32 2024):

	Global clocks (MHz): tProcessor 384.000, RF reference 245.760

	8 signal generator channels:
	0:	axis_signal_gen_v6 - envelope memory 16384 samples (2.667 us)
		fs=6144.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=6144.000 MHz
		DAC tile 0, blk 0 is 0_228, on JHC1
	1:	axis_signal_gen_v6 - envelope memory 16384 samples (2.667 us)
		fs=6144.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=6144.000 MHz
		DAC tile 0, blk 1 is 1_228, on JHC2
	2:	axis_signal_gen_v6 - envelope memory 16384 samples (2.667 us)
		fs=6144.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=6144.000 MHz
		DAC tile 0, blk 2 is 2_228, on JHC1
	3:	axis_signal_gen_v6 - envelope memory 16384 samples (2.667 us)
		fs=6144.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=6144.000 MHz
		DAC tile 0, blk 3 is 3_228, on JHC2
	4:	axis_signal_gen_v6 - envelope memory 16384 samples (2.667 us)
		fs=6144.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=6144.000 MHz
		DAC tile 1, blk 0 is 0_229, on JHC1
	5:	axis_signal_gen_v6 - envelope memory 16384 samples (2.667 us)
		fs=6144.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=6144.000 MHz
		DAC tile 1, blk 1 is 1_229, on JHC2
	6:	axis_signal_gen_v6 - envelope memory 8192 samples (1.333 us)
		fs=6144.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=6144.000 MHz
		DAC tile 1, blk 2 is 2_229, on JHC1
	7:	axis_signal_gen_v6 - envelope memory 8192 samples (1.333 us)
		fs=6144.000 MHz, fabric=384.000 MHz, 32-bit DDS, range=6144.000 MHz
		DAC tile 1, blk 3 is 3_229, on JHC2

	2 readout channels:
	0:	axis_dyn_readout_v1 - configured by tProc output 8
		fs=2457.600 MHz, decimated=307.200 MHz, 32-bit DDS, range=2457.600 MHz
		maxlen 16384 accumulated, 1024 decimated (3.333 us)
		triggered by tport 0, pin 0, feedback to tProc input 0
		ADC tile 2, blk 0 is 0_226, on JHC7
	1:	axis_dyn_readout_v1 - configured by tProc output 9
		fs=2457.600 MHz, decimated=307.200 MHz, 32-bit DDS, range=2457.600 MHz
		maxlen 16384 accumulated, 1024 decimated (3.333 us)
		triggered by tport 1, pin 0, feedback to tProc input 1
		ADC tile 2, blk 1 is 1_226, on JHC8

	4 digital output pins:
	0:	SPARE0_1V8
	1:	SPARE1_1V8
	2:	SPARE2_1V8
	3:	SPARE3_1V8

	tProc qick_processor ("v2") rev 21: program memory 4096 words, data memory 4096 words
		external start pin: None

	DDR4 memory buffer: 1073741824 samples (3.495 sec), 128 samples/transfer
		wired to readouts [0, 1]

	MR buffer: 8192 samples (3.333 us), wired to readouts [0, 1]