﻿<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<EDKSYSTEM EDWVERSION="1.2" TIMESTAMP="Tue Feb 13 19:05:43 2024" VIVADOVERSION="2022.1">

  <SYSTEMINFO ARCH="zynquplusRFSOC" BOARD="xilinx.com:zcu111:part0:1.4" DEVICE="xczu28dr" NAME="d_1" PACKAGE="ffvg1517" SPEEDGRADE="-2"/>

  <EXTERNALPORTS>
    <PORT DIR="O" NAME="ATTN_CLK" SIGIS="undef" SIGNAME="attn_spi_sck_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="attn_spi" PORT="sck_o"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="2" NAME="ATTN_LE" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_ss_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="attn_spi" PORT="ss_o"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="ATTN_SI" SIGIS="undef" SIGNAME="attn_spi_io0_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="attn_spi" PORT="io0_o"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="0" NAME="BIAS_CLR" RIGHT="0" SIGIS="undef" SIGNAME="bias_constant_1_dout">
      <CONNECTIONS>
        <CONNECTION INSTANCE="bias_constant_1" PORT="dout"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="3" NAME="BIAS_S" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_ss_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="dac_bias_spi" PORT="ss_o"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="BIAS_SCLK" SIGIS="undef" SIGNAME="dac_bias_spi_sck_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="dac_bias_spi" PORT="sck_o"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="BIAS_SDI" SIGIS="undef" SIGNAME="dac_bias_spi_io0_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="dac_bias_spi" PORT="io0_o"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="BIAS_SDO" SIGIS="undef" SIGNAME="External_Ports_BIAS_SDO">
      <CONNECTIONS>
        <CONNECTION INSTANCE="dac_bias_spi" PORT="io1_i"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="LO_CS0" SIGIS="undef" SIGNAME="lo_spi_mux_v2_0_ss0_out">
      <CONNECTIONS>
        <CONNECTION INSTANCE="lo_spi_mux_v2_0" PORT="ss0_out"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="LO_CS1" SIGIS="undef" SIGNAME="lo_spi_mux_v2_0_ss1_out">
      <CONNECTIONS>
        <CONNECTION INSTANCE="lo_spi_mux_v2_0" PORT="ss1_out"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="LO_CS2" SIGIS="undef" SIGNAME="lo_spi_mux_v2_0_ss2_out">
      <CONNECTIONS>
        <CONNECTION INSTANCE="lo_spi_mux_v2_0" PORT="ss2_out"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="LO_MISO0" SIGIS="undef" SIGNAME="External_Ports_LO_MISO0">
      <CONNECTIONS>
        <CONNECTION INSTANCE="lo_spi_mux_v2_0" PORT="sdo0_in"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="LO_MISO1" SIGIS="undef" SIGNAME="External_Ports_LO_MISO1">
      <CONNECTIONS>
        <CONNECTION INSTANCE="lo_spi_mux_v2_0" PORT="sdo1_in"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="LO_MISO2" SIGIS="undef" SIGNAME="External_Ports_LO_MISO2">
      <CONNECTIONS>
        <CONNECTION INSTANCE="lo_spi_mux_v2_0" PORT="sdo2_in"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="LO_MOSI" SIGIS="undef" SIGNAME="lo_spi_io0_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="lo_spi" PORT="io0_o"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="LO_SCLK" SIGIS="undef" SIGNAME="lo_spi_sck_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="lo_spi" PORT="sck_o"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="0" NAME="LO_SYNC" RIGHT="0" SIGIS="undef" SIGNAME="lo_sync_constant_0_dout">
      <CONNECTIONS>
        <CONNECTION INSTANCE="lo_sync_constant_0" PORT="dout"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="PMOD0_0_LS" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout0">
      <CONNECTIONS>
        <CONNECTION INSTANCE="qick_vec2bit_0" PORT="dout0"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="PMOD0_1_LS" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout1">
      <CONNECTIONS>
        <CONNECTION INSTANCE="qick_vec2bit_0" PORT="dout1"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="PMOD0_2_LS" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout2">
      <CONNECTIONS>
        <CONNECTION INSTANCE="qick_vec2bit_0" PORT="dout2"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="PMOD0_3_LS" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout3">
      <CONNECTIONS>
        <CONNECTION INSTANCE="qick_vec2bit_0" PORT="dout3"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="PMOD0_4_LS" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout4">
      <CONNECTIONS>
        <CONNECTION INSTANCE="qick_vec2bit_0" PORT="dout4"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="PMOD0_5_LS" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout5">
      <CONNECTIONS>
        <CONNECTION INSTANCE="qick_vec2bit_0" PORT="dout5"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="PMOD0_6_LS" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout6">
      <CONNECTIONS>
        <CONNECTION INSTANCE="qick_vec2bit_0" PORT="dout6"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="PMOD0_7_LS" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout7">
      <CONNECTIONS>
        <CONNECTION INSTANCE="qick_vec2bit_0" PORT="dout7"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="PMOD1_0_LS" SIGIS="undef" SIGNAME="External_Ports_PMOD1_0_LS">
      <CONNECTIONS>
        <CONNECTION INSTANCE="qick_processor_0" PORT="proc_start_i"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="PMOD1_1_LS" SIGIS="undef" SIGNAME="External_Ports_PMOD1_1_LS">
      <CONNECTIONS>
        <CONNECTION INSTANCE="qick_processor_0" PORT="proc_stop_i"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="0" NAME="PWR_SYNC" RIGHT="0" SIGIS="undef" SIGNAME="zynq_ultra_ps_e_0_pl_clk1">
      <CONNECTIONS>
        <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk1"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="3" NAME="S" RIGHT="0" SIGIS="undef" SIGNAME="psf_spi_ss_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="psf_spi" PORT="ss_o"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="SCLK" SIGIS="undef" SIGNAME="psf_spi_sck_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="psf_spi" PORT="sck_o"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="SDI" SIGIS="undef" SIGNAME="psf_spi_io0_o">
      <CONNECTIONS>
        <CONNECTION INSTANCE="psf_spi" PORT="io0_o"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="SDO" SIGIS="undef" SIGNAME="External_Ports_SDO">
      <CONNECTIONS>
        <CONNECTION INSTANCE="psf_spi" PORT="io1_i"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="I" NAME="adc0_clk_clk_n" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_adc0_clk_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="adc0_clk_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="I" NAME="adc0_clk_clk_p" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_adc0_clk_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="adc0_clk_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="I" NAME="dac0_clk_clk_n" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_dac0_clk_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="dac0_clk_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="I" NAME="dac0_clk_clk_p" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_dac0_clk_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="dac0_clk_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="I" NAME="dac1_clk_clk_n" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_dac1_clk_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="dac1_clk_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="I" NAME="dac1_clk_clk_p" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_dac1_clk_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="dac1_clk_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="ddr4_pl_act_n" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_act_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_act_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="16" NAME="ddr4_pl_adr" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_adr">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_adr"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" LEFT="1" NAME="ddr4_pl_ba" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_ba">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_ba"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="ddr4_pl_bg" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_bg">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_bg"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="O" NAME="ddr4_pl_ck_c" SIGIS="clk" SIGNAME="ddr4_0_c0_ddr4_ck_c">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_ck_c"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="O" NAME="ddr4_pl_ck_t" SIGIS="clk" SIGNAME="ddr4_0_c0_ddr4_ck_t">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_ck_t"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="ddr4_pl_cke" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_cke">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_cke"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="ddr4_pl_cs_n" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_cs_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_cs_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="7" NAME="ddr4_pl_dm_n" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_dm_dbi_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_dm_dbi_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="63" NAME="ddr4_pl_dq" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_dq">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_dq"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="7" NAME="ddr4_pl_dqs_c" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_dqs_c">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_dqs_c"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="IO" LEFT="7" NAME="ddr4_pl_dqs_t" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_dqs_t">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_dqs_t"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="ddr4_pl_odt" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_odt">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_odt"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="ddr4_pl_reset_n" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_reset_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_reset_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="I" NAME="sys_clk_ddr4_clk_n" SIGIS="clk" SIGNAME="ddr4_0_c0_sys_clk_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_sys_clk_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT CLKFREQUENCY="100000000" DIR="I" NAME="sys_clk_ddr4_clk_p" SIGIS="clk" SIGNAME="ddr4_0_c0_sys_clk_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="ddr4_0" PORT="c0_sys_clk_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="sysref_in_diff_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_sysref_in_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="sysref_in_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="sysref_in_diff_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_sysref_in_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="sysref_in_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout0_v_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout00_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout00_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout0_v_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout00_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout00_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout1_v_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout01_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout01_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout1_v_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout01_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout01_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout2_v_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout02_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout02_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout2_v_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout02_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout02_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout3_v_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout03_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout03_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout3_v_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout03_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout03_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout4_v_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout10_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout10_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout4_v_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout10_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout10_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout5_v_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout11_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout11_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout5_v_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout11_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout11_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout6_v_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout12_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout12_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout6_v_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout12_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout12_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="vin0_v_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vin0_01_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vin0_01_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="vin0_v_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vin0_01_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vin0_01_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="vin1_v_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vin0_23_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vin0_23_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="I" NAME="vin1_v_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vin0_23_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vin0_23_p"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout7_v_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout13_n">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout13_n"/>
      </CONNECTIONS>
    </PORT>
    <PORT DIR="O" NAME="vout7_v_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout13_p">
      <CONNECTIONS>
        <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="vout13_p"/>
      </CONNECTIONS>
    </PORT>
  </EXTERNALPORTS>

  <EXTERNALINTERFACES>
    <BUSINTERFACE BUSNAME="External_Interface_adc0_clk" NAME="adc0_clk" TYPE="TARGET">
      <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
      <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
      <PORTMAPS>
        <PORTMAP LOGICAL="CLK_N" PHYSICAL="adc0_clk_clk_n"/>
        <PORTMAP LOGICAL="CLK_P" PHYSICAL="adc0_clk_clk_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="External_Interface_dac0_clk" NAME="dac0_clk" TYPE="TARGET">
      <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
      <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
      <PORTMAPS>
        <PORTMAP LOGICAL="CLK_N" PHYSICAL="dac0_clk_clk_n"/>
        <PORTMAP LOGICAL="CLK_P" PHYSICAL="dac0_clk_clk_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="External_Interface_dac1_clk" NAME="dac1_clk" TYPE="TARGET">
      <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
      <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
      <PORTMAPS>
        <PORTMAP LOGICAL="CLK_N" PHYSICAL="dac1_clk_clk_n"/>
        <PORTMAP LOGICAL="CLK_P" PHYSICAL="dac1_clk_clk_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="ddr4_0_C0_DDR4" DATAWIDTH="64" NAME="ddr4_pl" TYPE="INITIATOR">
      <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
      <PARAMETER NAME="TIMEPERIOD_PS" VALUE="750"/>
      <PARAMETER NAME="MEMORY_TYPE" VALUE="Components"/>
      <PARAMETER NAME="MEMORY_PART" VALUE="MT40A512M16LY-075"/>
      <PARAMETER NAME="DATA_WIDTH" VALUE="64"/>
      <PARAMETER NAME="CS_ENABLED" VALUE="true"/>
      <PARAMETER NAME="DATA_MASK_ENABLED" VALUE="DM_NO_DBI"/>
      <PARAMETER NAME="SLOT" VALUE="Single"/>
      <PARAMETER NAME="CUSTOM_PARTS" VALUE="no_file_loaded"/>
      <PARAMETER NAME="MEM_ADDR_MAP" VALUE="ROW_COLUMN_BANK"/>
      <PARAMETER NAME="BURST_LENGTH" VALUE="8"/>
      <PARAMETER NAME="AXI_ARBITRATION_SCHEME" VALUE="RD_PRI_REG"/>
      <PARAMETER NAME="CAS_LATENCY" VALUE="19"/>
      <PARAMETER NAME="CAS_WRITE_LATENCY" VALUE="14"/>
      <PORTMAPS>
        <PORTMAP LOGICAL="ACT_N" PHYSICAL="ddr4_pl_act_n"/>
        <PORTMAP LOGICAL="ADR" PHYSICAL="ddr4_pl_adr"/>
        <PORTMAP LOGICAL="BA" PHYSICAL="ddr4_pl_ba"/>
        <PORTMAP LOGICAL="BG" PHYSICAL="ddr4_pl_bg"/>
        <PORTMAP LOGICAL="CK_C" PHYSICAL="ddr4_pl_ck_c"/>
        <PORTMAP LOGICAL="CK_T" PHYSICAL="ddr4_pl_ck_t"/>
        <PORTMAP LOGICAL="CKE" PHYSICAL="ddr4_pl_cke"/>
        <PORTMAP LOGICAL="CS_N" PHYSICAL="ddr4_pl_cs_n"/>
        <PORTMAP LOGICAL="DM_N" PHYSICAL="ddr4_pl_dm_n"/>
        <PORTMAP LOGICAL="DQ" PHYSICAL="ddr4_pl_dq"/>
        <PORTMAP LOGICAL="DQS_C" PHYSICAL="ddr4_pl_dqs_c"/>
        <PORTMAP LOGICAL="DQS_T" PHYSICAL="ddr4_pl_dqs_t"/>
        <PORTMAP LOGICAL="ODT" PHYSICAL="ddr4_pl_odt"/>
        <PORTMAP LOGICAL="RESET_N" PHYSICAL="ddr4_pl_reset_n"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="External_Interface_sys_clk_ddr4" NAME="sys_clk_ddr4" TYPE="TARGET">
      <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
      <PARAMETER NAME="FREQ_HZ" VALUE="300000000"/>
      <PORTMAPS>
        <PORTMAP LOGICAL="CLK_N" PHYSICAL="sys_clk_ddr4_clk_n"/>
        <PORTMAP LOGICAL="CLK_P" PHYSICAL="sys_clk_ddr4_clk_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="External_Interface_sysref_in" NAME="sysref_in" TYPE="TARGET">
      <PORTMAPS>
        <PORTMAP LOGICAL="diff_n" PHYSICAL="sysref_in_diff_n"/>
        <PORTMAP LOGICAL="diff_p" PHYSICAL="sysref_in_diff_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="External_Interface_vin0" NAME="vin0" TYPE="TARGET">
      <PORTMAPS>
        <PORTMAP LOGICAL="V_N" PHYSICAL="vin0_v_n"/>
        <PORTMAP LOGICAL="V_P" PHYSICAL="vin0_v_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="External_Interface_vin1" NAME="vin1" TYPE="TARGET">
      <PORTMAPS>
        <PORTMAP LOGICAL="V_N" PHYSICAL="vin1_v_n"/>
        <PORTMAP LOGICAL="V_P" PHYSICAL="vin1_v_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout00" NAME="vout0" TYPE="INITIATOR">
      <PORTMAPS>
        <PORTMAP LOGICAL="V_N" PHYSICAL="vout0_v_n"/>
        <PORTMAP LOGICAL="V_P" PHYSICAL="vout0_v_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout01" NAME="vout1" TYPE="INITIATOR">
      <PORTMAPS>
        <PORTMAP LOGICAL="V_N" PHYSICAL="vout1_v_n"/>
        <PORTMAP LOGICAL="V_P" PHYSICAL="vout1_v_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout02" NAME="vout2" TYPE="INITIATOR">
      <PORTMAPS>
        <PORTMAP LOGICAL="V_N" PHYSICAL="vout2_v_n"/>
        <PORTMAP LOGICAL="V_P" PHYSICAL="vout2_v_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout03" NAME="vout3" TYPE="INITIATOR">
      <PORTMAPS>
        <PORTMAP LOGICAL="V_N" PHYSICAL="vout3_v_n"/>
        <PORTMAP LOGICAL="V_P" PHYSICAL="vout3_v_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout10" NAME="vout4" TYPE="INITIATOR">
      <PORTMAPS>
        <PORTMAP LOGICAL="V_N" PHYSICAL="vout4_v_n"/>
        <PORTMAP LOGICAL="V_P" PHYSICAL="vout4_v_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout11" NAME="vout5" TYPE="INITIATOR">
      <PORTMAPS>
        <PORTMAP LOGICAL="V_N" PHYSICAL="vout5_v_n"/>
        <PORTMAP LOGICAL="V_P" PHYSICAL="vout5_v_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout12" NAME="vout6" TYPE="INITIATOR">
      <PORTMAPS>
        <PORTMAP LOGICAL="V_N" PHYSICAL="vout6_v_n"/>
        <PORTMAP LOGICAL="V_P" PHYSICAL="vout6_v_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
    <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout13" NAME="vout7" TYPE="INITIATOR">
      <PORTMAPS>
        <PORTMAP LOGICAL="V_N" PHYSICAL="vout7_v_n"/>
        <PORTMAP LOGICAL="V_P" PHYSICAL="vout7_v_p"/>
      </PORTMAPS>
    </BUSINTERFACE>
  </EXTERNALINTERFACES>

  <MODULES>
    <MODULE COREREVISION="25" FULLNAME="/attn_spi" HWVERSION="3.2" INSTANCE="attn_spi" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_quad_spi" VLNV="xilinx.com:ip:axi_quad_spi:3.2">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_quad_spi;v=v3_2;d=pg153-axi-quad-spi.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="AXI_LITE" NAME="Reg" RANGE="4096" USAGE="register">
          <REGISTERS>
            <REGISTER NAME="XIP_Config_Reg">
              <PROPERTY NAME="DESCRIPTION" VALUE="XIP Configuration Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x60"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="CPHA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPHA&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="XIP_Status_Reg">
              <PROPERTY NAME="DESCRIPTION" VALUE="XIP Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x64"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x1"/>
              <FIELDS>
                <FIELD NAME="RX_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receiver Empty.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="RX_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receiver Full.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Master_MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Master mode fault. This bit is set to 1 if the spisel line is deasserted.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA Error.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="AXI_Transaction_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="AXI Transaction Error.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SRR">
              <PROPERTY NAME="DESCRIPTION" VALUE="Software Reset Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x40"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="The only allowed operation on this register is a write of 0x0000000a, which resets the AXI Quad SPI core.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPICR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x60"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x180"/>
              <FIELDS>
                <FIELD NAME="LOOP">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Local loopback mode&#xA;Enables local loopback operation and is functional only in standard SPI master mode.&#xA;When set to:   0 - Normal operation.   1 - Loopback mode. The transmitter output is internally connected to the receiver input. The receiver and transmitter operate normally, except that received data (from remote slave) is ignored.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SPE">
                  <PROPERTY NAME="DESCRIPTION" VALUE="SPI system enable&#xA;When set to:&#xA;  0 - SPI system disabled. Both master and slave outputs are in 3-state and slave inputs are ignored.&#xA;  1 - SPI system enabled. Master outputs active (for example, IO0 (MOSI) and SCK in idle state) and slave outputs become active if SS becomes asserted. The master starts transferring when transmit data is available.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Master">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Master (SPI master mode)&#xA;Setting this bit configures the SPI device as a master or a slave.&#xA;When set to:&#xA;  0 - Slave configuration.&#xA;  1 - Master configuration.&#xA;In dual/quad SPI mode only the master mode of the core is allowed.&#xA;Standard Slave mode is not supported for SCK ratio = 2&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Clock polarity&#xA;Setting this bit defines clock polarity.&#xA;When set to:&#xA;  0 - Active-High clock; SCK idles Low.&#xA;  1 - Active-Low clock; SCK idles High.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPHA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Clock phase&#xA;Setting this bit selects one of two fundamentally different transfer formats.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_FIFO_Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit FIFO reset&#xA;When written to 1, this bit forces a reset of the transmit FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0.&#xA;When set to:   0 - Transmit FIFO normal operation.   1 - Reset transmit FIFO pointer&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="RX_FIFO_Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive FIFO reset&#xA;When written to 1, this bit forces a reset of the receive FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0.&#xA;When set to:   0 - Receive FIFO normal operation.   1 - Reset receive FIFO pointer.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Manual_Slave_Select_Assertion_Enable">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Manual slave select assertion enable&#xA;This bit forces the data in the slave select register to be asserted on the slave select output anytime the device is configured as a master and the device is enabled (SPE asserted).&#xA;This bit has no effect on slave operation.&#xA;When set to:   0 - Slave select output asserted by master core logic.   1 - Slave select output follows data in slave select register. The manual slave assertion mode is supported in standard SPI mode only.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Master_Transaction_Inhibit">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Master transaction inhibit&#xA;This bit inhibits master transactions.&#xA;This bit has no effect on slave operation.&#xA;When set to:   0 - Master transactions enabled.   1 - Master transactions disabled. This bit immediately inhibits the transaction. Setting this bit while transfer is in progress would result in unpredictable outcome&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="LSB_First">
                  <PROPERTY NAME="DESCRIPTION" VALUE="LSB first&#xA;This bit selects LSB first data transfer format.&#xA;The default transfer format is MSB first.&#xA;When set to:&#xA;  0 - MSB first transfer format.&#xA;  1 - LSB first transfer format.&#xA;In Dual/Quad SPI mode, only the MSB first mode of the core is allowed.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPISR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x64"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0A5"/>
              <FIELDS>
                <FIELD NAME="RX_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive Empty.&#xA;When a receive FIFO exists, this bit is set High when the receive FIFO is empty. The occupancy of the FIFO is decremented with each FIFO read operation.&#xA;Note: When FIFOs do not exist, this bit is set High when the receive register has been read (this option is available only in standard SPI mode). This bit is cleared at the end of a successful SPI transfer. For dual/quad SPI mode, the FIFO is always present in the core.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="RX_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive full.&#xA;When a receive FIFO exists, this bit is set High when the receive FIFO is full. The occupancy of the FIFO is incremented with the completion of each SPI transaction.&#xA;Note: When FIFOs do not exist, this bit is set High when an SPI transfer has completed (this option is available only in standard SPI mode). Rx_Empty and Rx_Full are complements in this case&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit empty.&#xA;When a transmit FIFO exists, this bit is set to High when the transmit FIFO is empty. This bit goes High as soon as the TX FIFO becomes empty. While this bit is High, the last byte of the data that is to be transmitted would still be in the pipeline.&#xA;The occupancy of the FIFO is decremented with the completion of each SPI transfer.&#xA;Note: When FIFOs do not exist, this bit is set with the completion of an SPI transfer (this option is available only in standard SPI mode). Either with or without FIFOs, this bit is cleared on an AXI write to the FIFO or transmit register. For Dual/Quad SPI mode, the FIFO is always present in the core.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit full.&#xA;When a transmit FIFO exists, this bit is set High when the transmit FIFO is full.&#xA;Note: When FIFOs do not exist, this bit is set High when an AXI write to the transmit register has been made (this option is available only in standard SPI mode). This bit is cleared when the SPI transfer is completed&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Mode-fault error flag.&#xA;This flag is set if the SS signal goes active while the SPI device is configured as a master. MODF is automatically cleared by reading the SPISR. &#xA;A Low-to-High MODF transition generates a single-cycle strobe interrupt.   0 - No error.   1 - Error condition detected&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Mode_Select">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave_Mode_Select flag.&#xA;This flag is asserted when the core is configured in slave mode. Slave_Mode_Select is activated as soon as the master SPI core asserts the chip select pin for the core.&#xA;1 - Default in standard mode.&#xA;0 - Asserted when core configured in slave mode and selected by external SPI master.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA_Error flag.&#xA;When set to:   0 - Default.   1 - The CPOL and CPHA are set to 01 or 10. When the SPI memory is chosen as either Winbond, Micron or Spansion, and CPOL and CPHA are configured as 01 or 10, this bit is set.&#xA;These memories support CPOL=CPHA mode in 00 or in 11 mode. CPOL_CPHA_Error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_mode_error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave mode error flag.&#xA;When set to:   1 - This bit is set when the core is configured with dual or quad SPI mode and the master is set to 0 in the control register (SPICR).   0 - Master mode is set in the control register (SPICR). Note: Quad SPI mode, only the master mode of the core is allowed. Slave mode error flag is only applicable when the core is configured either in dual or qu ad mode in legacy or enhanced AXI4 mode interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MSB_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="MSB error flag.&#xA;When set to:   0 - Default.   1 - This bit is set when the core is configured to transfer the SPI transactions in either dual or quad SPI mode and LSB first bit is set in the control register (SPICR). Note: In dual/quad SPI mode, only the MSB first mode of the core is allowed. MSB error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Loopback_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Loopback error flag.&#xA;When set to:   0 - Default. The loopback bit in the control register is at default state.   1 - When the SPI command, address, and data bits are set to be transferred in other than standard SPI protocol mode and this bit is set in control register (SPICR). Note: Loopback is only allowed when the core is configured in standard mode. Other modes setting of the bit causes an error and the interrupt bit is set in legacy or enhanced mode AXI4 interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Command_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Command error flag.&#xA;When set to:   0 - Default.   1 - When the core is configured in dual/quad SPI mode and the first entry in the SPI DTR FIFO (after reset) do not match with the supported command list for the particular memory, this bit is set. Note: Command error is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_SSR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Slave Select Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x70"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0xFFFF"/>
              <FIELDS>
                <FIELD NAME="Selected_Slave">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Active-Low, one-hot encoded slave select&#xA;The slaves are numbered right to left starting at zero with the LSB. The slave numbers correspond to the indexes of signal SS&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="3"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_TXFIFO_OR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Transmit FIFO Occupancy Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x74"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Occupancy_Value">
                  <PROPERTY NAME="DESCRIPTION" VALUE="The binary value plus 1 yields the occupancy.&#xA;Bit width is log(FIFO Depth). &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_RXFIFO_OR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Receive FIFO Occupancy Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x78"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Occupancy_Value">
                  <PROPERTY NAME="DESCRIPTION" VALUE="The binary value plus 1 yields the occupancy. &#xA;Bit width is log(FIFO Depth). &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="DGIER">
              <PROPERTY NAME="DESCRIPTION" VALUE="Device Global Interrupt Enable Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="GIE">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Global Interrupt Enable.&#xA;Allows passing all individually enabled interrupts to the interrupt controller.&#xA;When set to:   0 - Disabled.   1 - Enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="31"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="31"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_DTR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Data Transmit Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x68"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="TX_Data">
                  <PROPERTY NAME="DESCRIPTION" VALUE="SPI Transmit Data.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_DRR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Data Receive Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x6C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="RX_Data">
                  <PROPERTY NAME="DESCRIPTION" VALUE="SPI Receive Data&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="16"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IPISR">
              <PROPERTY NAME="DESCRIPTION" VALUE="IP Interrupt Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x20"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Mode-fault error.&#xA;This interrupt is generated if the SS signal goes active while the SPI device is configured as a master. This bit is set immediately on SS going active.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave mode-fault error.&#xA;This interrupt is generated if the SS signal goes active while the SPI device is configured as a slave, but is not enabled.&#xA;This bit is set immediately on SS going active and continually set if SS is active and the device is not enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit register/FIFO empty.&#xA;It is set when the last byte of data has been transferred out to the external flash memory.&#xA;In the context of the M68HC11 reference manual, when configured without FIFOs, this interrupt is equivalent in information content to the complement of the SPI transfer complete flag (SPIF ) interrupt bit.&#xA;In master mode if this bit is set to 1, no more SPI transfers are permitted&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Underrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit register/FIFO underrun.&#xA;This bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register when data is requested from an empty transmit register/FIFO by the SPI core logic to perform a SPI transfer.&#xA;This can occur only when the SPI device is configured as a slave in standard SPI configuration and is enabled by the SPE bit as set. All zeros are loaded in the shift register and transmitted by the slave in an under-run condition&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data receive register/FIFO full.&#xA;Without FIFOs, this bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register (An element can be a byte, half-word, or word depending on the value of Transfer Width).&#xA;With FIFOs, this bit is set at the end of the SPI element transfer, when the receive FIFO has been completely filled by a one-clock period strobe to the interrupt register.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Overrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data receive register/FIFO overrun.&#xA;This bit is set by a one-clock period strobe to the interrupt register when an attempt to write data to a full receive register or FIFO is made by the SPI core logic to complete a SPI transfer.&#xA;This can occur when the SPI device is in either master or slave mode (in standard SPI mode) or if the IP is configured in SPI master mode (dual or quad SPI mode).&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TXFIFO_Half_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit FIFO half empty.&#xA;In standard SPI configuration, IPISR Bit[6] is the transmit FIFO half-empty interrupt. &#xA;In dual or quad SPI configuration, based on the FIFO depth, this bit is set at half-empty condition.&#xA;Note: This interrupt exists only if the AXI Quad SPI core is configured with FIFOs (In standard, dual or quad SPI mode).&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Select_Mode">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave select mode.&#xA;The assertion of this bit is applicable only when the core is configured in slave mode in standard SPI configuration. &#xA;This bit is set when the other SPI master core selects the core by asserting the slave select line. This bit is set by a one-clock period strobe to the interrupt register.&#xA;Note: This bit is applicable only in standard SPI slave mode&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Not_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DRR not empty.&#xA;The assertion of this bit is applicable only in the case where FIFO Depth is 16 or 256 and the core is configured in slave mode and standard SPI mode. This bit is set when the DRR FIFO receives the first data value during the SPI transaction.&#xA;This bit is set by a one-clock period strobe to the interrupt register when the core receives the first data beat.&#xA;Note: The assertion of this bit is applicable only when the FIFO Depth parameter is 16 or 256 and the core is configured in slave mode in standard SPI mode. When FIFO Depth is set to 0, this bit always returns 0. This bit has no significance in dual/quad mode&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA error.&#xA;This flag is asserted when:&#xA;  The core is configured in either dual or quad SPI mode and&#xA;  The CPOL - CPHA control register bits are set to 01 or 10.&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Mode_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="I/O mode instruction error.&#xA;This flag is asserted when:&#xA;  The core is configured in either dual or quad SPI mode and&#xA;  The core is configured in master = 0 in control register (SPICR(2)).&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MSB_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="MSB error.&#xA;This flag is asserted when:&#xA;  The core is configured in either dual or quad SPI mode and&#xA;  The LSB First bit in the control register (SPICR) is set to 1.&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Loopback_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Loopback error.&#xA;This flag is asserted when:&#xA;  The core is configured in dual or quad SPI transfer mode and&#xA;  The LOOP bit is set in control register (SPICR(0)).&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Command_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Command error.&#xA;This flag is asserted when:   The core is configured in dual/quad SPI mode and   The first entry in the SPI DTR FIFO (after reset) does not match with the supported command list for particular memory. When the SPI command in DTR FIFO does not match with the internal supported command list, the core completes the SPI transactions in standard SPI format. This bit is set to show this behavior of the core.&#xA;In standard SPI mode this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IPIER">
              <PROPERTY NAME="DESCRIPTION" VALUE="IP Interrupt Enable Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x28"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Mode-fault error flag.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave mode-fault error flag.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit register/FIFO empty.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Underrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit FIFO underrun.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data receive register/FIFO full.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Overrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive FIFO overrun.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_FIFO_Half_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit FIFO half empty.   0 - Disabled.   1 - Enabled. Note: This bit is meaningful only if the AXI Quad SPI core is configured with FIFOs.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Select_Mode">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave_Select_Mode.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in slave mode by selecting the active-Low status on spisel.&#xA;In master mode, setting this bit has no effect.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Not_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DRR_Not_Empty.   0 - Disabled.   1 - Enabled. Note: The setting of this bit is applicable only when FIFO Depth is set to 1 and the core is configured in slave mode of standard SPI mode.&#xA;If FIFO Depth is set to 0, the setting of this bit has no effect. This is allowed only in standard SPI configuration. It means this bit is not set in the IPIER register. Therefore, this bit should only be used when FIFO Depth is set to 1 and when the core is configured in slave mode.&#xA;This bit has no significance in dual or quad mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Mode_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="I/O mode instruction error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MSB_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="MSB_Error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Loopback_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Loopback Error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Command_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Command_Error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
          </REGISTERS>
        </ADDRESSBLOCK>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="Async_Clk" VALUE="0"/>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_SELECT_XPM" VALUE="0"/>
        <PARAMETER NAME="C_SUB_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_INSTANCE" VALUE="axi_quad_spi_inst"/>
        <PARAMETER NAME="C_SPI_MEM_ADDR_BITS" VALUE="24"/>
        <PARAMETER NAME="C_TYPE_OF_AXI4_INTERFACE" VALUE="0"/>
        <PARAMETER NAME="C_XIP_MODE" VALUE="0"/>
        <PARAMETER NAME="C_XIP_PERF_MODE" VALUE="1"/>
        <PARAMETER NAME="C_BYTE_LEVEL_INTERRUPT_EN" VALUE="0"/>
        <PARAMETER NAME="C_UC_FAMILY" VALUE="1"/>
        <PARAMETER NAME="C_FIFO_DEPTH" VALUE="16"/>
        <PARAMETER NAME="C_SCK_RATIO" VALUE="16"/>
        <PARAMETER NAME="C_DUAL_QUAD_MODE" VALUE="0"/>
        <PARAMETER NAME="C_NUM_SS_BITS" VALUE="3"/>
        <PARAMETER NAME="C_NUM_TRANSFER_BITS" VALUE="16"/>
        <PARAMETER NAME="C_NEW_SEQ_EN" VALUE="1"/>
        <PARAMETER NAME="C_SPI_MODE" VALUE="0"/>
        <PARAMETER NAME="C_USE_STARTUP" VALUE="0"/>
        <PARAMETER NAME="C_USE_STARTUP_EXT" VALUE="0"/>
        <PARAMETER NAME="C_SPI_MEMORY" VALUE="1"/>
        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="7"/>
        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXI4_ADDR_WIDTH" VALUE="24"/>
        <PARAMETER NAME="C_S_AXI4_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXI4_ID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_SHARED_STARTUP" VALUE="0"/>
        <PARAMETER NAME="C_LSB_STUP" VALUE="0"/>
        <PARAMETER NAME="C_USE_STARTUP_INT" VALUE="0"/>
        <PARAMETER NAME="UC_FAMILY" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_attn_spi_0"/>
        <PARAMETER NAME="Master_mode" VALUE="1"/>
        <PARAMETER NAME="FIFO_INCLUDED" VALUE="1"/>
        <PARAMETER NAME="Multiples16" VALUE="1"/>
        <PARAMETER NAME="C_SCK_RATIO1" VALUE="1"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="QSPI_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0258000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0258FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="ext_spi_clk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="attn_spi_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="attn_spi_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="attn_spi_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="attn_spi_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="attn_spi_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="attn_spi_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="attn_spi_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="attn_spi_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="attn_spi_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="attn_spi_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="io0_i" SIGIS="undef"/>
        <PORT DIR="O" NAME="io0_o" SIGIS="undef" SIGNAME="attn_spi_io0_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="ATTN_SI"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="io0_t" SIGIS="undef"/>
        <PORT DIR="I" NAME="io1_i" SIGIS="undef"/>
        <PORT DIR="O" NAME="io1_o" SIGIS="undef"/>
        <PORT DIR="O" NAME="io1_t" SIGIS="undef"/>
        <PORT DIR="I" NAME="sck_i" SIGIS="undef"/>
        <PORT DIR="O" NAME="sck_o" SIGIS="undef" SIGNAME="attn_spi_sck_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="ATTN_CLK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="sck_t" SIGIS="undef"/>
        <PORT DIR="I" LEFT="2" NAME="ss_i" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="ss_o" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_ss_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="ATTN_LE"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ss_t" SIGIS="undef"/>
        <PORT DIR="O" NAME="ip2intc_irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="SPI_0" TYPE="INITIATOR" VLNV="xilinx.com:interface:spi:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="IO0_I" PHYSICAL="io0_i"/>
            <PORTMAP LOGICAL="IO0_O" PHYSICAL="io0_o"/>
            <PORTMAP LOGICAL="IO0_T" PHYSICAL="io0_t"/>
            <PORTMAP LOGICAL="IO1_I" PHYSICAL="io1_i"/>
            <PORTMAP LOGICAL="IO1_O" PHYSICAL="io1_o"/>
            <PORTMAP LOGICAL="IO1_T" PHYSICAL="io1_t"/>
            <PORTMAP LOGICAL="SCK_I" PHYSICAL="sck_i"/>
            <PORTMAP LOGICAL="SCK_O" PHYSICAL="sck_o"/>
            <PORTMAP LOGICAL="SCK_T" PHYSICAL="sck_t"/>
            <PORTMAP LOGICAL="SS_I" PHYSICAL="ss_i"/>
            <PORTMAP LOGICAL="SS_O" PHYSICAL="ss_o"/>
            <PORTMAP LOGICAL="SS_T" PHYSICAL="ss_t"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M27_AXI" DATAWIDTH="32" NAME="AXI_LITE" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="7"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="27" FULLNAME="/axi_dma_avg" HWVERSION="7.1" INSTANCE="axi_dma_avg" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_dma;v=v7_1;d=pg021_axi_dma.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI_LITE" NAME="Reg" RANGE="4096" USAGE="register">
          <REGISTERS>
            <REGISTER NAME="MM2S_DMACR">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10002"/>
              <FIELDS>
                <FIELD NAME="RS">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Run / Stop control for controlling running and stopping of the DMA channel.&#xA;  0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. &#xA;  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.&#xA;  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.&#xA;  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.&#xA;  1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.&#xA;AXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Normal operation.   1 - Reset in progress.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Keyhole">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.&#xA;This bit is non functional when the multichannel feature is enabled or in Direct Register mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Cyclic_BD_Enable">
                  <PROPERTY NAME="DESCRIPTION" VALUE="When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.&#xA;This bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.&#xA;This bit is non functional when DMA operates in multichannel mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set.   0 - IOC Interrupt disabled      1 - IOC Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out.      0 - Delay Interrupt disabled   1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error Interrupt Enable.&#xA;  0 - Error Interrupt disabled&#xA;  1 - Error Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThreshold">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.   Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.   Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelay">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.&#xA;Note: Setting this value to zero disables the delay timer interrupt.&#xA;Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_DMASR">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x04"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10000"/>
              <FIELDS>
                <FIELD NAME="Halted">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Idle">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Idle. Indicates the state of AXI DMA operations.&#xA;For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.&#xA;For Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete.      1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused.  Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIncld">
                  <PROPERTY NAME="DESCRIPTION" VALUE="1 - Scatter Gather Enabled&#xA;0 - Scatter Gather not enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMAIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors        1 - DMA Internal Error detected. DMA Engine halts&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMASlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected. DMA Engine halts&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMADecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Decode Errors.      1 - DMA Decode Error detected. DMA Engine halts.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGSlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGDecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected.  Writing a 1 to this bit will clear it.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.&#xA;Writing a 1 to this bit will clear it.   &#xA;0 - No error Interrupt.   &#xA;1 - Error interrupt detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThresholdSts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold Status. Indicates current interrupt threshold value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelaySts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Status. Indicates current interrupt delay time value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_CURDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_CURDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_TAILDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_TAILDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x14"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_SA">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S Source Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x18"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Source_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.&#xA;Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_SA_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S Source Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Source_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.&#xA;Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_LENGTH">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Transfer Length Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x28"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Length">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SG_CTL">
              <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather User and Cache Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x03"/>
              <FIELDS>
                <FIELD NAME="SG_CACHE">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather Cache Control. Values written in this register reflect on the m_axi_sg_arcache and m_axi_sg_awcache signals of the M_AXI_SG interface.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
                </FIELD>
                <FIELD NAME="SG_USER">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather User Control. Values written in this register reflect on the m_axi_sg_aruser and m_axi_sg_awuser signals of the M_AXI_SG interface.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DMACR">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x30"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10002"/>
              <FIELDS>
                <FIELD NAME="RS">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Run / Stop control for controlling running and stopping of the DMA channel.&#xA;  0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. &#xA;  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.&#xA;  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.&#xA;  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.&#xA;  1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.&#xA;AXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Reset not in progress. Normal operation.      1 - Reset in progress&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Keyhole">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.&#xA;This bit is non functional when DMA is used in multichannel mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Cyclic_BD_Enable">
                  <PROPERTY NAME="DESCRIPTION" VALUE="When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.&#xA;This bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set.      0 - IOC Interrupt disabled      1 - IOC Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Delay Interrupt disabled      1 - Delay Interrupt enabled  Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Error Interrupt disabled      1 - Error Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThreshold">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.&#xA;Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelay">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.&#xA;Note: Setting this value to zero disables the delay timer interrupt.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DMASR">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x34"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10000"/>
              <FIELDS>
                <FIELD NAME="Halted">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 &#xA;Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Idle">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Idle. Indicates the state of AXI DMA operations.&#xA;For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.&#xA;For Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle.      1 - Idle.   Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIncld">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMAIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.&#xA;This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors      1 - DMA Internal Error detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMASlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMADecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.     0 - No DMA Decode Errors.   1 - DMA Decode Error detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected.  Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGSlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGDecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.&#xA;Writing a 1 to this bit will clear it.      0 - No error Interrupt.      1 - Error interrupt detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThresholdSts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold Status. Indicates current interrupt threshold value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelaySts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Status. Indicates current interrupt delay time value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_CURDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x38"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). &#xA;Buffer Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and so forth. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_CURDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x3C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_TAILDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x40"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel DMACR.RS bit is set to 0 (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. &#xA;Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_TAILDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x44"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DA">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Destination Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x48"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Destination_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.&#xA;Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DA_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM Destination Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x4C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Destination_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.&#xA;Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_LENGTH">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Transfer Length Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x58"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Length">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.&#xA;At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.&#xA;Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
          </REGISTERS>
        </ADDRESSBLOCK>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="C_S_AXI_LITE_ADDR_WIDTH" VALUE="10"/>
        <PARAMETER NAME="C_S_AXI_LITE_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_DLYTMR_RESOLUTION" VALUE="125"/>
        <PARAMETER NAME="C_PRMRY_IS_ACLK_ASYNC" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_MULTI_CHANNEL" VALUE="0"/>
        <PARAMETER NAME="C_NUM_MM2S_CHANNELS" VALUE="1"/>
        <PARAMETER NAME="C_NUM_S2MM_CHANNELS" VALUE="1"/>
        <PARAMETER NAME="C_INCLUDE_SG" VALUE="0"/>
        <PARAMETER NAME="C_SG_INCLUDE_STSCNTRL_STRM" VALUE="0"/>
        <PARAMETER NAME="C_SG_USE_STSAPP_LENGTH" VALUE="0"/>
        <PARAMETER NAME="C_SG_LENGTH_WIDTH" VALUE="26"/>
        <PARAMETER NAME="C_M_AXI_SG_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_SG_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXIS_S2MM_STS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_MICRO_DMA" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_MM2S" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_MM2S_SF" VALUE="1"/>
        <PARAMETER NAME="C_MM2S_BURST_SIZE" VALUE="16"/>
        <PARAMETER NAME="C_M_AXI_MM2S_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_MM2S_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_MM2S_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_INCLUDE_MM2S_DRE" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_S2MM" VALUE="1"/>
        <PARAMETER NAME="C_INCLUDE_S2MM_SF" VALUE="1"/>
        <PARAMETER NAME="C_S2MM_BURST_SIZE" VALUE="16"/>
        <PARAMETER NAME="C_M_AXI_S2MM_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_S2MM_DATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="C_S_AXIS_S2MM_TDATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="C_INCLUDE_S2MM_DRE" VALUE="0"/>
        <PARAMETER NAME="C_INCREASE_THROUGHPUT" VALUE="0"/>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axi_dma_avg_0"/>
        <PARAMETER NAME="c_include_sg" VALUE="0"/>
        <PARAMETER NAME="c_enable_multi_channel" VALUE="0"/>
        <PARAMETER NAME="c_num_mm2s_channels" VALUE="1"/>
        <PARAMETER NAME="c_num_s2mm_channels" VALUE="1"/>
        <PARAMETER NAME="c_sg_length_width" VALUE="26"/>
        <PARAMETER NAME="c_dlytmr_resolution" VALUE="125"/>
        <PARAMETER NAME="c_prmry_is_aclk_async" VALUE="0"/>
        <PARAMETER NAME="c_sg_include_stscntrl_strm" VALUE="0"/>
        <PARAMETER NAME="c_micro_dma" VALUE="0"/>
        <PARAMETER NAME="c_include_mm2s" VALUE="0"/>
        <PARAMETER NAME="c_m_axi_mm2s_data_width" VALUE="32"/>
        <PARAMETER NAME="c_m_axis_mm2s_tdata_width" VALUE="32"/>
        <PARAMETER NAME="c_include_mm2s_dre" VALUE="0"/>
        <PARAMETER NAME="c_include_mm2s_sf" VALUE="1"/>
        <PARAMETER NAME="c_mm2s_burst_size" VALUE="16"/>
        <PARAMETER NAME="c_include_s2mm" VALUE="1"/>
        <PARAMETER NAME="c_sg_use_stsapp_length" VALUE="0"/>
        <PARAMETER NAME="c_m_axi_s2mm_data_width" VALUE="64"/>
        <PARAMETER NAME="c_s_axis_s2mm_tdata_width" VALUE="64"/>
        <PARAMETER NAME="c_include_s2mm_dre" VALUE="0"/>
        <PARAMETER NAME="c_include_s2mm_sf" VALUE="1"/>
        <PARAMETER NAME="c_s2mm_burst_size" VALUE="16"/>
        <PARAMETER NAME="c_addr_width" VALUE="32"/>
        <PARAMETER NAME="c_single_interface" VALUE="0"/>
        <PARAMETER NAME="c_increase_throughput" VALUE="0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0240000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0240FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_lite_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="m_axi_s2mm_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="axi_resetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_awvalid" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_awready" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="9" NAME="s_axi_lite_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_wvalid" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_wready" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_bvalid" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_bready" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_arvalid" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_arready" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="9" NAME="s_axi_lite_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_rvalid" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_rready" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axi_s2mm_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="m_axi_s2mm_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="m_axi_s2mm_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m_axi_s2mm_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_awvalid" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_s2mm_awready" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="63" NAME="m_axi_s2mm_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="m_axi_s2mm_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_wlast" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_wvalid" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_s2mm_wready" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="m_axi_s2mm_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_s2mm_bvalid" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_bready" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S03_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s2mm_prmry_reset_out_n" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="I" LEFT="63" NAME="s_axis_s2mm_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axis_s2mm_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="s_axis_s2mm_tkeep" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="s_axis_s2mm_tvalid" SIGIS="undef" SIGNAME="axi_dma_avg_s_axis_s2mm_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_s2mm_tready" SIGIS="undef" SIGNAME="axi_dma_avg_s_axis_s2mm_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_s2mm_tlast" SIGIS="undef" SIGNAME="axi_dma_avg_s_axis_s2mm_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="m_axis_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s2mm_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_dma_avg_s2mm_introut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconcat_0" PORT="In3"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M19_AXI" DATAWIDTH="32" NAME="S_AXI_LITE" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="10"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_lite_araddr"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_lite_arready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_lite_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_lite_awaddr"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_lite_awready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_lite_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_lite_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_lite_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_lite_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_lite_rdata"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_lite_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_lite_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_lite_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_lite_wdata"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_lite_wready"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_lite_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_dma_avg_M_AXI_S2MM" DATAWIDTH="64" NAME="M_AXI_S2MM" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="64"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="WRITE_ONLY"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="m_axi_s2mm_awaddr"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="m_axi_s2mm_awburst"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="m_axi_s2mm_awcache"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="m_axi_s2mm_awlen"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="m_axi_s2mm_awprot"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="m_axi_s2mm_awready"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="m_axi_s2mm_awsize"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="m_axi_s2mm_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="m_axi_s2mm_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="m_axi_s2mm_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="m_axi_s2mm_bvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="m_axi_s2mm_wdata"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="m_axi_s2mm_wlast"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="m_axi_s2mm_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="m_axi_s2mm_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="m_axi_s2mm_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_avg_M00_AXIS" NAME="S_AXIS_S2MM" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_s2mm_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="s_axis_s2mm_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="s_axis_s2mm_tlast"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_s2mm_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_s2mm_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE ADDRESSBLOCK="HPC0_DDR_LOW" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7FFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_S2MM" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HPC0_FPD"/>
        <MEMRANGE ADDRESSBLOCK="HPC0_QSPI" BASENAME="C_BASEADDR" BASEVALUE="0xC0000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xDFFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_S2MM" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HPC0_FPD"/>
      </MEMORYMAP>
      <PERIPHERALS>
        <PERIPHERAL INSTANCE="zynq_ultra_ps_e_0"/>
      </PERIPHERALS>
    </MODULE>
    <MODULE COREREVISION="27" FULLNAME="/axi_dma_buf" HWVERSION="7.1" INSTANCE="axi_dma_buf" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_dma;v=v7_1;d=pg021_axi_dma.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI_LITE" NAME="Reg" RANGE="4096" USAGE="register">
          <REGISTERS>
            <REGISTER NAME="MM2S_DMACR">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10002"/>
              <FIELDS>
                <FIELD NAME="RS">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Run / Stop control for controlling running and stopping of the DMA channel.&#xA;  0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. &#xA;  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.&#xA;  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.&#xA;  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.&#xA;  1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.&#xA;AXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Normal operation.   1 - Reset in progress.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Keyhole">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.&#xA;This bit is non functional when the multichannel feature is enabled or in Direct Register mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Cyclic_BD_Enable">
                  <PROPERTY NAME="DESCRIPTION" VALUE="When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.&#xA;This bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.&#xA;This bit is non functional when DMA operates in multichannel mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set.   0 - IOC Interrupt disabled      1 - IOC Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out.      0 - Delay Interrupt disabled   1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error Interrupt Enable.&#xA;  0 - Error Interrupt disabled&#xA;  1 - Error Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThreshold">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.   Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.   Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelay">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.&#xA;Note: Setting this value to zero disables the delay timer interrupt.&#xA;Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_DMASR">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x04"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10000"/>
              <FIELDS>
                <FIELD NAME="Halted">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Idle">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Idle. Indicates the state of AXI DMA operations.&#xA;For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.&#xA;For Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete.      1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused.  Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIncld">
                  <PROPERTY NAME="DESCRIPTION" VALUE="1 - Scatter Gather Enabled&#xA;0 - Scatter Gather not enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMAIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors        1 - DMA Internal Error detected. DMA Engine halts&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMASlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected. DMA Engine halts&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMADecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Decode Errors.      1 - DMA Decode Error detected. DMA Engine halts.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGSlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGDecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected.  Writing a 1 to this bit will clear it.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.&#xA;Writing a 1 to this bit will clear it.   &#xA;0 - No error Interrupt.   &#xA;1 - Error interrupt detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThresholdSts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold Status. Indicates current interrupt threshold value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelaySts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Status. Indicates current interrupt delay time value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_CURDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_CURDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_TAILDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_TAILDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x14"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_SA">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S Source Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x18"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Source_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.&#xA;Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_SA_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S Source Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Source_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.&#xA;Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_LENGTH">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Transfer Length Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x28"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Length">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SG_CTL">
              <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather User and Cache Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x03"/>
              <FIELDS>
                <FIELD NAME="SG_CACHE">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather Cache Control. Values written in this register reflect on the m_axi_sg_arcache and m_axi_sg_awcache signals of the M_AXI_SG interface.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
                </FIELD>
                <FIELD NAME="SG_USER">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather User Control. Values written in this register reflect on the m_axi_sg_aruser and m_axi_sg_awuser signals of the M_AXI_SG interface.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DMACR">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x30"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10002"/>
              <FIELDS>
                <FIELD NAME="RS">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Run / Stop control for controlling running and stopping of the DMA channel.&#xA;  0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. &#xA;  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.&#xA;  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.&#xA;  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.&#xA;  1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.&#xA;AXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Reset not in progress. Normal operation.      1 - Reset in progress&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Keyhole">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.&#xA;This bit is non functional when DMA is used in multichannel mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Cyclic_BD_Enable">
                  <PROPERTY NAME="DESCRIPTION" VALUE="When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.&#xA;This bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set.      0 - IOC Interrupt disabled      1 - IOC Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Delay Interrupt disabled      1 - Delay Interrupt enabled  Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Error Interrupt disabled      1 - Error Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThreshold">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.&#xA;Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelay">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.&#xA;Note: Setting this value to zero disables the delay timer interrupt.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DMASR">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x34"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10000"/>
              <FIELDS>
                <FIELD NAME="Halted">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 &#xA;Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Idle">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Idle. Indicates the state of AXI DMA operations.&#xA;For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.&#xA;For Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle.      1 - Idle.   Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIncld">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMAIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.&#xA;This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors      1 - DMA Internal Error detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMASlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMADecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.     0 - No DMA Decode Errors.   1 - DMA Decode Error detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected.  Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGSlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGDecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.&#xA;Writing a 1 to this bit will clear it.      0 - No error Interrupt.      1 - Error interrupt detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThresholdSts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold Status. Indicates current interrupt threshold value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelaySts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Status. Indicates current interrupt delay time value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_CURDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x38"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). &#xA;Buffer Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and so forth. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_CURDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x3C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_TAILDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x40"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel DMACR.RS bit is set to 0 (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. &#xA;Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_TAILDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x44"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DA">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Destination Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x48"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Destination_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.&#xA;Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DA_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM Destination Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x4C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Destination_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.&#xA;Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_LENGTH">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Transfer Length Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x58"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Length">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.&#xA;At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.&#xA;Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
          </REGISTERS>
        </ADDRESSBLOCK>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="C_S_AXI_LITE_ADDR_WIDTH" VALUE="10"/>
        <PARAMETER NAME="C_S_AXI_LITE_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_DLYTMR_RESOLUTION" VALUE="125"/>
        <PARAMETER NAME="C_PRMRY_IS_ACLK_ASYNC" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_MULTI_CHANNEL" VALUE="0"/>
        <PARAMETER NAME="C_NUM_MM2S_CHANNELS" VALUE="1"/>
        <PARAMETER NAME="C_NUM_S2MM_CHANNELS" VALUE="1"/>
        <PARAMETER NAME="C_INCLUDE_SG" VALUE="0"/>
        <PARAMETER NAME="C_SG_INCLUDE_STSCNTRL_STRM" VALUE="0"/>
        <PARAMETER NAME="C_SG_USE_STSAPP_LENGTH" VALUE="0"/>
        <PARAMETER NAME="C_SG_LENGTH_WIDTH" VALUE="26"/>
        <PARAMETER NAME="C_M_AXI_SG_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_SG_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXIS_S2MM_STS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_MICRO_DMA" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_MM2S" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_MM2S_SF" VALUE="1"/>
        <PARAMETER NAME="C_MM2S_BURST_SIZE" VALUE="16"/>
        <PARAMETER NAME="C_M_AXI_MM2S_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_MM2S_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_MM2S_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_INCLUDE_MM2S_DRE" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_S2MM" VALUE="1"/>
        <PARAMETER NAME="C_INCLUDE_S2MM_SF" VALUE="1"/>
        <PARAMETER NAME="C_S2MM_BURST_SIZE" VALUE="16"/>
        <PARAMETER NAME="C_M_AXI_S2MM_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_S2MM_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXIS_S2MM_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_INCLUDE_S2MM_DRE" VALUE="0"/>
        <PARAMETER NAME="C_INCREASE_THROUGHPUT" VALUE="0"/>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axi_dma_buf_0"/>
        <PARAMETER NAME="c_include_sg" VALUE="0"/>
        <PARAMETER NAME="c_enable_multi_channel" VALUE="0"/>
        <PARAMETER NAME="c_num_mm2s_channels" VALUE="1"/>
        <PARAMETER NAME="c_num_s2mm_channels" VALUE="1"/>
        <PARAMETER NAME="c_sg_length_width" VALUE="26"/>
        <PARAMETER NAME="c_dlytmr_resolution" VALUE="125"/>
        <PARAMETER NAME="c_prmry_is_aclk_async" VALUE="0"/>
        <PARAMETER NAME="c_sg_include_stscntrl_strm" VALUE="0"/>
        <PARAMETER NAME="c_micro_dma" VALUE="0"/>
        <PARAMETER NAME="c_include_mm2s" VALUE="0"/>
        <PARAMETER NAME="c_m_axi_mm2s_data_width" VALUE="32"/>
        <PARAMETER NAME="c_m_axis_mm2s_tdata_width" VALUE="32"/>
        <PARAMETER NAME="c_include_mm2s_dre" VALUE="0"/>
        <PARAMETER NAME="c_include_mm2s_sf" VALUE="1"/>
        <PARAMETER NAME="c_mm2s_burst_size" VALUE="16"/>
        <PARAMETER NAME="c_include_s2mm" VALUE="1"/>
        <PARAMETER NAME="c_sg_use_stsapp_length" VALUE="0"/>
        <PARAMETER NAME="c_m_axi_s2mm_data_width" VALUE="32"/>
        <PARAMETER NAME="c_s_axis_s2mm_tdata_width" VALUE="32"/>
        <PARAMETER NAME="c_include_s2mm_dre" VALUE="0"/>
        <PARAMETER NAME="c_include_s2mm_sf" VALUE="1"/>
        <PARAMETER NAME="c_s2mm_burst_size" VALUE="16"/>
        <PARAMETER NAME="c_addr_width" VALUE="32"/>
        <PARAMETER NAME="c_single_interface" VALUE="0"/>
        <PARAMETER NAME="c_increase_throughput" VALUE="0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0241000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0241FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_lite_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="m_axi_s2mm_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="axi_resetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_awvalid" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_awready" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="9" NAME="s_axi_lite_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_wvalid" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_wready" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_bvalid" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_bready" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_arvalid" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_arready" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="9" NAME="s_axi_lite_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_rvalid" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_rready" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axi_s2mm_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="m_axi_s2mm_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="m_axi_s2mm_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m_axi_s2mm_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_awvalid" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_s2mm_awready" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axi_s2mm_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m_axi_s2mm_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_wlast" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_wvalid" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_s2mm_wready" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="m_axi_s2mm_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_s2mm_bvalid" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_bready" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S04_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s2mm_prmry_reset_out_n" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="I" LEFT="31" NAME="s_axis_s2mm_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axis_s2mm_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axis_s2mm_tkeep" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="s_axis_s2mm_tvalid" SIGIS="undef" SIGNAME="axi_dma_buf_s_axis_s2mm_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_s2mm_tready" SIGIS="undef" SIGNAME="axi_dma_buf_s_axis_s2mm_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_s2mm_tlast" SIGIS="undef" SIGNAME="axi_dma_buf_s_axis_s2mm_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="m_axis_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s2mm_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_dma_buf_s2mm_introut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconcat_0" PORT="In4"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M20_AXI" DATAWIDTH="32" NAME="S_AXI_LITE" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="10"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_lite_araddr"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_lite_arready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_lite_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_lite_awaddr"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_lite_awready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_lite_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_lite_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_lite_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_lite_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_lite_rdata"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_lite_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_lite_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_lite_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_lite_wdata"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_lite_wready"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_lite_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_dma_buf_M_AXI_S2MM" DATAWIDTH="32" NAME="M_AXI_S2MM" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="WRITE_ONLY"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="m_axi_s2mm_awaddr"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="m_axi_s2mm_awburst"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="m_axi_s2mm_awcache"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="m_axi_s2mm_awlen"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="m_axi_s2mm_awprot"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="m_axi_s2mm_awready"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="m_axi_s2mm_awsize"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="m_axi_s2mm_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="m_axi_s2mm_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="m_axi_s2mm_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="m_axi_s2mm_bvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="m_axi_s2mm_wdata"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="m_axi_s2mm_wlast"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="m_axi_s2mm_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="m_axi_s2mm_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="m_axi_s2mm_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_buf_M00_AXIS" NAME="S_AXIS_S2MM" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_s2mm_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="s_axis_s2mm_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="s_axis_s2mm_tlast"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_s2mm_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_s2mm_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE ADDRESSBLOCK="HPC0_DDR_LOW" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7FFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_S2MM" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HPC0_FPD"/>
        <MEMRANGE ADDRESSBLOCK="HPC0_QSPI" BASENAME="C_BASEADDR" BASEVALUE="0xC0000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xDFFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_S2MM" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HPC0_FPD"/>
      </MEMORYMAP>
      <PERIPHERALS>
        <PERIPHERAL INSTANCE="zynq_ultra_ps_e_0"/>
      </PERIPHERALS>
    </MODULE>
    <MODULE COREREVISION="27" FULLNAME="/axi_dma_gen" HWVERSION="7.1" INSTANCE="axi_dma_gen" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_dma;v=v7_1;d=pg021_axi_dma.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI_LITE" NAME="Reg" RANGE="4096" USAGE="register">
          <REGISTERS>
            <REGISTER NAME="MM2S_DMACR">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10002"/>
              <FIELDS>
                <FIELD NAME="RS">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Run / Stop control for controlling running and stopping of the DMA channel.&#xA;  0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. &#xA;  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.&#xA;  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.&#xA;  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.&#xA;  1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.&#xA;AXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Normal operation.   1 - Reset in progress.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Keyhole">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.&#xA;This bit is non functional when the multichannel feature is enabled or in Direct Register mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Cyclic_BD_Enable">
                  <PROPERTY NAME="DESCRIPTION" VALUE="When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.&#xA;This bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.&#xA;This bit is non functional when DMA operates in multichannel mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set.   0 - IOC Interrupt disabled      1 - IOC Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out.      0 - Delay Interrupt disabled   1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error Interrupt Enable.&#xA;  0 - Error Interrupt disabled&#xA;  1 - Error Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThreshold">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.   Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.   Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelay">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.&#xA;Note: Setting this value to zero disables the delay timer interrupt.&#xA;Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_DMASR">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x04"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10000"/>
              <FIELDS>
                <FIELD NAME="Halted">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Idle">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Idle. Indicates the state of AXI DMA operations.&#xA;For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.&#xA;For Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete.      1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused.  Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIncld">
                  <PROPERTY NAME="DESCRIPTION" VALUE="1 - Scatter Gather Enabled&#xA;0 - Scatter Gather not enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMAIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors        1 - DMA Internal Error detected. DMA Engine halts&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMASlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected. DMA Engine halts&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMADecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Decode Errors.      1 - DMA Decode Error detected. DMA Engine halts.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGSlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGDecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected.  Writing a 1 to this bit will clear it.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.&#xA;Writing a 1 to this bit will clear it.   &#xA;0 - No error Interrupt.   &#xA;1 - Error interrupt detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThresholdSts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold Status. Indicates current interrupt threshold value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelaySts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Status. Indicates current interrupt delay time value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_CURDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_CURDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_TAILDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_TAILDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x14"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_SA">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S Source Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x18"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Source_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.&#xA;Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_SA_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S Source Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Source_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.&#xA;Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_LENGTH">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Transfer Length Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x28"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Length">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SG_CTL">
              <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather User and Cache Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x03"/>
              <FIELDS>
                <FIELD NAME="SG_CACHE">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather Cache Control. Values written in this register reflect on the m_axi_sg_arcache and m_axi_sg_awcache signals of the M_AXI_SG interface.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
                </FIELD>
                <FIELD NAME="SG_USER">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather User Control. Values written in this register reflect on the m_axi_sg_aruser and m_axi_sg_awuser signals of the M_AXI_SG interface.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DMACR">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x30"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10002"/>
              <FIELDS>
                <FIELD NAME="RS">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Run / Stop control for controlling running and stopping of the DMA channel.&#xA;  0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. &#xA;  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.&#xA;  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.&#xA;  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.&#xA;  1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.&#xA;AXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Reset not in progress. Normal operation.      1 - Reset in progress&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Keyhole">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.&#xA;This bit is non functional when DMA is used in multichannel mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Cyclic_BD_Enable">
                  <PROPERTY NAME="DESCRIPTION" VALUE="When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.&#xA;This bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set.      0 - IOC Interrupt disabled      1 - IOC Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Delay Interrupt disabled      1 - Delay Interrupt enabled  Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Error Interrupt disabled      1 - Error Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThreshold">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.&#xA;Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelay">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.&#xA;Note: Setting this value to zero disables the delay timer interrupt.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DMASR">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x34"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10000"/>
              <FIELDS>
                <FIELD NAME="Halted">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 &#xA;Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Idle">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Idle. Indicates the state of AXI DMA operations.&#xA;For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.&#xA;For Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle.      1 - Idle.   Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIncld">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMAIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.&#xA;This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors      1 - DMA Internal Error detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMASlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMADecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.     0 - No DMA Decode Errors.   1 - DMA Decode Error detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected.  Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGSlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGDecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.&#xA;Writing a 1 to this bit will clear it.      0 - No error Interrupt.      1 - Error interrupt detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThresholdSts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold Status. Indicates current interrupt threshold value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelaySts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Status. Indicates current interrupt delay time value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_CURDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x38"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). &#xA;Buffer Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and so forth. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_CURDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x3C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_TAILDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x40"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel DMACR.RS bit is set to 0 (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. &#xA;Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_TAILDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x44"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DA">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Destination Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x48"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Destination_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.&#xA;Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DA_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM Destination Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x4C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Destination_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.&#xA;Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_LENGTH">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Transfer Length Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x58"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Length">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.&#xA;At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.&#xA;Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
          </REGISTERS>
        </ADDRESSBLOCK>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="C_S_AXI_LITE_ADDR_WIDTH" VALUE="10"/>
        <PARAMETER NAME="C_S_AXI_LITE_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_DLYTMR_RESOLUTION" VALUE="125"/>
        <PARAMETER NAME="C_PRMRY_IS_ACLK_ASYNC" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_MULTI_CHANNEL" VALUE="0"/>
        <PARAMETER NAME="C_NUM_MM2S_CHANNELS" VALUE="1"/>
        <PARAMETER NAME="C_NUM_S2MM_CHANNELS" VALUE="1"/>
        <PARAMETER NAME="C_INCLUDE_SG" VALUE="0"/>
        <PARAMETER NAME="C_SG_INCLUDE_STSCNTRL_STRM" VALUE="0"/>
        <PARAMETER NAME="C_SG_USE_STSAPP_LENGTH" VALUE="0"/>
        <PARAMETER NAME="C_SG_LENGTH_WIDTH" VALUE="26"/>
        <PARAMETER NAME="C_M_AXI_SG_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_SG_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXIS_S2MM_STS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_MICRO_DMA" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_MM2S" VALUE="1"/>
        <PARAMETER NAME="C_INCLUDE_MM2S_SF" VALUE="1"/>
        <PARAMETER NAME="C_MM2S_BURST_SIZE" VALUE="16"/>
        <PARAMETER NAME="C_M_AXI_MM2S_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_MM2S_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_MM2S_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_INCLUDE_MM2S_DRE" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_S2MM" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_S2MM_SF" VALUE="1"/>
        <PARAMETER NAME="C_S2MM_BURST_SIZE" VALUE="16"/>
        <PARAMETER NAME="C_M_AXI_S2MM_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_S2MM_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXIS_S2MM_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_INCLUDE_S2MM_DRE" VALUE="0"/>
        <PARAMETER NAME="C_INCREASE_THROUGHPUT" VALUE="0"/>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axi_dma_gen_0"/>
        <PARAMETER NAME="c_include_sg" VALUE="0"/>
        <PARAMETER NAME="c_enable_multi_channel" VALUE="0"/>
        <PARAMETER NAME="c_num_mm2s_channels" VALUE="1"/>
        <PARAMETER NAME="c_num_s2mm_channels" VALUE="1"/>
        <PARAMETER NAME="c_sg_length_width" VALUE="26"/>
        <PARAMETER NAME="c_dlytmr_resolution" VALUE="125"/>
        <PARAMETER NAME="c_prmry_is_aclk_async" VALUE="0"/>
        <PARAMETER NAME="c_sg_include_stscntrl_strm" VALUE="0"/>
        <PARAMETER NAME="c_micro_dma" VALUE="0"/>
        <PARAMETER NAME="c_include_mm2s" VALUE="1"/>
        <PARAMETER NAME="c_m_axi_mm2s_data_width" VALUE="32"/>
        <PARAMETER NAME="c_m_axis_mm2s_tdata_width" VALUE="32"/>
        <PARAMETER NAME="c_include_mm2s_dre" VALUE="0"/>
        <PARAMETER NAME="c_include_mm2s_sf" VALUE="1"/>
        <PARAMETER NAME="c_mm2s_burst_size" VALUE="16"/>
        <PARAMETER NAME="c_include_s2mm" VALUE="0"/>
        <PARAMETER NAME="c_sg_use_stsapp_length" VALUE="0"/>
        <PARAMETER NAME="c_m_axi_s2mm_data_width" VALUE="32"/>
        <PARAMETER NAME="c_s_axis_s2mm_tdata_width" VALUE="32"/>
        <PARAMETER NAME="c_include_s2mm_dre" VALUE="0"/>
        <PARAMETER NAME="c_include_s2mm_sf" VALUE="1"/>
        <PARAMETER NAME="c_s2mm_burst_size" VALUE="16"/>
        <PARAMETER NAME="c_addr_width" VALUE="32"/>
        <PARAMETER NAME="c_single_interface" VALUE="0"/>
        <PARAMETER NAME="c_increase_throughput" VALUE="0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0242000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0242FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_lite_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="m_axi_mm2s_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="axi_resetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_awvalid" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_awready" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="9" NAME="s_axi_lite_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_wvalid" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_wready" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_bvalid" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_bready" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_arvalid" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_arready" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="9" NAME="s_axi_lite_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_rvalid" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_rready" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axi_mm2s_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S02_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="m_axi_mm2s_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S02_AXI_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_mm2s_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S02_AXI_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="m_axi_mm2s_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S02_AXI_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_mm2s_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S02_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m_axi_mm2s_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S02_AXI_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_mm2s_arvalid" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S02_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_mm2s_arready" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S02_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="m_axi_mm2s_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S02_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="m_axi_mm2s_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S02_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_mm2s_rlast" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S02_AXI_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_mm2s_rvalid" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S02_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_mm2s_rready" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S02_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="mm2s_prmry_reset_out_n" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="O" LEFT="31" NAME="m_axis_mm2s_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axis_mm2s_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m_axis_mm2s_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axis_mm2s_tkeep">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axis_tkeep"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_mm2s_tvalid" SIGIS="undef" SIGNAME="axi_dma_gen_m_axis_mm2s_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_mm2s_tready" SIGIS="undef" SIGNAME="axi_dma_gen_m_axis_mm2s_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_mm2s_tlast" SIGIS="undef" SIGNAME="axi_dma_gen_m_axis_mm2s_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axis_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="mm2s_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_dma_gen_mm2s_introut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconcat_0" PORT="In2"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M06_AXI" DATAWIDTH="32" NAME="S_AXI_LITE" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="10"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_lite_araddr"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_lite_arready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_lite_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_lite_awaddr"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_lite_awready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_lite_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_lite_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_lite_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_lite_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_lite_rdata"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_lite_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_lite_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_lite_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_lite_wdata"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_lite_wready"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_lite_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_dma_gen_M_AXI_MM2S" DATAWIDTH="32" NAME="M_AXI_MM2S" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_ONLY"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="0"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="m_axi_mm2s_araddr"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="m_axi_mm2s_arburst"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="m_axi_mm2s_arcache"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="m_axi_mm2s_arlen"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="m_axi_mm2s_arprot"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="m_axi_mm2s_arready"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="m_axi_mm2s_arsize"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="m_axi_mm2s_arvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="m_axi_mm2s_rdata"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="m_axi_mm2s_rlast"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="m_axi_mm2s_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="m_axi_mm2s_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="m_axi_mm2s_rvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_dma_gen_M_AXIS_MM2S" NAME="M_AXIS_MM2S" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_mm2s_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="m_axis_mm2s_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_mm2s_tlast"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_mm2s_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_mm2s_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE ADDRESSBLOCK="HPC0_DDR_LOW" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7FFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_MM2S" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HPC0_FPD"/>
        <MEMRANGE ADDRESSBLOCK="HPC0_QSPI" BASENAME="C_BASEADDR" BASEVALUE="0xC0000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xDFFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_MM2S" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HPC0_FPD"/>
      </MEMORYMAP>
      <PERIPHERALS>
        <PERIPHERAL INSTANCE="zynq_ultra_ps_e_0"/>
      </PERIPHERALS>
    </MODULE>
    <MODULE COREREVISION="27" FULLNAME="/axi_dma_mr" HWVERSION="7.1" INSTANCE="axi_dma_mr" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_dma;v=v7_1;d=pg021_axi_dma.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI_LITE" NAME="Reg" RANGE="4096" USAGE="register">
          <REGISTERS>
            <REGISTER NAME="MM2S_DMACR">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10002"/>
              <FIELDS>
                <FIELD NAME="RS">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Run / Stop control for controlling running and stopping of the DMA channel.&#xA;  0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. &#xA;  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.&#xA;  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.&#xA;  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.&#xA;  1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.&#xA;AXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Normal operation.   1 - Reset in progress.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Keyhole">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.&#xA;This bit is non functional when the multichannel feature is enabled or in Direct Register mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Cyclic_BD_Enable">
                  <PROPERTY NAME="DESCRIPTION" VALUE="When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.&#xA;This bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.&#xA;This bit is non functional when DMA operates in multichannel mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set.   0 - IOC Interrupt disabled      1 - IOC Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out.      0 - Delay Interrupt disabled   1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error Interrupt Enable.&#xA;  0 - Error Interrupt disabled&#xA;  1 - Error Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThreshold">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.   Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.   Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelay">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.&#xA;Note: Setting this value to zero disables the delay timer interrupt.&#xA;Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_DMASR">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x04"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10000"/>
              <FIELDS>
                <FIELD NAME="Halted">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Idle">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Idle. Indicates the state of AXI DMA operations.&#xA;For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.&#xA;For Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete.      1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused.  Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIncld">
                  <PROPERTY NAME="DESCRIPTION" VALUE="1 - Scatter Gather Enabled&#xA;0 - Scatter Gather not enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMAIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors        1 - DMA Internal Error detected. DMA Engine halts&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMASlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected. DMA Engine halts&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMADecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Decode Errors.      1 - DMA Decode Error detected. DMA Engine halts.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGSlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGDecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected.  Writing a 1 to this bit will clear it.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.&#xA;Writing a 1 to this bit will clear it.   &#xA;0 - No error Interrupt.   &#xA;1 - Error interrupt detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThresholdSts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold Status. Indicates current interrupt threshold value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelaySts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Status. Indicates current interrupt delay time value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_CURDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_CURDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_TAILDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_TAILDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x14"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_SA">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S Source Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x18"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Source_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.&#xA;Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_SA_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S Source Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Source_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.&#xA;Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_LENGTH">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Transfer Length Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x28"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Length">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SG_CTL">
              <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather User and Cache Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x03"/>
              <FIELDS>
                <FIELD NAME="SG_CACHE">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather Cache Control. Values written in this register reflect on the m_axi_sg_arcache and m_axi_sg_awcache signals of the M_AXI_SG interface.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
                </FIELD>
                <FIELD NAME="SG_USER">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather User Control. Values written in this register reflect on the m_axi_sg_aruser and m_axi_sg_awuser signals of the M_AXI_SG interface.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DMACR">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x30"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10002"/>
              <FIELDS>
                <FIELD NAME="RS">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Run / Stop control for controlling running and stopping of the DMA channel.&#xA;  0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. &#xA;  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.&#xA;  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.&#xA;  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.&#xA;  1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.&#xA;AXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Reset not in progress. Normal operation.      1 - Reset in progress&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Keyhole">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.&#xA;This bit is non functional when DMA is used in multichannel mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Cyclic_BD_Enable">
                  <PROPERTY NAME="DESCRIPTION" VALUE="When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.&#xA;This bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set.      0 - IOC Interrupt disabled      1 - IOC Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Delay Interrupt disabled      1 - Delay Interrupt enabled  Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Error Interrupt disabled      1 - Error Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThreshold">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.&#xA;Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelay">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.&#xA;Note: Setting this value to zero disables the delay timer interrupt.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DMASR">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x34"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10000"/>
              <FIELDS>
                <FIELD NAME="Halted">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 &#xA;Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Idle">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Idle. Indicates the state of AXI DMA operations.&#xA;For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.&#xA;For Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle.      1 - Idle.   Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIncld">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMAIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.&#xA;This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors      1 - DMA Internal Error detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMASlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMADecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.     0 - No DMA Decode Errors.   1 - DMA Decode Error detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected.  Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGSlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGDecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.&#xA;Writing a 1 to this bit will clear it.      0 - No error Interrupt.      1 - Error interrupt detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThresholdSts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold Status. Indicates current interrupt threshold value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelaySts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Status. Indicates current interrupt delay time value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_CURDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x38"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). &#xA;Buffer Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and so forth. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_CURDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x3C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_TAILDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x40"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel DMACR.RS bit is set to 0 (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. &#xA;Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_TAILDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x44"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DA">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Destination Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x48"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Destination_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.&#xA;Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DA_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM Destination Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x4C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Destination_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.&#xA;Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_LENGTH">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Transfer Length Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x58"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Length">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.&#xA;At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.&#xA;Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
          </REGISTERS>
        </ADDRESSBLOCK>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="C_S_AXI_LITE_ADDR_WIDTH" VALUE="10"/>
        <PARAMETER NAME="C_S_AXI_LITE_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_DLYTMR_RESOLUTION" VALUE="125"/>
        <PARAMETER NAME="C_PRMRY_IS_ACLK_ASYNC" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_MULTI_CHANNEL" VALUE="0"/>
        <PARAMETER NAME="C_NUM_MM2S_CHANNELS" VALUE="1"/>
        <PARAMETER NAME="C_NUM_S2MM_CHANNELS" VALUE="1"/>
        <PARAMETER NAME="C_INCLUDE_SG" VALUE="0"/>
        <PARAMETER NAME="C_SG_INCLUDE_STSCNTRL_STRM" VALUE="0"/>
        <PARAMETER NAME="C_SG_USE_STSAPP_LENGTH" VALUE="0"/>
        <PARAMETER NAME="C_SG_LENGTH_WIDTH" VALUE="26"/>
        <PARAMETER NAME="C_M_AXI_SG_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_SG_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXIS_S2MM_STS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_MICRO_DMA" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_MM2S" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_MM2S_SF" VALUE="1"/>
        <PARAMETER NAME="C_MM2S_BURST_SIZE" VALUE="16"/>
        <PARAMETER NAME="C_M_AXI_MM2S_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_MM2S_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_MM2S_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_INCLUDE_MM2S_DRE" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_S2MM" VALUE="1"/>
        <PARAMETER NAME="C_INCLUDE_S2MM_SF" VALUE="1"/>
        <PARAMETER NAME="C_S2MM_BURST_SIZE" VALUE="16"/>
        <PARAMETER NAME="C_M_AXI_S2MM_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_S2MM_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXIS_S2MM_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_INCLUDE_S2MM_DRE" VALUE="0"/>
        <PARAMETER NAME="C_INCREASE_THROUGHPUT" VALUE="0"/>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axi_dma_mr_0"/>
        <PARAMETER NAME="c_include_sg" VALUE="0"/>
        <PARAMETER NAME="c_enable_multi_channel" VALUE="0"/>
        <PARAMETER NAME="c_num_mm2s_channels" VALUE="1"/>
        <PARAMETER NAME="c_num_s2mm_channels" VALUE="1"/>
        <PARAMETER NAME="c_sg_length_width" VALUE="26"/>
        <PARAMETER NAME="c_dlytmr_resolution" VALUE="125"/>
        <PARAMETER NAME="c_prmry_is_aclk_async" VALUE="0"/>
        <PARAMETER NAME="c_sg_include_stscntrl_strm" VALUE="0"/>
        <PARAMETER NAME="c_micro_dma" VALUE="0"/>
        <PARAMETER NAME="c_include_mm2s" VALUE="0"/>
        <PARAMETER NAME="c_m_axi_mm2s_data_width" VALUE="32"/>
        <PARAMETER NAME="c_m_axis_mm2s_tdata_width" VALUE="32"/>
        <PARAMETER NAME="c_include_mm2s_dre" VALUE="0"/>
        <PARAMETER NAME="c_include_mm2s_sf" VALUE="1"/>
        <PARAMETER NAME="c_mm2s_burst_size" VALUE="16"/>
        <PARAMETER NAME="c_include_s2mm" VALUE="1"/>
        <PARAMETER NAME="c_sg_use_stsapp_length" VALUE="0"/>
        <PARAMETER NAME="c_m_axi_s2mm_data_width" VALUE="32"/>
        <PARAMETER NAME="c_s_axis_s2mm_tdata_width" VALUE="32"/>
        <PARAMETER NAME="c_include_s2mm_dre" VALUE="0"/>
        <PARAMETER NAME="c_include_s2mm_sf" VALUE="1"/>
        <PARAMETER NAME="c_s2mm_burst_size" VALUE="16"/>
        <PARAMETER NAME="c_addr_width" VALUE="32"/>
        <PARAMETER NAME="c_single_interface" VALUE="0"/>
        <PARAMETER NAME="c_increase_throughput" VALUE="0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0252000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0252FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_lite_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="m_axi_s2mm_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="axi_resetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_awvalid" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_awready" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="9" NAME="s_axi_lite_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_wvalid" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_wready" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_bvalid" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_bready" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_arvalid" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_arready" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="9" NAME="s_axi_lite_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_rvalid" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_rready" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axi_s2mm_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="m_axi_s2mm_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="m_axi_s2mm_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m_axi_s2mm_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_awvalid" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_s2mm_awready" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axi_s2mm_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m_axi_s2mm_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_wlast" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_wvalid" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_s2mm_wready" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="m_axi_s2mm_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_s2mm_bvalid" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_bready" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S05_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s2mm_prmry_reset_out_n" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="I" LEFT="31" NAME="s_axis_s2mm_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axis_s2mm_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="m00_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axis_s2mm_tkeep" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="s_axis_s2mm_tvalid" SIGIS="undef" SIGNAME="axi_dma_mr_s_axis_s2mm_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="m00_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_s2mm_tready" SIGIS="undef" SIGNAME="axi_dma_mr_s_axis_s2mm_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="m00_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_s2mm_tlast" SIGIS="undef" SIGNAME="axi_dma_mr_s_axis_s2mm_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="m00_axis_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s2mm_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_dma_mr_s2mm_introut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconcat_0" PORT="In5"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M25_AXI" DATAWIDTH="32" NAME="S_AXI_LITE" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="10"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_lite_araddr"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_lite_arready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_lite_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_lite_awaddr"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_lite_awready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_lite_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_lite_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_lite_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_lite_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_lite_rdata"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_lite_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_lite_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_lite_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_lite_wdata"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_lite_wready"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_lite_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_dma_mr_M_AXI_S2MM" DATAWIDTH="32" NAME="M_AXI_S2MM" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="WRITE_ONLY"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="m_axi_s2mm_awaddr"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="m_axi_s2mm_awburst"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="m_axi_s2mm_awcache"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="m_axi_s2mm_awlen"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="m_axi_s2mm_awprot"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="m_axi_s2mm_awready"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="m_axi_s2mm_awsize"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="m_axi_s2mm_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="m_axi_s2mm_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="m_axi_s2mm_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="m_axi_s2mm_bvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="m_axi_s2mm_wdata"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="m_axi_s2mm_wlast"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="m_axi_s2mm_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="m_axi_s2mm_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="m_axi_s2mm_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="mr_buffer_et_0_m00_axis" NAME="S_AXIS_S2MM" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_s2mm_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="s_axis_s2mm_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="s_axis_s2mm_tlast"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_s2mm_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_s2mm_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE ADDRESSBLOCK="HPC0_DDR_LOW" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7FFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_S2MM" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HPC0_FPD"/>
        <MEMRANGE ADDRESSBLOCK="HPC0_QSPI" BASENAME="C_BASEADDR" BASEVALUE="0xC0000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xDFFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_S2MM" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HPC0_FPD"/>
      </MEMORYMAP>
      <PERIPHERALS>
        <PERIPHERAL INSTANCE="zynq_ultra_ps_e_0"/>
      </PERIPHERALS>
    </MODULE>
    <MODULE COREREVISION="27" FULLNAME="/axi_dma_tproc" HWVERSION="7.1" INSTANCE="axi_dma_tproc" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axi_dma" VLNV="xilinx.com:ip:axi_dma:7.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_dma;v=v7_1;d=pg021_axi_dma.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI_LITE" NAME="Reg" RANGE="4096" USAGE="register">
          <REGISTERS>
            <REGISTER NAME="MM2S_DMACR">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10002"/>
              <FIELDS>
                <FIELD NAME="RS">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Run / Stop control for controlling running and stopping of the DMA channel.&#xA;  0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. &#xA;  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.&#xA;  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated.&#xA;  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.&#xA;  1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.&#xA;AXI4-Stream outs are potentially terminated early. Setting either MM2S_DMACR. Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Normal operation.   1 - Reset in progress.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Keyhole">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Keyhole Read. Setting this bit to 1 causes AXI DMA to initiate MM2S reads (AXI4read) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be updated when AXI DMA is in idle. When using keyhole operation the Max Burst Length should not exceed 16. This bit should not be set when DRE is enabled.&#xA;This bit is non functional when the multichannel feature is enabled or in Direct Register mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Cyclic_BD_Enable">
                  <PROPERTY NAME="DESCRIPTION" VALUE="When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.&#xA;This bit should be set/unset only when the DMA is idle or when not running. Updating this bit while the DMA is running can result in unexpected behavior.&#xA;This bit is non functional when DMA operates in multichannel mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows DMASR.IOC_Irq to generate an interrupt out for descriptors with the IOC bit set.   0 - IOC Interrupt disabled      1 - IOC Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay Timer Interrupt Enable. When set to 1, allows DMASR.Dly_Irq to generate an interrupt out.      0 - Delay Interrupt disabled   1 - Delay Interrupt enabled Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error Interrupt Enable.&#xA;  0 - Error Interrupt disabled&#xA;  1 - Error Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThreshold">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.   Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.   Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelay">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.&#xA;Note: Setting this value to zero disables the delay timer interrupt.&#xA;Note: This field is ignored when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_DMASR">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x04"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10000"/>
              <FIELDS>
                <FIELD NAME="Halted">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter / Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register mode (C_INCLUDE_SG = 0) this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Idle">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Idle. Indicates the state of AXI DMA operations.&#xA;For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.&#xA;For Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle. For Scatter / Gather Mode, SG has not reached tail descriptor pointer and/or DMA operations in progress. For Direct Register Mode, transfer is not complete.      1 - Idle. For Scatter / Gather Mode, SG has reached tail descriptor pointer and DMA operation paused. for Direct Register Mode, DMA transfer has completed and controller is paused.  Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIncld">
                  <PROPERTY NAME="DESCRIPTION" VALUE="1 - Scatter Gather Enabled&#xA;0 - Scatter Gather not enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMAIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Internal Error. Internal error occurs if the buffer length specified in the fetched descriptor is set to 0. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors        1 - DMA Internal Error detected. DMA Engine halts&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMASlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected. DMA Engine halts&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMADecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Decode Errors.      1 - DMA Decode Error detected. DMA Engine halts.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. Refer to the Scatter Gather Descriptor section for more information.This indicates to the SG Engine that the descriptor is a stale descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGSlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGDecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts.  Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit is enabled in the MM2S_DMACR (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected.  Writing a 1 to this bit will clear it.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the MM2S_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected. Note: This bit is not used and is fixed at 0 when AXI DMA is configured for Direct Register Mode. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the MM2S_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.&#xA;Writing a 1 to this bit will clear it.   &#xA;0 - No error Interrupt.   &#xA;1 - Error interrupt detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThresholdSts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold Status. Indicates current interrupt threshold value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelaySts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Status. Indicates current interrupt delay time value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_CURDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x08"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_CURDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_TAILDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_TAILDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x14"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_SA">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S Source Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x18"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Source_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.&#xA;Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_SA_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S Source Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Source_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the MSB 32 bits of the source address AXI DMA reads from to transfer data to AXI4-Stream on the MM2S Channel.&#xA;Note: If Data Realignment Engine is included, the Source Address can be at any byte offset. If Data Realignment Engine is not included, the Source Address must be MM2S Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MM2S_LENGTH">
              <PROPERTY NAME="DESCRIPTION" VALUE="MM2S DMA Transfer Length Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x28"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Length">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the number of bytes to transfer for the MM2S channel. Writing a non-zero value to this register starts the MM2S transfer.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SG_CTL">
              <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather User and Cache Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x03"/>
              <FIELDS>
                <FIELD NAME="SG_CACHE">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather Cache Control. Values written in this register reflect on the m_axi_sg_arcache and m_axi_sg_awcache signals of the M_AXI_SG interface.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
                </FIELD>
                <FIELD NAME="SG_USER">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter/Gather User Control. Values written in this register reflect on the m_axi_sg_aruser and m_axi_sg_awuser signals of the M_AXI_SG interface.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DMACR">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x30"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10002"/>
              <FIELDS>
                <FIELD NAME="RS">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Run / Stop control for controlling running and stopping of the DMA channel.&#xA;  0 - Stop – DMA stops when current (if any) DMA operations are complete. For Scatter / Gather Mode pending commands/transfers are flushed or completed. &#xA;  AXI4-Stream outs are potentially terminated early. Descriptors in the update queue are allowed to finish updating to remote memory before engine halt.&#xA;  For Direct Register mode pending commands/transfers are flushed or completed. AXI4-Stream outs are potentially terminated. Data integrity on S2MM AXI4 cannot be guaranteed.&#xA;  The halted bit in the DMA Status register asserts to 1 when the DMA engine is halted. This bit is cleared by AXI DMA hardware when an error occurs. The CPU can also choose to clear this bit to stop DMA operations.&#xA;  1 - Run – Start DMA operations. The halted bit in the DMA Status register deasserts to 0 when the DMA engine begins operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Soft reset for resetting the AXI DMA core. Setting this bit to a 1 causes the AXI DMA to be reset. Reset is accomplished gracefully. Pending commands/transfers are flushed or completed.&#xA;AXI4-Stream outs are terminated early, if necessary with associated TLAST. Setting either MM2S_DMACR.Reset = 1 or S2MM_DMACR.Reset = 1 resets the entire AXI DMA engine. After completion of a soft reset, all registers and bits are in the Reset State.      0 - Reset not in progress. Normal operation.      1 - Reset in progress&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Keyhole">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Keyhole Write. Setting this bit to 1 causes AXI DMA to initiate S2MM writes (AXI4 Writes) in non-incrementing address mode (Fixed Address Burst transfer on AXI4). This bit can be modified when AXI DMA is in idle. When enabling Key hole operation the maximum burst length cannot be more than 16. This bit should not be set when DRE is enabled.&#xA;This bit is non functional when DMA is used in multichannel mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Cyclic_BD_Enable">
                  <PROPERTY NAME="DESCRIPTION" VALUE="When set to 1, the DMA operates in Cyclic Buffer Descriptor (BD) mode without any user intervention. In this mode, the Scatter Gather module ignores the Completed bit of the BD. With this bit set, you can use the same BDs in cyclic manner without worrying about any stale descriptor errors.&#xA;This bit is non functional when DMA operates in Multichannel mode. or in Direct Register Mode&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete (IOC) Interrupt Enable. When set to 1, allows Interrupt On Complete events to generate an interrupt out for descriptors with the Complete bit set.      0 - IOC Interrupt disabled      1 - IOC Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay Timer Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Delay Interrupt disabled      1 - Delay Interrupt enabled  Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_IrqEn">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error Interrupt Enable. When set to 1, allows error events to generate an interrupt out.      0 - Error Interrupt disabled      1 - Error Interrupt enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThreshold">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold. This value is used for setting the interrupt threshold. When IOC interrupt events occur, an internal counter counts down from the Interrupt Threshold setting. When the count reaches zero, an interrupt out is generated by the DMA engine.&#xA;Note: The minimum setting for the threshold is 0x01. A write of 0x00 to this register has no effect.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelay">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Out. This value is used for setting the interrupt timeout value. The interrupt timeout mechanism causes the DMA engine to generate an interrupt after the delay time period has expired. Timer begins counting at the end of a packet and resets with receipt of a new packet or a timeout event occurs.&#xA;Note: Setting this value to zero disables the delay timer interrupt.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DMASR">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x34"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x10000"/>
              <FIELDS>
                <FIELD NAME="Halted">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Halted. Indicates the run/stop state of the DMA channel.      0 - DMA channel running.      1 - DMA channel halted.  For Scatter/Gather Mode this bit gets set when DMACR.RS = 0 and DMA and SG operations have halted. For Direct Register Mode this bit gets set when DMACR.RS = 0 and DMA operations have halted. There can be a lag of time between when DMACR.RS = 0 and when DMASR.Halted = 1 &#xA;Note: When halted (RS= 0 and Halted = 1), writing to CURDESC_PTR or TAILDESC_PTR pointer registers has no effect on DMA operations when in Scatter Gather Mode. For Direct Register Mode, writing to the LENGTH register has no effect on DMA operations.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Idle">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Channel Idle. Indicates the state of AXI DMA operations.&#xA;For Scatter / Gather Mode when IDLE indicates the SG Engine has reached the tail pointer for the associated channel and all queued descriptors have been processed. Writing to the tail pointer register automatically restarts DMA operations.&#xA;For Direct Register Mode when IDLE indicates the current transfer has completed.      0 - Not Idle.      1 - Idle.   Note: This bit is 0 when channel is halted (DMASR.Halted=1). This bit is also 0 prior to initial transfer when AXI DMA configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIncld">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Engine Included. DMASR.SGIncld = 1 indicates the Scatter Gather engine is included and the AXI DMA is configured for Scatter Gather mode. DMASR.SGIncld = 0 indicates the Scatter Gather engine is excluded and the AXI DMA is configured for Direct Register Mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMAIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Internal Error. This error occurs if the buffer length specified in the fetched descriptor is set to 0. Also, when in Scatter Gather Mode and using the status app length field, this error occurs when the Status AXI4-Stream packet RxLength field does not match the S2MM packet being received by the S_AXIS_S2MM interface. When Scatter Gather is disabled, this error is flagged if any error occurs during Memory write or if the incoming packet is bigger than what is specified in the DMA length register.&#xA;This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Internal Errors      1 - DMA Internal Error detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMASlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Slave Error. This error occurs if the slave read from the Memory Map interface issues a Slave Error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No DMA Slave Errors.      1 - DMA Slave Error detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DMADecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DMA Decode Error. This error occurs if the address request points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.     0 - No DMA Decode Errors.   1 - DMA Decode Error detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGIntErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Internal Error. This error occurs if a descriptor with the “Complete bit” already set is fetched. This indicates to the SG Engine that the descriptor is a tail descriptor. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Internal Errors.      1 - SG Internal Error detected.  Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGSlvErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Slave Error. This error occurs if the slave read from on the Memory Map interface issues a Slave error. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Slave Errors.      1 - SG Slave Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SGDecErr">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Scatter Gather Decode Error. This error occurs if CURDESC_PTR and/or NXTDESC_PTR points to an invalid address. This error condition causes the AXI DMA to halt gracefully. The DMACR.RS bit is set to 0, and when the engine has completely shut down, the DMASR.Halted bit is set to 1.      0 - No SG Decode Errors.      1 - SG Decode Error detected. DMA Engine halts. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IOC_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Complete. When set to 1 for Scatter/Gather Mode, indicates an interrupt event was generated on completion of a descriptor. This occurs for descriptors with the End of Frame (EOF) bit set. When set to 1 for Direct Register Mode, indicates an interrupt event was generated on completion of a transfer. If the corresponding bit in S2MM_DMACR is enabled (IOC_IrqEn = 1) and if the interrupt threshold has been met, causes an interrupt out to be generated from the AXI DMA.      0 - No IOC Interrupt.      1 - IOC Interrupt detected. Writing a 1 to this bit will clear it.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Dly_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Delay. When set to 1, indicates an interrupt event was generated on delay timer time out. If the corresponding bit is enabled in the S2MM_DMACR (Dly_IrqEn = 1), an interrupt out is generated from the AXI DMA.      0 - No Delay Interrupt.      1 - Delay Interrupt detected.1 = IOC Interrupt detected. Writing a 1 to this bit will clear it. Note: Applicable only when Scatter Gather is enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Err_Irq">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt on Error. When set to 1, indicates an interrupt event was generated on error. If the corresponding bit is enabled in the S2MM_DMACR (Err_IrqEn = 1), an interrupt out is generated from the AXI DMA.&#xA;Writing a 1 to this bit will clear it.      0 - No error Interrupt.      1 - Error interrupt detected.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="14"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="IRQThresholdSts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Threshold Status. Indicates current interrupt threshold value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="16"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
                <FIELD NAME="IRQDelaySts">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Delay Time Status. Indicates current interrupt delay time value.&#xA;Note: Applicable only when Scatter Gather is enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="24"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_CURDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x38"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). &#xA;Buffer Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and so forth. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_CURDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Current Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x3C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Current_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pointer of the current descriptor being worked on. This register must contain a pointer to a valid descriptor prior to writing the TAILDESC_PTR register. Otherwise, undefined results occur. When DMACR.RS is 1, CURDESC_PTR becomes Read Only (RO) and is used to fetch the first descriptor.&#xA;When the DMA Engine is running (DMACR.RS=1), CURDESC_PTR registers are updated by AXI DMA to indicate the current descriptor being worked on.&#xA;On error detection, CURDESC_PTR is updated to reflect the descriptor associated with the detected error.&#xA;Note: The register can only be written to by the CPU when the DMA Engine is Halted (DMACR.RS=0 and DMASR.Halted =1). At all other times, this register is Read Only (RO). Descriptors must be 16 word aligned, that is, 0x00, 0x40, 0x80 and others. Any other alignment has undefined results.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_TAILDESC">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x40"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel DMACR.RS bit is set to 0 (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. &#xA;Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_TAILDESC_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Tail Descriptor Pointer Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x44"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Tail_Descriptor_Pointer">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the pause pointer in a descriptor chain. The AXI DMA SG Engine pauses descriptor fetching after completing operations on the descriptor whose current descriptor pointer matches the tail descriptor pointer.&#xA;When AXI DMA Channel is not halted (DMASR.Halted = 0), a write by the CPU to the TAILDESC_PTR register causes the AXI DMA SG Engine to start fetching descriptors or restart if it was idle (DMASR.Idle = 1). If it was not idle, writing TAILDESC_PTR has no effect except to reposition the pause point.&#xA;If the AXI DMA Channel is halted (DMASR.Halted = 1 and DMACR.RS = 0), a write by the CPU to the TAILDESC_PTR register has no effect except to reposition the pause point.&#xA;Note: The software must not move the tail pointer to a location that has not been updated. The software processes and reallocates all completed descriptors (Cmplted = 1), clears the completed bits and then moves the tail pointer. The software must move the pointer to the last descriptor it updated. Descriptors must be 16-word aligned, that is, 0x00, 0x40, 0x80, and so forth. Any other alignment has undefined results. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DA">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Destination Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x48"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Destination_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the destination address the AXI DMA writes to transfer data from AXI4-Stream on S2MM Channel.&#xA;Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Destination Address must be S2MM Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_DA_MSB">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM Destination Address Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x4C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Destination_Address">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the MSB 32 bits of the Destination address AXI DMA writes to transfer data from AXI4-Stream on the S2MM Channel.&#xA;Note: If Data Realignment Engine is included, the Destination Address can be at any byte offset. If Data Realignment Engine is not included, the Dstination Address must be S2MM Memory Map data width aligned.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="S2MM_LENGTH">
              <PROPERTY NAME="DESCRIPTION" VALUE="S2MM DMA Transfer Length Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x58"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Length">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Indicates the length in bytes of the S2MM buffer available to write receive data from the S2MM channel. Writing a non-zero value to this register enables S2MM channel to receive packet data.&#xA;At the completion of the S2MM transfer, the number of actual bytes written on the S2MM AXI4 interface is updated to the S2MM_LENGTH register.&#xA;Note: This value must be greater than or equal to the largest expected packet to be received on S2MM AXI4-Stream. Values smaller than the received packet result in undefined behavior. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="26"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
          </REGISTERS>
        </ADDRESSBLOCK>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="C_S_AXI_LITE_ADDR_WIDTH" VALUE="10"/>
        <PARAMETER NAME="C_S_AXI_LITE_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_DLYTMR_RESOLUTION" VALUE="125"/>
        <PARAMETER NAME="C_PRMRY_IS_ACLK_ASYNC" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_MULTI_CHANNEL" VALUE="0"/>
        <PARAMETER NAME="C_NUM_MM2S_CHANNELS" VALUE="1"/>
        <PARAMETER NAME="C_NUM_S2MM_CHANNELS" VALUE="1"/>
        <PARAMETER NAME="C_INCLUDE_SG" VALUE="0"/>
        <PARAMETER NAME="C_SG_INCLUDE_STSCNTRL_STRM" VALUE="0"/>
        <PARAMETER NAME="C_SG_USE_STSAPP_LENGTH" VALUE="0"/>
        <PARAMETER NAME="C_SG_LENGTH_WIDTH" VALUE="26"/>
        <PARAMETER NAME="C_M_AXI_SG_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_SG_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXIS_S2MM_STS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_MICRO_DMA" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_MM2S" VALUE="1"/>
        <PARAMETER NAME="C_INCLUDE_MM2S_SF" VALUE="1"/>
        <PARAMETER NAME="C_MM2S_BURST_SIZE" VALUE="2"/>
        <PARAMETER NAME="C_M_AXI_MM2S_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_MM2S_DATA_WIDTH" VALUE="256"/>
        <PARAMETER NAME="C_M_AXIS_MM2S_TDATA_WIDTH" VALUE="256"/>
        <PARAMETER NAME="C_INCLUDE_MM2S_DRE" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_S2MM" VALUE="1"/>
        <PARAMETER NAME="C_INCLUDE_S2MM_SF" VALUE="1"/>
        <PARAMETER NAME="C_S2MM_BURST_SIZE" VALUE="16"/>
        <PARAMETER NAME="C_M_AXI_S2MM_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXI_S2MM_DATA_WIDTH" VALUE="256"/>
        <PARAMETER NAME="C_S_AXIS_S2MM_TDATA_WIDTH" VALUE="256"/>
        <PARAMETER NAME="C_INCLUDE_S2MM_DRE" VALUE="0"/>
        <PARAMETER NAME="C_INCREASE_THROUGHPUT" VALUE="0"/>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axi_dma_tproc_0"/>
        <PARAMETER NAME="c_include_sg" VALUE="0"/>
        <PARAMETER NAME="c_enable_multi_channel" VALUE="0"/>
        <PARAMETER NAME="c_num_mm2s_channels" VALUE="1"/>
        <PARAMETER NAME="c_num_s2mm_channels" VALUE="1"/>
        <PARAMETER NAME="c_sg_length_width" VALUE="26"/>
        <PARAMETER NAME="c_dlytmr_resolution" VALUE="125"/>
        <PARAMETER NAME="c_prmry_is_aclk_async" VALUE="0"/>
        <PARAMETER NAME="c_sg_include_stscntrl_strm" VALUE="0"/>
        <PARAMETER NAME="c_micro_dma" VALUE="0"/>
        <PARAMETER NAME="c_include_mm2s" VALUE="1"/>
        <PARAMETER NAME="c_m_axi_mm2s_data_width" VALUE="256"/>
        <PARAMETER NAME="c_m_axis_mm2s_tdata_width" VALUE="256"/>
        <PARAMETER NAME="c_include_mm2s_dre" VALUE="0"/>
        <PARAMETER NAME="c_include_mm2s_sf" VALUE="1"/>
        <PARAMETER NAME="c_mm2s_burst_size" VALUE="2"/>
        <PARAMETER NAME="c_include_s2mm" VALUE="1"/>
        <PARAMETER NAME="c_sg_use_stsapp_length" VALUE="0"/>
        <PARAMETER NAME="c_m_axi_s2mm_data_width" VALUE="256"/>
        <PARAMETER NAME="c_s_axis_s2mm_tdata_width" VALUE="256"/>
        <PARAMETER NAME="c_include_s2mm_dre" VALUE="0"/>
        <PARAMETER NAME="c_include_s2mm_sf" VALUE="1"/>
        <PARAMETER NAME="c_s2mm_burst_size" VALUE="16"/>
        <PARAMETER NAME="c_addr_width" VALUE="32"/>
        <PARAMETER NAME="c_single_interface" VALUE="0"/>
        <PARAMETER NAME="c_increase_throughput" VALUE="0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0243000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0243FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_lite_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="m_axi_mm2s_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="m_axi_s2mm_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="axi_resetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_awvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_awready" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="9" NAME="s_axi_lite_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_wvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_wready" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_lite_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_lite_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_bvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_bready" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_arvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_arready" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="9" NAME="s_axi_lite_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_lite_rvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_lite_rready" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_lite_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_lite_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axi_mm2s_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="m_axi_mm2s_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_mm2s_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="m_axi_mm2s_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_mm2s_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m_axi_mm2s_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_mm2s_arvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_mm2s_arready" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="255" NAME="m_axi_mm2s_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="m_axi_mm2s_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_mm2s_rlast" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_mm2s_rvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_mm2s_rready" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S00_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="mm2s_prmry_reset_out_n" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="O" LEFT="255" NAME="m_axis_mm2s_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axis_mm2s_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_dma_axis_tdata_i"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axis_mm2s_tkeep" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="m_axis_mm2s_tvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axis_mm2s_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_dma_axis_tvalid_i"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_mm2s_tready" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axis_mm2s_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_dma_axis_tready_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_mm2s_tlast" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axis_mm2s_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_dma_axis_tlast_i"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axi_s2mm_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="m_axi_s2mm_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="m_axi_s2mm_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_s2mm_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m_axi_s2mm_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_awvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_s2mm_awready" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="255" NAME="m_axi_s2mm_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axi_s2mm_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_wlast" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_wvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_s2mm_wready" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="m_axi_s2mm_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_s2mm_bvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_s2mm_bready" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="S01_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s2mm_prmry_reset_out_n" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="I" LEFT="255" NAME="s_axis_s2mm_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axis_s2mm_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m_dma_axis_tdata_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axis_s2mm_tkeep" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="s_axis_s2mm_tvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axis_s2mm_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m_dma_axis_tvalid_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_s2mm_tready" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axis_s2mm_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m_dma_axis_tready_i"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_s2mm_tlast" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axis_s2mm_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m_dma_axis_tlast_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="mm2s_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_dma_tproc_mm2s_introut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconcat_0" PORT="In0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s2mm_introut" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_dma_tproc_s2mm_introut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconcat_0" PORT="In1"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M00_AXI" DATAWIDTH="32" NAME="S_AXI_LITE" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="10"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_lite_araddr"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_lite_arready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_lite_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_lite_awaddr"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_lite_awready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_lite_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_lite_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_lite_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_lite_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_lite_rdata"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_lite_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_lite_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_lite_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_lite_wdata"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_lite_wready"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_lite_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_dma_tproc_M_AXI_MM2S" DATAWIDTH="256" NAME="M_AXI_MM2S" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="256"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_ONLY"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="0"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="2"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="m_axi_mm2s_araddr"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="m_axi_mm2s_arburst"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="m_axi_mm2s_arcache"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="m_axi_mm2s_arlen"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="m_axi_mm2s_arprot"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="m_axi_mm2s_arready"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="m_axi_mm2s_arsize"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="m_axi_mm2s_arvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="m_axi_mm2s_rdata"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="m_axi_mm2s_rlast"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="m_axi_mm2s_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="m_axi_mm2s_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="m_axi_mm2s_rvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_dma_tproc_M_AXI_S2MM" DATAWIDTH="256" NAME="M_AXI_S2MM" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="256"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="WRITE_ONLY"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="m_axi_s2mm_awaddr"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="m_axi_s2mm_awburst"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="m_axi_s2mm_awcache"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="m_axi_s2mm_awlen"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="m_axi_s2mm_awprot"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="m_axi_s2mm_awready"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="m_axi_s2mm_awsize"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="m_axi_s2mm_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="m_axi_s2mm_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="m_axi_s2mm_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="m_axi_s2mm_bvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="m_axi_s2mm_wdata"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="m_axi_s2mm_wlast"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="m_axi_s2mm_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="m_axi_s2mm_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="m_axi_s2mm_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_dma_tproc_M_AXIS_MM2S" NAME="M_AXIS_MM2S" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_mm2s_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="m_axis_mm2s_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_mm2s_tlast"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_mm2s_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_mm2s_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m_dma_axis_o" NAME="S_AXIS_S2MM" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_s2mm_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="s_axis_s2mm_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="s_axis_s2mm_tlast"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_s2mm_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_s2mm_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE ADDRESSBLOCK="HPC0_DDR_LOW" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7FFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_MM2S" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HPC0_FPD"/>
        <MEMRANGE ADDRESSBLOCK="HPC0_DDR_LOW" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x7FFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_S2MM" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HPC0_FPD"/>
        <MEMRANGE ADDRESSBLOCK="HPC0_QSPI" BASENAME="C_BASEADDR" BASEVALUE="0xC0000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xDFFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_MM2S" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HPC0_FPD"/>
        <MEMRANGE ADDRESSBLOCK="HPC0_QSPI" BASENAME="C_BASEADDR" BASEVALUE="0xC0000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xDFFFFFFF" INSTANCE="zynq_ultra_ps_e_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_S2MM" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="S_AXI_HPC0_FPD"/>
      </MEMORYMAP>
      <PERIPHERALS>
        <PERIPHERAL INSTANCE="zynq_ultra_ps_e_0"/>
        <PERIPHERAL INSTANCE="qick_processor_0"/>
      </PERIPHERALS>
    </MODULE>
    <MODULE COREREVISION="17" FULLNAME="/axi_intc_0" HWVERSION="4.1" INSTANCE="axi_intc_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="INTERRUPT_CNTLR" MODTYPE="axi_intc" VLNV="xilinx.com:ip:axi_intc:4.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_intc;v=v4_1;d=pg099-axi-intc.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI" NAME="Reg" RANGE="4096" USAGE="register">
          <REGISTERS>
            <REGISTER NAME="ISR">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x0"/>
              <PROPERTY NAME="SIZE" VALUE="6"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="INT">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Status Register.&#xA;For each bit up to number of periperhal interrupts:&#xA;  R - Reads active interrupt signal.&#xA;  W - No effect after MER HIE bit has been set, otherwise writes active interrupt signal.&#xA;For remaining bits defined by number of software interrupts:&#xA;  R - Reads software interrupt value.&#xA;  W - Writes software interrupt value.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="6"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IPR">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Pending Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x4"/>
              <PROPERTY NAME="SIZE" VALUE="6"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="INT">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Pending Register.&#xA;For each bit:&#xA;  R - Reads logical AND of bits in ISR and IER.&#xA;  W - No effect.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="6"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IER">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Enable Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x8"/>
              <PROPERTY NAME="SIZE" VALUE="6"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="INT">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Enable Register.&#xA;For each bit:&#xA;  R - Reads interrupt enable value.&#xA;  W - Writes interrupt enable value.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="6"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IAR">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Acknowledge Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0xC"/>
              <PROPERTY NAME="SIZE" VALUE="6"/>
              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="INT">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Acknowledge Register.&#xA;For each bit:&#xA;  W - Acknowledge interrupt.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="6"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SIE">
              <PROPERTY NAME="DESCRIPTION" VALUE="Set Interrupt Enables"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10"/>
              <PROPERTY NAME="SIZE" VALUE="6"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="INT">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Set Interrupt Enables&#xA;For each bit:&#xA;  R - Reads active interrupt.&#xA;  W - Writing 1 enables the interrupt, writing 0 has no effect.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToSet"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="6"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="CIE">
              <PROPERTY NAME="DESCRIPTION" VALUE="Clear Interrupt Enables"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x14"/>
              <PROPERTY NAME="SIZE" VALUE="6"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="INT">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Clear Interrupt Enables&#xA;For each bit:&#xA;  R - Reads active interrupt.&#xA;  W - Writing 1 disables the interrupt, writing 0 has no effect.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToClear"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="6"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVR">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x18"/>
              <PROPERTY NAME="SIZE" VALUE="5"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="IVN">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Number.&#xA;  R - Reads ordinal of highest priority, enabled, active interrupt.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="5"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="MER">
              <PROPERTY NAME="DESCRIPTION" VALUE="Master Enable Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1C"/>
              <PROPERTY NAME="SIZE" VALUE="2"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="ME">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Master IRQ Enable.&#xA;  0 - All interrupts disabled.&#xA;  1 - All interrupts can be enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="HIE">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Hardware Interrupt Enable.&#xA;  0 - HW interrupts disabled.&#xA;  1 - HW interrupts enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IMR">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Mode Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x20"/>
              <PROPERTY NAME="SIZE" VALUE="6"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="INT">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Mode Register.&#xA;For each bit:&#xA;  R - Reads interrupt mode.&#xA;  W - Sets interrupt mode, where 0 is normal mode and 1 is fast mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="6"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="ILR">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Level Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x24"/>
              <PROPERTY NAME="SIZE" VALUE="5"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="ILN">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Level Number.&#xA;  R - Reads ordinal of highest priority interrupt not allowed to generate IRQ.&#xA;  W - Writes ordinal of highest priority interrupt not allowed to generate IRQ.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="5"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[0]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 0"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x100"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 0 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[1]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 1"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x104"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 1 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[2]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 2"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x108"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 2 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[3]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 3"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x10C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 3 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[4]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 4"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x110"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 4 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[5]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 5"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x114"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 5 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[6]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 6"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x118"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 6 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[7]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 7"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x11C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 7 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[8]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 8"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x120"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 8 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[9]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 9"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x124"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 9 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[10]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 10"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x128"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 10 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[11]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 11"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x12C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 11 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[12]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 12"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x130"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 12 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[13]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 13"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x134"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 13 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[14]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 14"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x138"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 14 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[15]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 15"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x13C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 15 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[16]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 16"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x140"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 16 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[17]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 17"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x144"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 17 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[18]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 18"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x148"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 18 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[19]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 19"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x14C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 19 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[20]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 20"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x150"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 20 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[21]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 21"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x154"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 21 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[22]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 22"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x158"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 22 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[23]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 23"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x15C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 23 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[24]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 24"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x160"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 24 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[25]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 25"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x164"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 25 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[26]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 26"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x168"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 26 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[27]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 27"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x16C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 27 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[28]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 28"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x170"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 28 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[29]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 29"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x174"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 29 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[30]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 30"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x178"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 30 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVAR[31]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 31"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x17C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 31 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[0]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 0"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x200"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 0 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[1]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 1"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x208"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 1 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[2]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 2"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x210"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 2 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[3]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 3"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x218"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 3 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[4]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 4"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x220"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 4 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[5]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 5"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x228"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 5 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[6]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 6"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x230"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 6 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[7]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 7"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x238"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 7 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[8]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 8"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x240"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 8 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[9]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 9"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x248"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 9 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[10]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 10"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x250"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 10 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[11]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 11"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x258"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 11 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[12]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 12"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x260"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 12 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[13]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 13"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x268"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 13 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[14]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 14"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x270"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 14 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[15]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 15"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x278"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 15 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[16]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 16"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x280"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 16 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[17]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 17"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x288"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 17 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[18]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 18"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x290"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 18 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[19]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 19"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x298"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 19 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[20]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 20"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2A0"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 20 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[21]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 21"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2A8"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 21 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[22]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 22"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2B0"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 22 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[23]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 23"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2B8"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 23 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[24]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 24"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2C0"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 24 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[25]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 25"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2C8"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 25 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[26]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 26"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2D0"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 26 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[27]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 27"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2D8"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 27 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[28]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 28"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2E0"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 28 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[29]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 29"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2E8"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 29 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[30]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 30"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2F0"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 30 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IVEAR[31]">
              <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt Vector Address Register 31"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x2F8"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x00000000000000010"/>
              <FIELDS>
                <FIELD NAME="IVA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Interrupt vector address of active interrupt 31 with highest priority.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
          </REGISTERS>
        </ADDRESSBLOCK>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_INSTANCE" VALUE="d_1_axi_intc_0_0"/>
        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="9"/>
        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_NUM_INTR_INPUTS" VALUE="6"/>
        <PARAMETER NAME="C_NUM_SW_INTR" VALUE="0"/>
        <PARAMETER NAME="C_KIND_OF_INTR" VALUE="0xffffffc0"/>
        <PARAMETER NAME="C_KIND_OF_EDGE" VALUE="0xFFFFFFFF"/>
        <PARAMETER NAME="C_KIND_OF_LVL" VALUE="0xFFFFFFFF"/>
        <PARAMETER NAME="C_ASYNC_INTR" VALUE="0xFFFFFFC0"/>
        <PARAMETER NAME="C_NUM_SYNC_FF" VALUE="2"/>
        <PARAMETER NAME="C_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_IVAR_RESET_VALUE" VALUE="0x0000000000000010"/>
        <PARAMETER NAME="C_ENABLE_ASYNC" VALUE="0"/>
        <PARAMETER NAME="C_HAS_IPR" VALUE="1"/>
        <PARAMETER NAME="C_HAS_SIE" VALUE="1"/>
        <PARAMETER NAME="C_HAS_CIE" VALUE="1"/>
        <PARAMETER NAME="C_HAS_IVR" VALUE="1"/>
        <PARAMETER NAME="C_HAS_ILR" VALUE="0"/>
        <PARAMETER NAME="C_IRQ_IS_LEVEL" VALUE="1"/>
        <PARAMETER NAME="C_IRQ_ACTIVE" VALUE="0x1"/>
        <PARAMETER NAME="C_DISABLE_SYNCHRONIZERS" VALUE="0"/>
        <PARAMETER NAME="C_MB_CLK_NOT_CONNECTED" VALUE="1"/>
        <PARAMETER NAME="C_HAS_FAST" VALUE="0"/>
        <PARAMETER NAME="C_EN_CASCADE_MODE" VALUE="0"/>
        <PARAMETER NAME="C_CASCADE_MASTER" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axi_intc_0_0"/>
        <PARAMETER NAME="Sense_of_IRQ_Level_Type" VALUE="Active_High"/>
        <PARAMETER NAME="Sense_of_IRQ_Edge_Type" VALUE="Rising"/>
        <PARAMETER NAME="C_S_AXI_ACLK_FREQ_MHZ" VALUE="99.999001"/>
        <PARAMETER NAME="C_PROCESSOR_CLK_FREQ_MHZ" VALUE="100.0"/>
        <PARAMETER NAME="C_IRQ_CONNECTION" VALUE="1"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="EDK_SPECIAL" VALUE="INTR_CTRL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0253000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0253FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="8" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="8" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="intr" RIGHT="0" SENSITIVITY="LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH:LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="xlconcat_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="xlconcat_0" PORT="dout"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="irq" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_intc_0_irq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_ps_irq0"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M26_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="9"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE BD="d_1_axi_smc_0" BDTYPE="SBD" COREREVISION="18" DRIVERMODE="CORE" FULLNAME="/axi_smc" HWVERSION="1.0" INSTANCE="axi_smc" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="smartconnect" SIM_BD="d_1_axi_smc_0" VLNV="xilinx.com:ip:smartconnect:1.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=smartconnect;v=v1_0;d=pg247-smartconnect.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="TLM_COMPONENT_NAME" VALUE="d_1_axi_smc_0"/>
        <PARAMETER NAME="HAS_RESET" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axi_smc_0"/>
        <PARAMETER NAME="NUM_MI" VALUE="1"/>
        <PARAMETER NAME="NUM_SI" VALUE="6"/>
        <PARAMETER NAME="NUM_CLKS" VALUE="1"/>
        <PARAMETER NAME="HAS_ARESETN" VALUE="1"/>
        <PARAMETER NAME="ADVANCED_PROPERTIES" VALUE="0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_mm2s_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_mm2s_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_mm2s_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_mm2s_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_mm2s_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_mm2s_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_mm2s_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_mm2s_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="255" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_mm2s_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_mm2s_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_mm2s_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_mm2s_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_mm2s_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_mm2s_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S01_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S01_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S01_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="S01_AXI_awlock" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="3" NAME="S01_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S01_AXI_awqos" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="S01_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S01_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="255" NAME="S01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S01_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S01_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S01_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S01_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S01_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axi_s2mm_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="48" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="48" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxigp0_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S02_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axi_mm2s_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S02_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axi_mm2s_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S02_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axi_mm2s_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S02_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axi_mm2s_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="S02_AXI_arlock" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="3" NAME="S02_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axi_mm2s_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S02_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axi_mm2s_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S02_AXI_arqos" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="S02_AXI_arvalid" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axi_mm2s_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S02_AXI_arready" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axi_mm2s_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="S02_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axi_mm2s_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S02_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axi_mm2s_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S02_AXI_rlast" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axi_mm2s_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S02_AXI_rvalid" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axi_mm2s_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S02_AXI_rready" SIGIS="undef" SIGNAME="axi_dma_gen_m_axi_mm2s_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axi_mm2s_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S03_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S03_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S03_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S03_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="S03_AXI_awlock" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="3" NAME="S03_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S03_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S03_AXI_awqos" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="S03_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S03_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="63" NAME="S03_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S03_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S03_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S03_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S03_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S03_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S03_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S03_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_avg_m_axi_s2mm_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S04_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S04_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S04_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S04_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="S04_AXI_awlock" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="3" NAME="S04_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S04_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S04_AXI_awqos" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="S04_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S04_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S04_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S04_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S04_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S04_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S04_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S04_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S04_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S04_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_buf_m_axi_s2mm_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S05_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S05_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S05_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S05_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="S05_AXI_awlock" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="3" NAME="S05_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S05_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S05_AXI_awqos" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="S05_AXI_awvalid" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S05_AXI_awready" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S05_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S05_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S05_AXI_wlast" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S05_AXI_wvalid" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S05_AXI_wready" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S05_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S05_AXI_bvalid" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S05_AXI_bready" SIGIS="undef" SIGNAME="axi_dma_mr_m_axi_s2mm_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_bready"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi_dma_tproc_M_AXI_MM2S" DATAWIDTH="256" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="256"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_ONLY"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="0"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="2"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="S00_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S00_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="S00_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_dma_tproc_M_AXI_S2MM" DATAWIDTH="256" NAME="S01_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="256"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="WRITE_ONLY"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S01_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S01_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S01_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S01_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S01_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S01_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S01_AXI_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S01_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S01_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S01_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="S01_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S01_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="S01_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="S01_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="S01_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="S01_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="S01_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="S01_AXI_bready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_dma_gen_M_AXI_MM2S" DATAWIDTH="32" NAME="S02_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_ONLY"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="0"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S02_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="S02_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S02_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="S02_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S02_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S02_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="S02_AXI_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="S02_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S02_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S02_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="S02_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="S02_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="S02_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="S02_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="S02_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_dma_avg_M_AXI_S2MM" DATAWIDTH="64" NAME="S03_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="64"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="WRITE_ONLY"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S03_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S03_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S03_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S03_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S03_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S03_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S03_AXI_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S03_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S03_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S03_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="S03_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S03_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="S03_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="S03_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="S03_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="S03_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="S03_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="S03_AXI_bready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_dma_buf_M_AXI_S2MM" DATAWIDTH="32" NAME="S04_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="WRITE_ONLY"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S04_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S04_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S04_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S04_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S04_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S04_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S04_AXI_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S04_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S04_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S04_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="S04_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S04_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="S04_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="S04_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="S04_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="S04_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="S04_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="S04_AXI_bready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_dma_mr_M_AXI_S2MM" DATAWIDTH="32" NAME="S05_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="WRITE_ONLY"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="0"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="16"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S05_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S05_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S05_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S05_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S05_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S05_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S05_AXI_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S05_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S05_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S05_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="S05_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S05_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="S05_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="S05_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="S05_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="S05_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="S05_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="S05_AXI_bready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_smc_M00_AXI" DATAWIDTH="128" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="49"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="32"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M00_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M00_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M00_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M00_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M00_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M00_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M00_AXI_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M00_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M00_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M00_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M00_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M00_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M00_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M00_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M00_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M00_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M00_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M00_AXI_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M00_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M00_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE BD="d_1_axi_smc_1_0" BDTYPE="SBD" COREREVISION="18" DRIVERMODE="CORE" FULLNAME="/axi_smc_1" HWVERSION="1.0" INSTANCE="axi_smc_1" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="smartconnect" SIM_BD="d_1_axi_smc_1_0" VLNV="xilinx.com:ip:smartconnect:1.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=smartconnect;v=v1_0;d=pg247-smartconnect.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="TLM_COMPONENT_NAME" VALUE="d_1_axi_smc_1_0"/>
        <PARAMETER NAME="HAS_RESET" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axi_smc_1_0"/>
        <PARAMETER NAME="NUM_MI" VALUE="1"/>
        <PARAMETER NAME="NUM_SI" VALUE="2"/>
        <PARAMETER NAME="NUM_CLKS" VALUE="1"/>
        <PARAMETER NAME="HAS_ARESETN" VALUE="1"/>
        <PARAMETER NAME="ADVANCED_PROPERTIES" VALUE="0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="333250000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="ddr4_0_c0_ddr4_ui_clk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_ui_clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_ddr4_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ddr4" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="S00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="39" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="S00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="S00_AXI_awuser" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awuser">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_awuser"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="S00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_bid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_arid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="39" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="S00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="S00_AXI_aruser" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_aruser">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_aruser"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="S00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_rid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp1_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="S01_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S01_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S01_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S01_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="S01_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S01_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S01_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S01_AXI_awvalid" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S01_AXI_awready" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="511" NAME="S01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="63" NAME="S01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S01_AXI_wlast" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S01_AXI_wvalid" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S01_AXI_wready" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="S01_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_bid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S01_AXI_bvalid" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S01_AXI_bready" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="S01_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_arid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="S01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S01_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S01_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S01_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="S01_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S01_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S01_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S01_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S01_AXI_arvalid" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S01_AXI_arready" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="S01_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_rid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="511" NAME="S01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S01_AXI_rlast" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S01_AXI_rvalid" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S01_AXI_rready" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="m_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="M00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="M00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="M00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="M00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="M00_AXI_awuser" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_awvalid" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_AXI_awready" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="511" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="63" NAME="M00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_wvalid" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_AXI_wready" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_AXI_bvalid" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_bready" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="M00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="M00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="M00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="M00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="M00_AXI_aruser" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_arvalid" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_AXI_arready" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="511" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_AXI_rvalid" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_rready" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" DATAWIDTH="128" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="333250000"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="16"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="40"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="16"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="16"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
          <PARAMETER NAME="PHASE" VALUE="0.00"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_ddr4_0_0_c0_ddr4_ui_clk"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="4"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="4"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWID" PHYSICAL="S00_AXI_awid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S00_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S00_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S00_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S00_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S00_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S00_AXI_awqos"/>
            <PORTMAP LOGICAL="AWUSER" PHYSICAL="S00_AXI_awuser"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="S00_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S00_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="S00_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="S00_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="S00_AXI_wready"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="S00_AXI_bid"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="S00_AXI_arid"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="S00_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S00_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="S00_AXI_arqos"/>
            <PORTMAP LOGICAL="ARUSER" PHYSICAL="S00_AXI_aruser"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="S00_AXI_rid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_buffer_ddr_v1_0_m_axi" DATAWIDTH="512" NAME="S01_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="512"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="333250000"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="1"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
          <PARAMETER NAME="PHASE" VALUE="0.00"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_ddr4_0_0_c0_ddr4_ui_clk"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWID" PHYSICAL="S01_AXI_awid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S01_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S01_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S01_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S01_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S01_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S01_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S01_AXI_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S01_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S01_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S01_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="S01_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S01_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="S01_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="S01_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="S01_AXI_wready"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="S01_AXI_bid"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="S01_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="S01_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="S01_AXI_bready"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="S01_AXI_arid"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S01_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="S01_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S01_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="S01_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S01_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S01_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="S01_AXI_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="S01_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S01_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S01_AXI_arready"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="S01_AXI_rid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="S01_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="S01_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="S01_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="S01_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="S01_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_smc_1_M00_AXI" DATAWIDTH="512" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="512"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="333250000"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="16"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="16"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
          <PARAMETER NAME="PHASE" VALUE="0.00"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_ddr4_0_0_c0_ddr4_ui_clk"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M00_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M00_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M00_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M00_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M00_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M00_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M00_AXI_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M00_AXI_awqos"/>
            <PORTMAP LOGICAL="AWUSER" PHYSICAL="M00_AXI_awuser"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M00_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M00_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M00_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M00_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M00_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M00_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M00_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M00_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M00_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M00_AXI_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M00_AXI_arqos"/>
            <PORTMAP LOGICAL="ARUSER" PHYSICAL="M00_AXI_aruser"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M00_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="6" FULLNAME="/axis_avg_buffer_0" HWVERSION="1.0" INSTANCE="axis_avg_buffer_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_avg_buffer" VLNV="user.org:user:axis_avg_buffer:1.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="64" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="N_AVG" VALUE="14"/>
        <PARAMETER NAME="N_BUF" VALUE="10"/>
        <PARAMETER NAME="B" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_avg_buffer_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0244000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0244FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="trigger" SIGIS="undef" SIGNAME="qick_vec2bit_1_dout0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_vec2bit_1" PORT="dout0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="512000000" DIR="I" NAME="s_axis_aclk" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_adc0_x2_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_broadcaster_0" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_broadcaster_0" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="m_axis_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m0_axis_tvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_0_m0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m0_axis_tready" SIGIS="undef" SIGNAME="axis_avg_buffer_0_m0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="63" NAME="m0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_m0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m0_axis_tlast" SIGIS="undef" SIGNAME="axis_avg_buffer_0_m0_axis_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axis_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m1_axis_tvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_0_m1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m1_axis_tready" SIGIS="undef" SIGNAME="axis_avg_buffer_0_m1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_m1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m1_axis_tlast" SIGIS="undef" SIGNAME="axis_avg_buffer_0_m1_axis_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axis_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m2_axis_tvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_0_m2_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_0" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m2_axis_tready" SIGIS="undef" SIGNAME="axis_avg_buffer_0_m2_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_0" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="63" NAME="m2_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_m2_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_avg_buffer_0_m0_axis" NAME="m0_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m0_axis_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m0_axis_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m0_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m0_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_avg_buffer_0_m1_axis" NAME="m1_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m1_axis_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m1_axis_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m1_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m1_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_broadcaster_0_M00_AXIS" NAME="s_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M09_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_avg_buffer_0_m2_axis" NAME="m2_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m2_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m2_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m2_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="6" FULLNAME="/axis_avg_buffer_1" HWVERSION="1.0" INSTANCE="axis_avg_buffer_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_avg_buffer" VLNV="user.org:user:axis_avg_buffer:1.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="64" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="N_AVG" VALUE="14"/>
        <PARAMETER NAME="N_BUF" VALUE="10"/>
        <PARAMETER NAME="B" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_avg_buffer_1_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0245000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0245FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="trigger" SIGIS="undef" SIGNAME="qick_vec2bit_1_dout1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_vec2bit_1" PORT="dout1"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="512000000" DIR="I" NAME="s_axis_aclk" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_adc0_x2_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_broadcaster_1" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_broadcaster_1" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="m_axis_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m0_axis_tvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m0_axis_tready" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="63" NAME="m0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m0_axis_tlast" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m0_axis_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axis_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m1_axis_tvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m1_axis_tready" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m1_axis_tlast" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m1_axis_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axis_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m2_axis_tvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m2_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_1" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m2_axis_tready" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m2_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_1" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="63" NAME="m2_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m2_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_1" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_avg_buffer_1_m0_axis" NAME="m0_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m0_axis_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m0_axis_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m0_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m0_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_avg_buffer_1_m1_axis" NAME="m1_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m1_axis_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m1_axis_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m1_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m1_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_broadcaster_1_M00_AXIS" NAME="s_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M10_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_avg_buffer_1_m2_axis" NAME="m2_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m2_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m2_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m2_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="25" FULLNAME="/axis_broadcaster_0" HWVERSION="1.1" INSTANCE="axis_broadcaster_0" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axis_broadcaster" VLNV="xilinx.com:ip:axis_broadcaster:1.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_broadcaster;v=v1_1;d=pg085-axi4stream-infrastructure.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_NUM_MI_SLOTS" VALUE="2"/>
        <PARAMETER NAME="C_S_AXIS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_S_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_M_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000000010"/>
        <PARAMETER NAME="NUM_MI" VALUE="2"/>
        <PARAMETER NAME="M_TDATA_NUM_BYTES" VALUE="4"/>
        <PARAMETER NAME="S_TDATA_NUM_BYTES" VALUE="4"/>
        <PARAMETER NAME="HAS_SPLITTER" VALUE="0"/>
        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="M_TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="S_TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
        <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="M00_TDATA_REMAP" VALUE="tdata[31:0]"/>
        <PARAMETER NAME="M01_TDATA_REMAP" VALUE="tdata[31:0]"/>
        <PARAMETER NAME="M02_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M03_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M04_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M05_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M06_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M07_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M08_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M09_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M10_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M11_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M12_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M13_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M14_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M15_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M16_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M00_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M01_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M02_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M03_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M04_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M05_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M06_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M07_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M08_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M09_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M10_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M11_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M12_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M13_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M14_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M15_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M16_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_broadcaster_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="512000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_adc0_x2_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_broadcaster_0_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="m1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_broadcaster_0_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="m1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="m_axis_tvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_broadcaster_0_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="63" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_broadcaster_0_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_readout_v2_0_m1_axis" NAME="S_AXIS" TYPE="SLAVE" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_broadcaster_0_M00_AXIS" NAME="M00_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_broadcaster_0_M01_AXIS" NAME="M01_AXIS" TYPE="MASTER" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="25" FULLNAME="/axis_broadcaster_1" HWVERSION="1.1" INSTANCE="axis_broadcaster_1" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axis_broadcaster" VLNV="xilinx.com:ip:axis_broadcaster:1.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_broadcaster;v=v1_1;d=pg085-axi4stream-infrastructure.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_NUM_MI_SLOTS" VALUE="2"/>
        <PARAMETER NAME="C_S_AXIS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_S_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_M_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000000010"/>
        <PARAMETER NAME="NUM_MI" VALUE="2"/>
        <PARAMETER NAME="M_TDATA_NUM_BYTES" VALUE="4"/>
        <PARAMETER NAME="S_TDATA_NUM_BYTES" VALUE="4"/>
        <PARAMETER NAME="HAS_SPLITTER" VALUE="0"/>
        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="M_TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="S_TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
        <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="M00_TDATA_REMAP" VALUE="tdata[31:0]"/>
        <PARAMETER NAME="M01_TDATA_REMAP" VALUE="tdata[31:0]"/>
        <PARAMETER NAME="M02_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M03_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M04_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M05_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M06_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M07_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M08_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M09_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M10_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M11_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M12_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M13_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M14_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M15_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M16_TDATA_REMAP" VALUE="TDATA[7:0]"/>
        <PARAMETER NAME="M00_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M01_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M02_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M03_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M04_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M05_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M06_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M07_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M08_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M09_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M10_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M11_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M12_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M13_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M14_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M15_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="M16_TUSER_REMAP" VALUE="1'b0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_broadcaster_1_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="512000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_adc0_x2_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_broadcaster_1_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="m1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_broadcaster_1_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="m1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="m_axis_tvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_broadcaster_1_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="63" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_broadcaster_1_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axis_tdata"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_readout_v2_1_m1_axis" NAME="S_AXIS" TYPE="SLAVE" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_broadcaster_1_M00_AXIS" NAME="M00_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_broadcaster_1_M01_AXIS" NAME="M01_AXIS" TYPE="MASTER" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="3" FULLNAME="/axis_buffer_ddr_v1_0" HWVERSION="1.0" INSTANCE="axis_buffer_ddr_v1_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_buffer_ddr_v1" VLNV="user.org:user:axis_buffer_ddr_v1:1.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="0x1000" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="TARGET_SLAVE_BASE_ADDR" VALUE="0x00000000"/>
        <PARAMETER NAME="ID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="DATA_WIDTH" VALUE="512"/>
        <PARAMETER NAME="BURST_SIZE" VALUE="15"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_buffer_ddr_v1_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0254000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0254FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="trigger" SIGIS="undef" SIGNAME="qick_vec2bit_1_dout2">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_vec2bit_1" PORT="dout2"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="333250000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="ddr4_0_c0_ddr4_ui_clk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_ui_clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_ddr4_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ddr4" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="m_axi_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="m_axi_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="m_axi_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_awlock" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m_axi_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m_axi_awregion" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="3" NAME="m_axi_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_awvalid" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_awready" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="511" NAME="m_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="63" NAME="m_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_wlast" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_wvalid" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_wready" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="m_axi_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_bid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="m_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_bvalid" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_bready" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="m_axi_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_arid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="m_axi_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="m_axi_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_arlock" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m_axi_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="m_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m_axi_arregion" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="3" NAME="m_axi_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_arvalid" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_arready" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="m_axi_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_rid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="511" NAME="m_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="m_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_rlast" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axi_rvalid" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axi_rready" SIGIS="undef" SIGNAME="axi_smc_1_S01_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S01_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef"/>
        <PORT DIR="O" LEFT="511" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="63" NAME="m_axis_tstrb" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="m_axis_tlast" SIGIS="undef"/>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clock_converter_0" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="511" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clock_converter_0" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="63" NAME="s_axis_tstrb" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="s_axis_tlast" SIGIS="undef"/>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clock_converter_0" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="m_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="64"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="333250000"/>
          <PARAMETER NAME="PHASE" VALUE="0.00"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_ddr4_0_0_c0_ddr4_ui_clk"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TSTRB" PHYSICAL="m_axis_tstrb"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_clock_converter_0_M_AXIS" NAME="s_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="64"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="333250000"/>
          <PARAMETER NAME="PHASE" VALUE="0.00"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_ddr4_0_0_c0_ddr4_ui_clk"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TSTRB" PHYSICAL="s_axis_tstrb"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="s_axis_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_buffer_ddr_v1_0_m_axi" DATAWIDTH="512" NAME="m_axi" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="512"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="333250000"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="1"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="1"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
          <PARAMETER NAME="PHASE" VALUE="0.00"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_ddr4_0_0_c0_ddr4_ui_clk"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWID" PHYSICAL="m_axi_awid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="m_axi_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="m_axi_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="m_axi_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="m_axi_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="m_axi_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="m_axi_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="m_axi_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="m_axi_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="m_axi_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="m_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="m_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="m_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="m_axi_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="m_axi_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="m_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="m_axi_wready"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="m_axi_bid"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="m_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="m_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="m_axi_bready"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="m_axi_arid"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="m_axi_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="m_axi_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="m_axi_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="m_axi_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="m_axi_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="m_axi_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="m_axi_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="m_axi_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="m_axi_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="m_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="m_axi_arready"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="m_axi_rid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="m_axi_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="m_axi_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="m_axi_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="m_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="m_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M21_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="8"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE ADDRESSBLOCK="C0_DDR4_ADDRESS_BLOCK" BASENAME="C_BASEADDR" BASEVALUE="0x00000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xFFFFFFFF" INSTANCE="ddr4_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="m_axi" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="C0_DDR4_S_AXI"/>
      </MEMORYMAP>
      <PERIPHERALS>
        <PERIPHERAL INSTANCE="ddr4_0"/>
      </PERIPHERALS>
    </MODULE>
    <MODULE COREREVISION="3" FULLNAME="/axis_cdcsync_v1_0" HWVERSION="1.0" INSTANCE="axis_cdcsync_v1_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_cdcsync_v1" VLNV="user.org:user:axis_cdcsync_v1:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="N" VALUE="4"/>
        <PARAMETER NAME="B" VALUE="168"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_cdcsync_v1_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="s_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="s_axis_aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s0_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m0_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m0_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m0_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s1_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m1_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s1_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s2_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s2_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m2_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s2_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s2_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m2_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s2_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s2_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m2_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s3_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s3_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m3_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s3_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s3_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m3_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s3_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s3_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m3_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="m_axis_aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m0_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_0" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m1_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_1" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_1" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m2_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m2_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_2" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m2_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m2_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_2" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m3_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m3_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_3" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m3_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m3_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_3" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_0_m0_axis" NAME="m0_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m0_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m0_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_0_m1_axis" NAME="m1_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m1_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m1_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_0_m2_axis" NAME="m2_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m2_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m2_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_0_m3_axis" NAME="m3_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m3_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m3_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m0_axis" NAME="s0_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s0_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s0_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s0_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m1_axis" NAME="s1_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s1_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s1_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s1_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m2_axis" NAME="s2_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s2_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s2_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s2_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m3_axis" NAME="s3_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s3_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s3_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s3_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="3" FULLNAME="/axis_cdcsync_v1_1" HWVERSION="1.0" INSTANCE="axis_cdcsync_v1_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_cdcsync_v1" VLNV="user.org:user:axis_cdcsync_v1:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="N" VALUE="4"/>
        <PARAMETER NAME="B" VALUE="168"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_cdcsync_v1_1_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="s_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="s_axis_aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s0_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m4_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m4_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m4_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s1_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m5_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s1_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m5_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m5_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s2_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s2_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m6_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s2_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s2_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m6_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s2_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s2_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m6_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s3_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s3_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m7_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s3_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s3_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m7_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s3_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s3_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="m7_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac1_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac1" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="m_axis_aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m0_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_4" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_4" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m1_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_5" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_5" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m2_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m2_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_6" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m2_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m2_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_6" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m3_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m3_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_7" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m3_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m3_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_7" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_1_m0_axis" NAME="m0_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m0_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m0_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_1_m1_axis" NAME="m1_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m1_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m1_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_1_m2_axis" NAME="m2_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m2_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m2_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_1_m3_axis" NAME="m3_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m3_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m3_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m4_axis" NAME="s0_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s0_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s0_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s0_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m5_axis" NAME="s1_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s1_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s1_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s1_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m6_axis" NAME="s2_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s2_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s2_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s2_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m7_axis" NAME="s3_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s3_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s3_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s3_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="27" FULLNAME="/axis_clk_cnvrt_avg_0" HWVERSION="1.1" INSTANCE="axis_clk_cnvrt_avg_0" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axis_clock_converter" VLNV="xilinx.com:ip:axis_clock_converter:1.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_clock_converter;v=v1_1;d=pg085-axi4stream-infrastructure.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000000011"/>
        <PARAMETER NAME="C_IS_ACLK_ASYNC" VALUE="1"/>
        <PARAMETER NAME="C_SYNCHRONIZER_STAGE" VALUE="2"/>
        <PARAMETER NAME="C_S_AXIS_ACLK_RATIO" VALUE="1"/>
        <PARAMETER NAME="C_M_AXIS_ACLK_RATIO" VALUE="2"/>
        <PARAMETER NAME="C_ACLKEN_CONV_MODE" VALUE="0"/>
        <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="IS_ACLK_ASYNC" VALUE="1"/>
        <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
        <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="2"/>
        <PARAMETER NAME="ACLK_RATIO" VALUE="1:2"/>
        <PARAMETER NAME="ACLKEN_CONV_MODE" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_clk_cnvrt_avg_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="s_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_core_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_core" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axis_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_0_m2_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="m2_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef" SIGNAME="axis_avg_buffer_0_m2_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="m2_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="63" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_m2_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="m2_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="199998000" DIR="I" NAME="m_axis_aclk" SIGIS="clk" SIGNAME="clk_core_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_core" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="axis_clk_cnvrt_avg_0_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s0_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="63" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_clk_cnvrt_avg_0_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s0_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_avg_buffer_0_m2_axis" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_clk_cnvrt_avg_0_M_AXIS" NAME="M_AXIS" TYPE="MASTER" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="199998000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_1_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="27" FULLNAME="/axis_clk_cnvrt_avg_1" HWVERSION="1.1" INSTANCE="axis_clk_cnvrt_avg_1" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axis_clock_converter" VLNV="xilinx.com:ip:axis_clock_converter:1.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_clock_converter;v=v1_1;d=pg085-axi4stream-infrastructure.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000000011"/>
        <PARAMETER NAME="C_IS_ACLK_ASYNC" VALUE="1"/>
        <PARAMETER NAME="C_SYNCHRONIZER_STAGE" VALUE="2"/>
        <PARAMETER NAME="C_S_AXIS_ACLK_RATIO" VALUE="1"/>
        <PARAMETER NAME="C_M_AXIS_ACLK_RATIO" VALUE="2"/>
        <PARAMETER NAME="C_ACLKEN_CONV_MODE" VALUE="0"/>
        <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="IS_ACLK_ASYNC" VALUE="1"/>
        <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
        <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="2"/>
        <PARAMETER NAME="ACLK_RATIO" VALUE="1:2"/>
        <PARAMETER NAME="ACLKEN_CONV_MODE" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_clk_cnvrt_avg_1_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="s_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_core_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_core" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axis_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m2_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="m2_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m2_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="m2_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="63" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m2_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="m2_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="199998000" DIR="I" NAME="m_axis_aclk" SIGIS="clk" SIGNAME="clk_core_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_core" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="axis_clk_cnvrt_avg_1_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="63" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_clk_cnvrt_avg_1_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_avg_buffer_1_m2_axis" NAME="S_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_clk_cnvrt_avg_1_M_AXIS" NAME="M_AXIS" TYPE="MASTER" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="199998000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_1_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="27" FULLNAME="/axis_clock_converter_0" HWVERSION="1.1" INSTANCE="axis_clock_converter_0" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axis_clock_converter" VLNV="xilinx.com:ip:axis_clock_converter:1.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_clock_converter;v=v1_1;d=pg085-axi4stream-infrastructure.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="512"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000000011"/>
        <PARAMETER NAME="C_IS_ACLK_ASYNC" VALUE="1"/>
        <PARAMETER NAME="C_SYNCHRONIZER_STAGE" VALUE="2"/>
        <PARAMETER NAME="C_S_AXIS_ACLK_RATIO" VALUE="1"/>
        <PARAMETER NAME="C_M_AXIS_ACLK_RATIO" VALUE="2"/>
        <PARAMETER NAME="C_ACLKEN_CONV_MODE" VALUE="0"/>
        <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="64"/>
        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="IS_ACLK_ASYNC" VALUE="1"/>
        <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
        <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="2"/>
        <PARAMETER NAME="ACLK_RATIO" VALUE="1:2"/>
        <PARAMETER NAME="ACLKEN_CONV_MODE" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_clock_converter_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="s_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_adc0_x2_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_ddr4_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ddr4" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="512000000" DIR="I" NAME="s_axis_aclk" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_clock_converter_0_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_dwidth_converter_0" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef" SIGNAME="axis_clock_converter_0_s_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_dwidth_converter_0" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="511" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_clock_converter_0_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_dwidth_converter_0" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="333250000" DIR="I" NAME="m_axis_aclk" SIGIS="clk" SIGNAME="ddr4_0_c0_ddr4_ui_clk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_ui_clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="511" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_dwidth_converter_0_M_AXIS" NAME="S_AXIS" TYPE="SLAVE" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="64"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_clock_converter_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="64"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="333250000"/>
          <PARAMETER NAME="PHASE" VALUE="0.00"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_ddr4_0_0_c0_ddr4_ui_clk"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="25" FULLNAME="/axis_dwidth_converter_0" HWVERSION="1.1" INSTANCE="axis_dwidth_converter_0" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axis_dwidth_converter" VLNV="xilinx.com:ip:axis_dwidth_converter:1.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_dwidth_converter;v=v1_1;d=pg085-axi4stream-infrastructure.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_S_AXIS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_M_AXIS_TDATA_WIDTH" VALUE="512"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_S_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_M_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000000011"/>
        <PARAMETER NAME="S_TDATA_NUM_BYTES" VALUE="4"/>
        <PARAMETER NAME="M_TDATA_NUM_BYTES" VALUE="64"/>
        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TUSER_BITS_PER_BYTE" VALUE="0"/>
        <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
        <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
        <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="HAS_MI_TKEEP" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_dwidth_converter_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="512000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_adc0_x2_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_dwidth_converter_0_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_dwidth_converter_0_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="axis_clock_converter_0_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clock_converter_0" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="axis_clock_converter_0_s_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clock_converter_0" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="511" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_clock_converter_0_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clock_converter_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_switch_ddr_M00_AXIS" NAME="S_AXIS" TYPE="SLAVE" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_dwidth_converter_0_M_AXIS" NAME="M_AXIS" TYPE="MASTER" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="64"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="8" FULLNAME="/axis_readout_v2_0" HWVERSION="1.0" INSTANCE="axis_readout_v2_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_readout_v2" VLNV="user.org:user:axis_readout_v2:1.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="64" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_readout_v2_0_0"/>
        <PARAMETER NAME="FULLSPEED_OUTPUT" VALUE="true"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0246000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0246FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_adc0_x2_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="512000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_register_slice_0" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_register_slice_0" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_register_slice_0" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m0_axis_tready" SIGIS="undef" SIGNAME="axis_readout_v2_0_m0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m0_axis_tvalid" SIGIS="undef" SIGNAME="axis_readout_v2_0_m0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="255" NAME="m0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_m0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m1_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" NAME="m1_axis_tvalid" SIGIS="undef" SIGNAME="axis_broadcaster_0_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_broadcaster_0" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_broadcaster_0_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_broadcaster_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_readout_v2_0_m0_axis" NAME="m0_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m0_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m0_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m0_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_readout_v2_0_m1_axis" NAME="m1_axis" TYPE="MASTER" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m1_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m1_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m1_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_register_slice_0_M_AXIS" NAME="s_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="16"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M15_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="8" FULLNAME="/axis_readout_v2_1" HWVERSION="1.0" INSTANCE="axis_readout_v2_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_readout_v2" VLNV="user.org:user:axis_readout_v2:1.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="64" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_readout_v2_1_0"/>
        <PARAMETER NAME="FULLSPEED_OUTPUT" VALUE="true"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0247000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0247FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_adc0_x2_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="512000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_register_slice_1" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_register_slice_1" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_register_slice_1" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m0_axis_tready" SIGIS="undef" SIGNAME="axis_readout_v2_1_m0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m0_axis_tvalid" SIGIS="undef" SIGNAME="axis_readout_v2_1_m0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="255" NAME="m0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_m0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m1_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" NAME="m1_axis_tvalid" SIGIS="undef" SIGNAME="axis_broadcaster_1_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_broadcaster_1" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_broadcaster_1_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_broadcaster_1" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_readout_v2_1_m0_axis" NAME="m0_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m0_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m0_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m0_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_readout_v2_1_m1_axis" NAME="m1_axis" TYPE="MASTER" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m1_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m1_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m1_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_register_slice_1_M_AXIS" NAME="s_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="16"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M16_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="26" FULLNAME="/axis_register_slice_0" HWVERSION="1.1" INSTANCE="axis_register_slice_0" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axis_register_slice" VLNV="xilinx.com:ip:axis_register_slice:1.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_register_slice;v=v1_1;d=pg085-axi4stream-infrastructure.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000000011"/>
        <PARAMETER NAME="C_REG_CONFIG" VALUE="1"/>
        <PARAMETER NAME="C_NUM_SLR_CROSSINGS" VALUE="0"/>
        <PARAMETER NAME="C_PIPELINES_MASTER" VALUE="0"/>
        <PARAMETER NAME="C_PIPELINES_SLAVE" VALUE="0"/>
        <PARAMETER NAME="C_PIPELINES_MIDDLE" VALUE="0"/>
        <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="16"/>
        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="REG_CONFIG" VALUE="1"/>
        <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
        <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="NUM_SLR_CROSSINGS" VALUE="0"/>
        <PARAMETER NAME="PIPELINES_MASTER" VALUE="0"/>
        <PARAMETER NAME="PIPELINES_MIDDLE" VALUE="0"/>
        <PARAMETER NAME="PIPELINES_SLAVE" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_register_slice_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="512000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_adc0_x2_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_register_slice_0_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="m00_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef" SIGNAME="axis_register_slice_0_s_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="m00_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_register_slice_0_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="m00_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_m00_axis" NAME="S_AXIS" TYPE="SLAVE" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="16"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_register_slice_0_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="16"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="26" FULLNAME="/axis_register_slice_1" HWVERSION="1.1" INSTANCE="axis_register_slice_1" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axis_register_slice" VLNV="xilinx.com:ip:axis_register_slice:1.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_register_slice;v=v1_1;d=pg085-axi4stream-infrastructure.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000000011"/>
        <PARAMETER NAME="C_REG_CONFIG" VALUE="1"/>
        <PARAMETER NAME="C_NUM_SLR_CROSSINGS" VALUE="0"/>
        <PARAMETER NAME="C_PIPELINES_MASTER" VALUE="0"/>
        <PARAMETER NAME="C_PIPELINES_SLAVE" VALUE="0"/>
        <PARAMETER NAME="C_PIPELINES_MIDDLE" VALUE="0"/>
        <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="16"/>
        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="REG_CONFIG" VALUE="1"/>
        <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
        <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="NUM_SLR_CROSSINGS" VALUE="0"/>
        <PARAMETER NAME="PIPELINES_MASTER" VALUE="0"/>
        <PARAMETER NAME="PIPELINES_MIDDLE" VALUE="0"/>
        <PARAMETER NAME="PIPELINES_SLAVE" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_register_slice_1_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="512000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_adc0_x2_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_register_slice_1_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="m02_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef" SIGNAME="axis_register_slice_1_s_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="m02_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_register_slice_1_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="m02_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_m02_axis" NAME="S_AXIS" TYPE="SLAVE" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="16"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_register_slice_1_M_AXIS" NAME="M_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="16"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="4" FULLNAME="/axis_signal_gen_v6_0" HWVERSION="1.0" INSTANCE="axis_signal_gen_v6_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_signal_gen_v6" VLNV="user.org:user:axis_signal_gen_v6:1.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="64" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="N" VALUE="12"/>
        <PARAMETER NAME="N_DDS" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_signal_gen_v6_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0248000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0248FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s0_axis_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s0_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="159" NAME="s1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_0" PORT="m_gen_v6_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s1_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_0" PORT="m_gen_v6_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s1_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_0" PORT="m_gen_v6_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s00_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s00_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="255" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s00_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_0_m_axis" NAME="m_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M00_AXIS" NAME="s0_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s0_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s0_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s0_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="sg_translator_0_m_gen_v6_axis" NAME="s1_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s1_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s1_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s1_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M02_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="4" FULLNAME="/axis_signal_gen_v6_1" HWVERSION="1.0" INSTANCE="axis_signal_gen_v6_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_signal_gen_v6" VLNV="user.org:user:axis_signal_gen_v6:1.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="64" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="N" VALUE="12"/>
        <PARAMETER NAME="N_DDS" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_signal_gen_v6_1_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0249000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0249FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s0_axis_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s0_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="159" NAME="s1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_1" PORT="m_gen_v6_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s1_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_1" PORT="m_gen_v6_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s1_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_1" PORT="m_gen_v6_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s01_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s01_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="255" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s01_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_1_m_axis" NAME="m_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M01_AXIS" NAME="s0_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s0_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s0_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s0_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="sg_translator_1_m_gen_v6_axis" NAME="s1_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s1_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s1_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s1_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M03_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="4" FULLNAME="/axis_signal_gen_v6_2" HWVERSION="1.0" INSTANCE="axis_signal_gen_v6_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_signal_gen_v6" VLNV="user.org:user:axis_signal_gen_v6:1.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="64" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="N" VALUE="11"/>
        <PARAMETER NAME="N_DDS" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_signal_gen_v6_2_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA024A000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA024AFFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s0_axis_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s0_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="159" NAME="s1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_2" PORT="m_gen_v6_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s1_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_2" PORT="m_gen_v6_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s1_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_2" PORT="m_gen_v6_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s02_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s02_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="255" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s02_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_2_m_axis" NAME="m_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M02_AXIS" NAME="s0_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s0_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s0_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s0_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="sg_translator_2_m_gen_v6_axis" NAME="s1_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s1_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s1_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s1_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M04_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="4" FULLNAME="/axis_signal_gen_v6_3" HWVERSION="1.0" INSTANCE="axis_signal_gen_v6_3" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_signal_gen_v6" VLNV="user.org:user:axis_signal_gen_v6:1.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="64" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="N" VALUE="11"/>
        <PARAMETER NAME="N_DDS" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_signal_gen_v6_3_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA024B000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA024BFFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s0_axis_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s0_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="159" NAME="s1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_3" PORT="m_gen_v6_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s1_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_3" PORT="m_gen_v6_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s1_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_3" PORT="m_gen_v6_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s03_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s03_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="255" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s03_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_3_m_axis" NAME="m_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M03_AXIS" NAME="s0_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s0_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s0_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s0_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="sg_translator_3_m_gen_v6_axis" NAME="s1_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s1_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s1_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s1_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M05_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="4" FULLNAME="/axis_signal_gen_v6_4" HWVERSION="1.0" INSTANCE="axis_signal_gen_v6_4" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_signal_gen_v6" VLNV="user.org:user:axis_signal_gen_v6:1.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="64" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="N" VALUE="12"/>
        <PARAMETER NAME="N_DDS" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_signal_gen_v6_4_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA024C000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA024CFFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s0_axis_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s0_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac1_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac1" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="159" NAME="s1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_4" PORT="m_gen_v6_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s1_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_4" PORT="m_gen_v6_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s1_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_4" PORT="m_gen_v6_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s10_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s10_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="255" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s10_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_4_m_axis" NAME="m_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M04_AXIS" NAME="s0_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s0_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s0_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s0_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="sg_translator_4_m_gen_v6_axis" NAME="s1_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s1_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s1_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s1_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M11_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="4" FULLNAME="/axis_signal_gen_v6_5" HWVERSION="1.0" INSTANCE="axis_signal_gen_v6_5" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_signal_gen_v6" VLNV="user.org:user:axis_signal_gen_v6:1.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="64" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="N" VALUE="12"/>
        <PARAMETER NAME="N_DDS" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_signal_gen_v6_5_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA024D000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA024DFFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s0_axis_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s0_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac1_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac1" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="159" NAME="s1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_5" PORT="m_gen_v6_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s1_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_5" PORT="m_gen_v6_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s1_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_5" PORT="m_gen_v6_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s11_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s11_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="255" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s11_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_5_m_axis" NAME="m_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M05_AXIS" NAME="s0_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s0_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s0_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s0_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="sg_translator_5_m_gen_v6_axis" NAME="s1_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s1_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s1_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s1_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M12_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="4" FULLNAME="/axis_signal_gen_v6_6" HWVERSION="1.0" INSTANCE="axis_signal_gen_v6_6" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_signal_gen_v6" VLNV="user.org:user:axis_signal_gen_v6:1.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="64" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="N" VALUE="11"/>
        <PARAMETER NAME="N_DDS" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_signal_gen_v6_6_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA024E000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA024EFFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s0_axis_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s0_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac1_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac1" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="159" NAME="s1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_6" PORT="m_gen_v6_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s1_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_6" PORT="m_gen_v6_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s1_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_6" PORT="m_gen_v6_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s12_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s12_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="255" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s12_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_6_m_axis" NAME="m_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M06_AXIS" NAME="s0_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s0_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s0_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s0_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="sg_translator_6_m_gen_v6_axis" NAME="s1_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s1_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s1_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s1_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M14_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="4" FULLNAME="/axis_signal_gen_v6_7" HWVERSION="1.0" INSTANCE="axis_signal_gen_v6_7" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_signal_gen_v6" VLNV="user.org:user:axis_signal_gen_v6:1.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="64" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="N" VALUE="11"/>
        <PARAMETER NAME="N_DDS" VALUE="16"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_signal_gen_v6_7_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA025C000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA025CFFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s0_axis_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s0_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac1_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac1" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="159" NAME="s1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_7" PORT="m_gen_v6_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s1_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_7" PORT="m_gen_v6_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s1_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="sg_translator_7" PORT="m_gen_v6_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s13_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s13_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="255" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s13_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_7_m_axis" NAME="m_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M07_AXIS" NAME="s0_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s0_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s0_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s0_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="sg_translator_7_m_gen_v6_axis" NAME="s1_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s1_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s1_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s1_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M13_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="26" FULLNAME="/axis_switch_avg" HWVERSION="1.1" INSTANCE="axis_switch_avg" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_switch" VLNV="xilinx.com:ip:axis_switch:1.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_switch;v=v1_1;d=pg085-axi4stream-infrastructure.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI_CTRL" NAME="Reg" RANGE="4096" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_NUM_SI_SLOTS" VALUE="2"/>
        <PARAMETER NAME="C_LOG_SI_SLOTS" VALUE="1"/>
        <PARAMETER NAME="C_NUM_MI_SLOTS" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="64"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000010011"/>
        <PARAMETER NAME="C_ARB_ON_MAX_XFERS" VALUE="1"/>
        <PARAMETER NAME="C_ARB_ON_NUM_CYCLES" VALUE="0"/>
        <PARAMETER NAME="C_ARB_ON_TLAST" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_ARBITER" VALUE="1"/>
        <PARAMETER NAME="C_ARB_ALGORITHM" VALUE="0"/>
        <PARAMETER NAME="C_OUTPUT_REG" VALUE="0"/>
        <PARAMETER NAME="C_DECODER_REG" VALUE="0"/>
        <PARAMETER NAME="C_M_AXIS_CONNECTIVITY_ARRAY" VALUE="&quot;11&quot;"/>
        <PARAMETER NAME="C_M_AXIS_BASETDEST_ARRAY" VALUE="0b0"/>
        <PARAMETER NAME="C_M_AXIS_HIGHTDEST_ARRAY" VALUE="0b0"/>
        <PARAMETER NAME="C_ROUTING_MODE" VALUE="1"/>
        <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="7"/>
        <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_COMMON_CLOCK" VALUE="0"/>
        <PARAMETER NAME="NUM_SI" VALUE="2"/>
        <PARAMETER NAME="NUM_MI" VALUE="1"/>
        <PARAMETER NAME="ROUTING_MODE" VALUE="1"/>
        <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
        <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
        <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="ARB_ON_MAX_XFERS" VALUE="1"/>
        <PARAMETER NAME="ARB_ON_NUM_CYCLES" VALUE="0"/>
        <PARAMETER NAME="ARB_ON_TLAST" VALUE="0"/>
        <PARAMETER NAME="ARB_ALGORITHM" VALUE="0"/>
        <PARAMETER NAME="DECODER_REG" VALUE="0"/>
        <PARAMETER NAME="OUTPUT_REG" VALUE="0"/>
        <PARAMETER NAME="COMMON_CLOCK" VALUE="0"/>
        <PARAMETER NAME="M00_AXIS_BASETDEST" VALUE="0x00000000"/>
        <PARAMETER NAME="M01_AXIS_BASETDEST" VALUE="0x00000001"/>
        <PARAMETER NAME="M02_AXIS_BASETDEST" VALUE="0x00000002"/>
        <PARAMETER NAME="M03_AXIS_BASETDEST" VALUE="0x00000003"/>
        <PARAMETER NAME="M04_AXIS_BASETDEST" VALUE="0x00000004"/>
        <PARAMETER NAME="M05_AXIS_BASETDEST" VALUE="0x00000005"/>
        <PARAMETER NAME="M06_AXIS_BASETDEST" VALUE="0x00000006"/>
        <PARAMETER NAME="M07_AXIS_BASETDEST" VALUE="0x00000007"/>
        <PARAMETER NAME="M08_AXIS_BASETDEST" VALUE="0x00000008"/>
        <PARAMETER NAME="M09_AXIS_BASETDEST" VALUE="0x00000009"/>
        <PARAMETER NAME="M10_AXIS_BASETDEST" VALUE="0x0000000a"/>
        <PARAMETER NAME="M11_AXIS_BASETDEST" VALUE="0x0000000b"/>
        <PARAMETER NAME="M12_AXIS_BASETDEST" VALUE="0x0000000c"/>
        <PARAMETER NAME="M13_AXIS_BASETDEST" VALUE="0x0000000d"/>
        <PARAMETER NAME="M14_AXIS_BASETDEST" VALUE="0x0000000e"/>
        <PARAMETER NAME="M15_AXIS_BASETDEST" VALUE="0x0000000f"/>
        <PARAMETER NAME="M00_AXIS_HIGHTDEST" VALUE="0x00000000"/>
        <PARAMETER NAME="M01_AXIS_HIGHTDEST" VALUE="0x00000001"/>
        <PARAMETER NAME="M02_AXIS_HIGHTDEST" VALUE="0x00000002"/>
        <PARAMETER NAME="M03_AXIS_HIGHTDEST" VALUE="0x00000003"/>
        <PARAMETER NAME="M04_AXIS_HIGHTDEST" VALUE="0x00000004"/>
        <PARAMETER NAME="M05_AXIS_HIGHTDEST" VALUE="0x00000005"/>
        <PARAMETER NAME="M06_AXIS_HIGHTDEST" VALUE="0x00000006"/>
        <PARAMETER NAME="M07_AXIS_HIGHTDEST" VALUE="0x00000007"/>
        <PARAMETER NAME="M08_AXIS_HIGHTDEST" VALUE="0x00000008"/>
        <PARAMETER NAME="M09_AXIS_HIGHTDEST" VALUE="0x00000009"/>
        <PARAMETER NAME="M10_AXIS_HIGHTDEST" VALUE="0x0000000a"/>
        <PARAMETER NAME="M11_AXIS_HIGHTDEST" VALUE="0x0000000b"/>
        <PARAMETER NAME="M12_AXIS_HIGHTDEST" VALUE="0x0000000c"/>
        <PARAMETER NAME="M13_AXIS_HIGHTDEST" VALUE="0x0000000d"/>
        <PARAMETER NAME="M14_AXIS_HIGHTDEST" VALUE="0x0000000e"/>
        <PARAMETER NAME="M15_AXIS_HIGHTDEST" VALUE="0x0000000f"/>
        <PARAMETER NAME="M00_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_switch_avg_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA024F000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA024FFFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="s_axis_tvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="m0_axis_tvalid"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="m0_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axis_tready" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="m0_axis_tready"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="m0_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="m0_axis_tdata"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="m0_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="s_axis_tlast" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m0_axis_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="m0_axis_tlast"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="m0_axis_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="m_axis_tvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axis_s2mm_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axis_s2mm_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="m_axis_tready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axis_s2mm_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axis_s2mm_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="63" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axis_s2mm_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axis_s2mm_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="m_axis_tlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axis_s2mm_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axis_s2mm_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_ctrl_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_awvalid" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_awready" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_ctrl_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_wvalid" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_wready" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_ctrl_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_bvalid" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_bready" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_ctrl_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_arvalid" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_arready" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_ctrl_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_rvalid" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_rready" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_ctrl_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_ctrl_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_avg_buffer_0_m0_axis" NAME="S00_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="s_axis_tlast"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_avg_M00_AXIS" NAME="M00_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_tlast"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_avg_buffer_1_m0_axis" NAME="S01_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="s_axis_tlast"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M17_AXI" DATAWIDTH="32" NAME="S_AXI_CTRL" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="7"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_ctrl_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_ctrl_awready"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_ctrl_awaddr"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_ctrl_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_ctrl_wready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_ctrl_wdata"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_ctrl_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_ctrl_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_ctrl_bresp"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_ctrl_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_ctrl_arready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_ctrl_araddr"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_ctrl_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_ctrl_rready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_ctrl_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_ctrl_rresp"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="26" FULLNAME="/axis_switch_buf" HWVERSION="1.1" INSTANCE="axis_switch_buf" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_switch" VLNV="xilinx.com:ip:axis_switch:1.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_switch;v=v1_1;d=pg085-axi4stream-infrastructure.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI_CTRL" NAME="Reg" RANGE="4096" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_NUM_SI_SLOTS" VALUE="2"/>
        <PARAMETER NAME="C_LOG_SI_SLOTS" VALUE="1"/>
        <PARAMETER NAME="C_NUM_MI_SLOTS" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000010011"/>
        <PARAMETER NAME="C_ARB_ON_MAX_XFERS" VALUE="1"/>
        <PARAMETER NAME="C_ARB_ON_NUM_CYCLES" VALUE="0"/>
        <PARAMETER NAME="C_ARB_ON_TLAST" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_ARBITER" VALUE="1"/>
        <PARAMETER NAME="C_ARB_ALGORITHM" VALUE="0"/>
        <PARAMETER NAME="C_OUTPUT_REG" VALUE="0"/>
        <PARAMETER NAME="C_DECODER_REG" VALUE="0"/>
        <PARAMETER NAME="C_M_AXIS_CONNECTIVITY_ARRAY" VALUE="&quot;11&quot;"/>
        <PARAMETER NAME="C_M_AXIS_BASETDEST_ARRAY" VALUE="0b0"/>
        <PARAMETER NAME="C_M_AXIS_HIGHTDEST_ARRAY" VALUE="0b0"/>
        <PARAMETER NAME="C_ROUTING_MODE" VALUE="1"/>
        <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="7"/>
        <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_COMMON_CLOCK" VALUE="0"/>
        <PARAMETER NAME="NUM_SI" VALUE="2"/>
        <PARAMETER NAME="NUM_MI" VALUE="1"/>
        <PARAMETER NAME="ROUTING_MODE" VALUE="1"/>
        <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
        <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
        <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="ARB_ON_MAX_XFERS" VALUE="1"/>
        <PARAMETER NAME="ARB_ON_NUM_CYCLES" VALUE="0"/>
        <PARAMETER NAME="ARB_ON_TLAST" VALUE="0"/>
        <PARAMETER NAME="ARB_ALGORITHM" VALUE="0"/>
        <PARAMETER NAME="DECODER_REG" VALUE="0"/>
        <PARAMETER NAME="OUTPUT_REG" VALUE="0"/>
        <PARAMETER NAME="COMMON_CLOCK" VALUE="0"/>
        <PARAMETER NAME="M00_AXIS_BASETDEST" VALUE="0x00000000"/>
        <PARAMETER NAME="M01_AXIS_BASETDEST" VALUE="0x00000001"/>
        <PARAMETER NAME="M02_AXIS_BASETDEST" VALUE="0x00000002"/>
        <PARAMETER NAME="M03_AXIS_BASETDEST" VALUE="0x00000003"/>
        <PARAMETER NAME="M04_AXIS_BASETDEST" VALUE="0x00000004"/>
        <PARAMETER NAME="M05_AXIS_BASETDEST" VALUE="0x00000005"/>
        <PARAMETER NAME="M06_AXIS_BASETDEST" VALUE="0x00000006"/>
        <PARAMETER NAME="M07_AXIS_BASETDEST" VALUE="0x00000007"/>
        <PARAMETER NAME="M08_AXIS_BASETDEST" VALUE="0x00000008"/>
        <PARAMETER NAME="M09_AXIS_BASETDEST" VALUE="0x00000009"/>
        <PARAMETER NAME="M10_AXIS_BASETDEST" VALUE="0x0000000a"/>
        <PARAMETER NAME="M11_AXIS_BASETDEST" VALUE="0x0000000b"/>
        <PARAMETER NAME="M12_AXIS_BASETDEST" VALUE="0x0000000c"/>
        <PARAMETER NAME="M13_AXIS_BASETDEST" VALUE="0x0000000d"/>
        <PARAMETER NAME="M14_AXIS_BASETDEST" VALUE="0x0000000e"/>
        <PARAMETER NAME="M15_AXIS_BASETDEST" VALUE="0x0000000f"/>
        <PARAMETER NAME="M00_AXIS_HIGHTDEST" VALUE="0x00000000"/>
        <PARAMETER NAME="M01_AXIS_HIGHTDEST" VALUE="0x00000001"/>
        <PARAMETER NAME="M02_AXIS_HIGHTDEST" VALUE="0x00000002"/>
        <PARAMETER NAME="M03_AXIS_HIGHTDEST" VALUE="0x00000003"/>
        <PARAMETER NAME="M04_AXIS_HIGHTDEST" VALUE="0x00000004"/>
        <PARAMETER NAME="M05_AXIS_HIGHTDEST" VALUE="0x00000005"/>
        <PARAMETER NAME="M06_AXIS_HIGHTDEST" VALUE="0x00000006"/>
        <PARAMETER NAME="M07_AXIS_HIGHTDEST" VALUE="0x00000007"/>
        <PARAMETER NAME="M08_AXIS_HIGHTDEST" VALUE="0x00000008"/>
        <PARAMETER NAME="M09_AXIS_HIGHTDEST" VALUE="0x00000009"/>
        <PARAMETER NAME="M10_AXIS_HIGHTDEST" VALUE="0x0000000a"/>
        <PARAMETER NAME="M11_AXIS_HIGHTDEST" VALUE="0x0000000b"/>
        <PARAMETER NAME="M12_AXIS_HIGHTDEST" VALUE="0x0000000c"/>
        <PARAMETER NAME="M13_AXIS_HIGHTDEST" VALUE="0x0000000d"/>
        <PARAMETER NAME="M14_AXIS_HIGHTDEST" VALUE="0x0000000e"/>
        <PARAMETER NAME="M15_AXIS_HIGHTDEST" VALUE="0x0000000f"/>
        <PARAMETER NAME="M00_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_switch_buf_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0250000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0250FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="s_axis_tvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="m1_axis_tvalid"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="m1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axis_tready" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="m1_axis_tready"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="m1_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="63" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="m1_axis_tdata"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="m1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="s_axis_tlast" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_m1_axis_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="m1_axis_tlast"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="m1_axis_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="m_axis_tvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axis_s2mm_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axis_s2mm_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="m_axis_tready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axis_s2mm_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axis_s2mm_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axis_s2mm_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axis_s2mm_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="m_axis_tlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axis_s2mm_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axis_s2mm_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_ctrl_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_awvalid" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_awready" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_ctrl_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_wvalid" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_wready" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_ctrl_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_bvalid" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_bready" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_ctrl_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_arvalid" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_arready" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_ctrl_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_rvalid" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_rready" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_ctrl_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_ctrl_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_avg_buffer_0_m1_axis" NAME="S00_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="s_axis_tlast"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_buf_M00_AXIS" NAME="M00_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_tlast"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_avg_buffer_1_m1_axis" NAME="S01_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="s_axis_tlast"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M18_AXI" DATAWIDTH="32" NAME="S_AXI_CTRL" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="7"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_ctrl_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_ctrl_awready"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_ctrl_awaddr"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_ctrl_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_ctrl_wready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_ctrl_wdata"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_ctrl_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_ctrl_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_ctrl_bresp"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_ctrl_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_ctrl_arready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_ctrl_araddr"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_ctrl_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_ctrl_rready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_ctrl_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_ctrl_rresp"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="26" FULLNAME="/axis_switch_ddr" HWVERSION="1.1" INSTANCE="axis_switch_ddr" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_switch" VLNV="xilinx.com:ip:axis_switch:1.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_switch;v=v1_1;d=pg085-axi4stream-infrastructure.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI_CTRL" NAME="Reg" RANGE="4096" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_NUM_SI_SLOTS" VALUE="2"/>
        <PARAMETER NAME="C_LOG_SI_SLOTS" VALUE="1"/>
        <PARAMETER NAME="C_NUM_MI_SLOTS" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000000010"/>
        <PARAMETER NAME="C_ARB_ON_MAX_XFERS" VALUE="1"/>
        <PARAMETER NAME="C_ARB_ON_NUM_CYCLES" VALUE="0"/>
        <PARAMETER NAME="C_ARB_ON_TLAST" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_ARBITER" VALUE="1"/>
        <PARAMETER NAME="C_ARB_ALGORITHM" VALUE="0"/>
        <PARAMETER NAME="C_OUTPUT_REG" VALUE="0"/>
        <PARAMETER NAME="C_DECODER_REG" VALUE="0"/>
        <PARAMETER NAME="C_M_AXIS_CONNECTIVITY_ARRAY" VALUE="&quot;11&quot;"/>
        <PARAMETER NAME="C_M_AXIS_BASETDEST_ARRAY" VALUE="0b0"/>
        <PARAMETER NAME="C_M_AXIS_HIGHTDEST_ARRAY" VALUE="0b0"/>
        <PARAMETER NAME="C_ROUTING_MODE" VALUE="1"/>
        <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="7"/>
        <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_COMMON_CLOCK" VALUE="0"/>
        <PARAMETER NAME="NUM_SI" VALUE="2"/>
        <PARAMETER NAME="NUM_MI" VALUE="1"/>
        <PARAMETER NAME="ROUTING_MODE" VALUE="1"/>
        <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
        <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
        <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="ARB_ON_MAX_XFERS" VALUE="1"/>
        <PARAMETER NAME="ARB_ON_NUM_CYCLES" VALUE="0"/>
        <PARAMETER NAME="ARB_ON_TLAST" VALUE="0"/>
        <PARAMETER NAME="ARB_ALGORITHM" VALUE="0"/>
        <PARAMETER NAME="DECODER_REG" VALUE="0"/>
        <PARAMETER NAME="OUTPUT_REG" VALUE="0"/>
        <PARAMETER NAME="COMMON_CLOCK" VALUE="0"/>
        <PARAMETER NAME="M00_AXIS_BASETDEST" VALUE="0x00000000"/>
        <PARAMETER NAME="M01_AXIS_BASETDEST" VALUE="0x00000001"/>
        <PARAMETER NAME="M02_AXIS_BASETDEST" VALUE="0x00000002"/>
        <PARAMETER NAME="M03_AXIS_BASETDEST" VALUE="0x00000003"/>
        <PARAMETER NAME="M04_AXIS_BASETDEST" VALUE="0x00000004"/>
        <PARAMETER NAME="M05_AXIS_BASETDEST" VALUE="0x00000005"/>
        <PARAMETER NAME="M06_AXIS_BASETDEST" VALUE="0x00000006"/>
        <PARAMETER NAME="M07_AXIS_BASETDEST" VALUE="0x00000007"/>
        <PARAMETER NAME="M08_AXIS_BASETDEST" VALUE="0x00000008"/>
        <PARAMETER NAME="M09_AXIS_BASETDEST" VALUE="0x00000009"/>
        <PARAMETER NAME="M10_AXIS_BASETDEST" VALUE="0x0000000a"/>
        <PARAMETER NAME="M11_AXIS_BASETDEST" VALUE="0x0000000b"/>
        <PARAMETER NAME="M12_AXIS_BASETDEST" VALUE="0x0000000c"/>
        <PARAMETER NAME="M13_AXIS_BASETDEST" VALUE="0x0000000d"/>
        <PARAMETER NAME="M14_AXIS_BASETDEST" VALUE="0x0000000e"/>
        <PARAMETER NAME="M15_AXIS_BASETDEST" VALUE="0x0000000f"/>
        <PARAMETER NAME="M00_AXIS_HIGHTDEST" VALUE="0x00000000"/>
        <PARAMETER NAME="M01_AXIS_HIGHTDEST" VALUE="0x00000001"/>
        <PARAMETER NAME="M02_AXIS_HIGHTDEST" VALUE="0x00000002"/>
        <PARAMETER NAME="M03_AXIS_HIGHTDEST" VALUE="0x00000003"/>
        <PARAMETER NAME="M04_AXIS_HIGHTDEST" VALUE="0x00000004"/>
        <PARAMETER NAME="M05_AXIS_HIGHTDEST" VALUE="0x00000005"/>
        <PARAMETER NAME="M06_AXIS_HIGHTDEST" VALUE="0x00000006"/>
        <PARAMETER NAME="M07_AXIS_HIGHTDEST" VALUE="0x00000007"/>
        <PARAMETER NAME="M08_AXIS_HIGHTDEST" VALUE="0x00000008"/>
        <PARAMETER NAME="M09_AXIS_HIGHTDEST" VALUE="0x00000009"/>
        <PARAMETER NAME="M10_AXIS_HIGHTDEST" VALUE="0x0000000a"/>
        <PARAMETER NAME="M11_AXIS_HIGHTDEST" VALUE="0x0000000b"/>
        <PARAMETER NAME="M12_AXIS_HIGHTDEST" VALUE="0x0000000c"/>
        <PARAMETER NAME="M13_AXIS_HIGHTDEST" VALUE="0x0000000d"/>
        <PARAMETER NAME="M14_AXIS_HIGHTDEST" VALUE="0x0000000e"/>
        <PARAMETER NAME="M15_AXIS_HIGHTDEST" VALUE="0x0000000f"/>
        <PARAMETER NAME="M00_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_switch_ddr_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0255000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0255FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="512000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_adc0_x2_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="s_axis_tvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_broadcaster_1_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_broadcaster_0" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_broadcaster_1" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="63" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_broadcaster_1_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_broadcaster_0" PORT="m_axis_tdata"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_broadcaster_1" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="m_axis_tvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_dwidth_converter_0_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_dwidth_converter_0" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_dwidth_converter_0_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_dwidth_converter_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_ctrl_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_awvalid" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_awready" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_ctrl_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_wvalid" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_wready" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_ctrl_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_bvalid" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_bready" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_ctrl_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_arvalid" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_arready" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_ctrl_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_rvalid" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_rready" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_ctrl_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_ctrl_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_broadcaster_0_M01_AXIS" NAME="S00_AXIS" TYPE="SLAVE" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_ddr_M00_AXIS" NAME="M00_AXIS" TYPE="MASTER" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_broadcaster_1_M01_AXIS" NAME="S01_AXIS" TYPE="SLAVE" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M22_AXI" DATAWIDTH="32" NAME="S_AXI_CTRL" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="7"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_ctrl_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_ctrl_awready"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_ctrl_awaddr"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_ctrl_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_ctrl_wready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_ctrl_wdata"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_ctrl_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_ctrl_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_ctrl_bresp"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_ctrl_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_ctrl_arready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_ctrl_araddr"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_ctrl_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_ctrl_rready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_ctrl_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_ctrl_rresp"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="26" FULLNAME="/axis_switch_gen" HWVERSION="1.1" INSTANCE="axis_switch_gen" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_switch" VLNV="xilinx.com:ip:axis_switch:1.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_switch;v=v1_1;d=pg085-axi4stream-infrastructure.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI_CTRL" NAME="Reg" RANGE="4096" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_NUM_SI_SLOTS" VALUE="1"/>
        <PARAMETER NAME="C_LOG_SI_SLOTS" VALUE="1"/>
        <PARAMETER NAME="C_NUM_MI_SLOTS" VALUE="8"/>
        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000011011"/>
        <PARAMETER NAME="C_ARB_ON_MAX_XFERS" VALUE="1"/>
        <PARAMETER NAME="C_ARB_ON_NUM_CYCLES" VALUE="0"/>
        <PARAMETER NAME="C_ARB_ON_TLAST" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_ARBITER" VALUE="1"/>
        <PARAMETER NAME="C_ARB_ALGORITHM" VALUE="0"/>
        <PARAMETER NAME="C_OUTPUT_REG" VALUE="0"/>
        <PARAMETER NAME="C_DECODER_REG" VALUE="1"/>
        <PARAMETER NAME="C_M_AXIS_CONNECTIVITY_ARRAY" VALUE="0b11111111"/>
        <PARAMETER NAME="C_M_AXIS_BASETDEST_ARRAY" VALUE="0b10101010"/>
        <PARAMETER NAME="C_M_AXIS_HIGHTDEST_ARRAY" VALUE="0b10101010"/>
        <PARAMETER NAME="C_ROUTING_MODE" VALUE="1"/>
        <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="7"/>
        <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_COMMON_CLOCK" VALUE="0"/>
        <PARAMETER NAME="NUM_SI" VALUE="1"/>
        <PARAMETER NAME="NUM_MI" VALUE="8"/>
        <PARAMETER NAME="ROUTING_MODE" VALUE="1"/>
        <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
        <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
        <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
        <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="ARB_ON_MAX_XFERS" VALUE="1"/>
        <PARAMETER NAME="ARB_ON_NUM_CYCLES" VALUE="0"/>
        <PARAMETER NAME="ARB_ON_TLAST" VALUE="0"/>
        <PARAMETER NAME="ARB_ALGORITHM" VALUE="0"/>
        <PARAMETER NAME="DECODER_REG" VALUE="1"/>
        <PARAMETER NAME="OUTPUT_REG" VALUE="0"/>
        <PARAMETER NAME="COMMON_CLOCK" VALUE="0"/>
        <PARAMETER NAME="M00_AXIS_BASETDEST" VALUE="0x00000000"/>
        <PARAMETER NAME="M01_AXIS_BASETDEST" VALUE="0x00000001"/>
        <PARAMETER NAME="M02_AXIS_BASETDEST" VALUE="0x00000002"/>
        <PARAMETER NAME="M03_AXIS_BASETDEST" VALUE="0x00000003"/>
        <PARAMETER NAME="M04_AXIS_BASETDEST" VALUE="0x00000004"/>
        <PARAMETER NAME="M05_AXIS_BASETDEST" VALUE="0x00000005"/>
        <PARAMETER NAME="M06_AXIS_BASETDEST" VALUE="0x00000006"/>
        <PARAMETER NAME="M07_AXIS_BASETDEST" VALUE="0x00000007"/>
        <PARAMETER NAME="M08_AXIS_BASETDEST" VALUE="0x00000008"/>
        <PARAMETER NAME="M09_AXIS_BASETDEST" VALUE="0x00000009"/>
        <PARAMETER NAME="M10_AXIS_BASETDEST" VALUE="0x0000000a"/>
        <PARAMETER NAME="M11_AXIS_BASETDEST" VALUE="0x0000000b"/>
        <PARAMETER NAME="M12_AXIS_BASETDEST" VALUE="0x0000000c"/>
        <PARAMETER NAME="M13_AXIS_BASETDEST" VALUE="0x0000000d"/>
        <PARAMETER NAME="M14_AXIS_BASETDEST" VALUE="0x0000000e"/>
        <PARAMETER NAME="M15_AXIS_BASETDEST" VALUE="0x0000000f"/>
        <PARAMETER NAME="M00_AXIS_HIGHTDEST" VALUE="0x00000000"/>
        <PARAMETER NAME="M01_AXIS_HIGHTDEST" VALUE="0x00000001"/>
        <PARAMETER NAME="M02_AXIS_HIGHTDEST" VALUE="0x00000002"/>
        <PARAMETER NAME="M03_AXIS_HIGHTDEST" VALUE="0x00000003"/>
        <PARAMETER NAME="M04_AXIS_HIGHTDEST" VALUE="0x00000004"/>
        <PARAMETER NAME="M05_AXIS_HIGHTDEST" VALUE="0x00000005"/>
        <PARAMETER NAME="M06_AXIS_HIGHTDEST" VALUE="0x00000006"/>
        <PARAMETER NAME="M07_AXIS_HIGHTDEST" VALUE="0x00000007"/>
        <PARAMETER NAME="M08_AXIS_HIGHTDEST" VALUE="0x00000008"/>
        <PARAMETER NAME="M09_AXIS_HIGHTDEST" VALUE="0x00000009"/>
        <PARAMETER NAME="M10_AXIS_HIGHTDEST" VALUE="0x0000000a"/>
        <PARAMETER NAME="M11_AXIS_HIGHTDEST" VALUE="0x0000000b"/>
        <PARAMETER NAME="M12_AXIS_HIGHTDEST" VALUE="0x0000000c"/>
        <PARAMETER NAME="M13_AXIS_HIGHTDEST" VALUE="0x0000000d"/>
        <PARAMETER NAME="M14_AXIS_HIGHTDEST" VALUE="0x0000000e"/>
        <PARAMETER NAME="M15_AXIS_HIGHTDEST" VALUE="0x0000000f"/>
        <PARAMETER NAME="M00_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_switch_gen_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0251000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0251FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="s_axis_tvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axis_mm2s_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axis_mm2s_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="s_axis_tready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axis_mm2s_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axis_mm2s_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axis_mm2s_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axis_mm2s_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axis_tkeep" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axis_mm2s_tkeep">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axis_mm2s_tkeep"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="s_axis_tlast" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_m_axis_mm2s_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axis_mm2s_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="m_axis_tvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s0_axis_tvalid"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s0_axis_tvalid"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s0_axis_tvalid"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s0_axis_tvalid"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s0_axis_tvalid"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s0_axis_tvalid"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s0_axis_tvalid"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s0_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="m_axis_tready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s0_axis_tready"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s0_axis_tready"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s0_axis_tready"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s0_axis_tready"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s0_axis_tready"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s0_axis_tready"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s0_axis_tready"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s0_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="255" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s0_axis_tdata"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s0_axis_tdata"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s0_axis_tdata"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s0_axis_tdata"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s0_axis_tdata"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s0_axis_tdata"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s0_axis_tdata"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s0_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m_axis_tkeep" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="7" NAME="m_axis_tlast" RIGHT="0" SIGIS="undef"/>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_ctrl_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_awvalid" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_awready" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_ctrl_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_wvalid" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_wready" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_ctrl_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_bvalid" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_bready" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_ctrl_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_arvalid" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_arready" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_ctrl_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_rvalid" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_rready" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_ctrl_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_ctrl_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axi_dma_gen_M_AXIS_MM2S" NAME="S00_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="s_axis_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="s_axis_tlast"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M00_AXIS" NAME="M00_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="m_axis_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_tlast"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M01_AXIS" NAME="M01_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="m_axis_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_tlast"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M02_AXIS" NAME="M02_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="m_axis_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_tlast"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M03_AXIS" NAME="M03_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="m_axis_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_tlast"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M04_AXIS" NAME="M04_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="m_axis_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_tlast"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M05_AXIS" NAME="M05_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="m_axis_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_tlast"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M06_AXIS" NAME="M06_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="m_axis_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_tlast"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_gen_M07_AXIS" NAME="M07_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="1"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
            <PORTMAP LOGICAL="TKEEP" PHYSICAL="m_axis_tkeep"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_axis_tlast"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M07_AXI" DATAWIDTH="32" NAME="S_AXI_CTRL" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="7"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_ctrl_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_ctrl_awready"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_ctrl_awaddr"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_ctrl_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_ctrl_wready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_ctrl_wdata"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_ctrl_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_ctrl_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_ctrl_bresp"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_ctrl_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_ctrl_arready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_ctrl_araddr"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_ctrl_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_ctrl_rready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_ctrl_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_ctrl_rresp"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="26" FULLNAME="/axis_switch_mr" HWVERSION="1.1" INSTANCE="axis_switch_mr" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="axis_switch" VLNV="xilinx.com:ip:axis_switch:1.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="https://www.xilinx.com/cgi-bin/docs/ipdoc?c=axis_switch;v=v1_1;d=pg085-axi4stream-infrastructure.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="S_AXI_CTRL" NAME="Reg" RANGE="4096" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_NUM_SI_SLOTS" VALUE="2"/>
        <PARAMETER NAME="C_LOG_SI_SLOTS" VALUE="1"/>
        <PARAMETER NAME="C_NUM_MI_SLOTS" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDATA_WIDTH" VALUE="256"/>
        <PARAMETER NAME="C_AXIS_TID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TDEST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_TUSER_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_AXIS_SIGNAL_SET" VALUE="0b00000000000000000000000000000011"/>
        <PARAMETER NAME="C_ARB_ON_MAX_XFERS" VALUE="1"/>
        <PARAMETER NAME="C_ARB_ON_NUM_CYCLES" VALUE="0"/>
        <PARAMETER NAME="C_ARB_ON_TLAST" VALUE="0"/>
        <PARAMETER NAME="C_INCLUDE_ARBITER" VALUE="1"/>
        <PARAMETER NAME="C_ARB_ALGORITHM" VALUE="0"/>
        <PARAMETER NAME="C_OUTPUT_REG" VALUE="0"/>
        <PARAMETER NAME="C_DECODER_REG" VALUE="0"/>
        <PARAMETER NAME="C_M_AXIS_CONNECTIVITY_ARRAY" VALUE="&quot;11&quot;"/>
        <PARAMETER NAME="C_M_AXIS_BASETDEST_ARRAY" VALUE="0b0"/>
        <PARAMETER NAME="C_M_AXIS_HIGHTDEST_ARRAY" VALUE="0b0"/>
        <PARAMETER NAME="C_ROUTING_MODE" VALUE="1"/>
        <PARAMETER NAME="C_S_AXI_CTRL_ADDR_WIDTH" VALUE="7"/>
        <PARAMETER NAME="C_S_AXI_CTRL_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_COMMON_CLOCK" VALUE="0"/>
        <PARAMETER NAME="NUM_SI" VALUE="2"/>
        <PARAMETER NAME="NUM_MI" VALUE="1"/>
        <PARAMETER NAME="ROUTING_MODE" VALUE="1"/>
        <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
        <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
        <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
        <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
        <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
        <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
        <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
        <PARAMETER NAME="HAS_ACLKEN" VALUE="0"/>
        <PARAMETER NAME="ARB_ON_MAX_XFERS" VALUE="1"/>
        <PARAMETER NAME="ARB_ON_NUM_CYCLES" VALUE="0"/>
        <PARAMETER NAME="ARB_ON_TLAST" VALUE="0"/>
        <PARAMETER NAME="ARB_ALGORITHM" VALUE="0"/>
        <PARAMETER NAME="DECODER_REG" VALUE="0"/>
        <PARAMETER NAME="OUTPUT_REG" VALUE="0"/>
        <PARAMETER NAME="COMMON_CLOCK" VALUE="0"/>
        <PARAMETER NAME="M00_AXIS_BASETDEST" VALUE="0x00000000"/>
        <PARAMETER NAME="M01_AXIS_BASETDEST" VALUE="0x00000001"/>
        <PARAMETER NAME="M02_AXIS_BASETDEST" VALUE="0x00000002"/>
        <PARAMETER NAME="M03_AXIS_BASETDEST" VALUE="0x00000003"/>
        <PARAMETER NAME="M04_AXIS_BASETDEST" VALUE="0x00000004"/>
        <PARAMETER NAME="M05_AXIS_BASETDEST" VALUE="0x00000005"/>
        <PARAMETER NAME="M06_AXIS_BASETDEST" VALUE="0x00000006"/>
        <PARAMETER NAME="M07_AXIS_BASETDEST" VALUE="0x00000007"/>
        <PARAMETER NAME="M08_AXIS_BASETDEST" VALUE="0x00000008"/>
        <PARAMETER NAME="M09_AXIS_BASETDEST" VALUE="0x00000009"/>
        <PARAMETER NAME="M10_AXIS_BASETDEST" VALUE="0x0000000a"/>
        <PARAMETER NAME="M11_AXIS_BASETDEST" VALUE="0x0000000b"/>
        <PARAMETER NAME="M12_AXIS_BASETDEST" VALUE="0x0000000c"/>
        <PARAMETER NAME="M13_AXIS_BASETDEST" VALUE="0x0000000d"/>
        <PARAMETER NAME="M14_AXIS_BASETDEST" VALUE="0x0000000e"/>
        <PARAMETER NAME="M15_AXIS_BASETDEST" VALUE="0x0000000f"/>
        <PARAMETER NAME="M00_AXIS_HIGHTDEST" VALUE="0x00000000"/>
        <PARAMETER NAME="M01_AXIS_HIGHTDEST" VALUE="0x00000001"/>
        <PARAMETER NAME="M02_AXIS_HIGHTDEST" VALUE="0x00000002"/>
        <PARAMETER NAME="M03_AXIS_HIGHTDEST" VALUE="0x00000003"/>
        <PARAMETER NAME="M04_AXIS_HIGHTDEST" VALUE="0x00000004"/>
        <PARAMETER NAME="M05_AXIS_HIGHTDEST" VALUE="0x00000005"/>
        <PARAMETER NAME="M06_AXIS_HIGHTDEST" VALUE="0x00000006"/>
        <PARAMETER NAME="M07_AXIS_HIGHTDEST" VALUE="0x00000007"/>
        <PARAMETER NAME="M08_AXIS_HIGHTDEST" VALUE="0x00000008"/>
        <PARAMETER NAME="M09_AXIS_HIGHTDEST" VALUE="0x00000009"/>
        <PARAMETER NAME="M10_AXIS_HIGHTDEST" VALUE="0x0000000a"/>
        <PARAMETER NAME="M11_AXIS_HIGHTDEST" VALUE="0x0000000b"/>
        <PARAMETER NAME="M12_AXIS_HIGHTDEST" VALUE="0x0000000c"/>
        <PARAMETER NAME="M13_AXIS_HIGHTDEST" VALUE="0x0000000d"/>
        <PARAMETER NAME="M14_AXIS_HIGHTDEST" VALUE="0x0000000e"/>
        <PARAMETER NAME="M15_AXIS_HIGHTDEST" VALUE="0x0000000f"/>
        <PARAMETER NAME="M00_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M00_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M01_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M02_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M03_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M04_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M05_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M06_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M07_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M08_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M09_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M10_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M11_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M12_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M13_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M14_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S00_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S01_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S02_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S03_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S04_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S05_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S06_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S07_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S08_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S09_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S10_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S11_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S12_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S13_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S14_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="M15_S15_CONNECTIVITY" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_axis_switch_mr_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0256000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0256FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="512000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_adc0_x2_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="s_axis_tvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_m0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="m0_axis_tvalid"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="m0_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axis_tready" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_m0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="m0_axis_tready"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="m0_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="511" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_m0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="m0_axis_tdata"/>
          </CONNECTIONS>
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="m0_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="m_axis_tvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="m_axis_tready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="255" NAME="m_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_ctrl_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_awvalid" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_awready" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_ctrl_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_wvalid" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_wready" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_ctrl_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_bvalid" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_bready" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_ctrl_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_arvalid" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_arready" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_ctrl_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_ctrl_rvalid" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_ctrl_rready" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_ctrl_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_ctrl_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="axis_readout_v2_0_m0_axis" NAME="S00_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_mr_M00_AXIS" NAME="M00_AXIS" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_readout_v2_1_m0_axis" NAME="S01_AXIS" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M23_AXI" DATAWIDTH="32" NAME="S_AXI_CTRL" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="7"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_ctrl_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_ctrl_awready"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_ctrl_awaddr"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_ctrl_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_ctrl_wready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_ctrl_wdata"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_ctrl_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_ctrl_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_ctrl_bresp"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_ctrl_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_ctrl_arready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_ctrl_araddr"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_ctrl_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_ctrl_rready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_ctrl_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_ctrl_rresp"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="7" FULLNAME="/bias_constant_1" HWVERSION="1.1" INSTANCE="bias_constant_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconstant" VLNV="xilinx.com:ip:xlconstant:1.1">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="CONST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="CONST_VAL" VALUE="0x1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_bias_constant_1_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" LEFT="0" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="bias_constant_1_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="BIAS_CLR"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="10" FULLNAME="/clk_adc0_x2" HWVERSION="6.0" INSTANCE="clk_adc0_x2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="clk_wiz" VLNV="xilinx.com:ip:clk_wiz:6.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clk_wiz;v=v6_0;d=pg065-clk-wiz.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_CLKOUT2_USED" VALUE="0"/>
        <PARAMETER NAME="C_USER_CLK_FREQ0" VALUE="100.0"/>
        <PARAMETER NAME="C_AUTO_PRIMITIVE" VALUE="MMCM"/>
        <PARAMETER NAME="C_USER_CLK_FREQ1" VALUE="100.0"/>
        <PARAMETER NAME="C_USER_CLK_FREQ2" VALUE="100.0"/>
        <PARAMETER NAME="C_USER_CLK_FREQ3" VALUE="100.0"/>
        <PARAMETER NAME="C_ENABLE_CLOCK_MONITOR" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_USER_CLOCK0" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_USER_CLOCK1" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_USER_CLOCK2" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_USER_CLOCK3" VALUE="0"/>
        <PARAMETER NAME="C_Enable_PLL0" VALUE="0"/>
        <PARAMETER NAME="C_Enable_PLL1" VALUE="0"/>
        <PARAMETER NAME="C_REF_CLK_FREQ" VALUE="100.0"/>
        <PARAMETER NAME="C_PRECISION" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT3_USED" VALUE="0"/>
        <PARAMETER NAME="C_CLKOUT4_USED" VALUE="0"/>
        <PARAMETER NAME="C_CLKOUT5_USED" VALUE="0"/>
        <PARAMETER NAME="C_CLKOUT6_USED" VALUE="0"/>
        <PARAMETER NAME="C_CLKOUT7_USED" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLKOUT1_BAR" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLKOUT2_BAR" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLKOUT3_BAR" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLKOUT4_BAR" VALUE="0"/>
        <PARAMETER NAME="c_component_name" VALUE="d_1_clk_adc0_x2_0"/>
        <PARAMETER NAME="C_PLATFORM" VALUE="UNKNOWN"/>
        <PARAMETER NAME="C_USE_FREQ_SYNTH" VALUE="1"/>
        <PARAMETER NAME="C_USE_PHASE_ALIGNMENT" VALUE="0"/>
        <PARAMETER NAME="C_PRIM_IN_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="C_SECONDARY_IN_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="C_JITTER_SEL" VALUE="No_Jitter"/>
        <PARAMETER NAME="C_USE_MIN_POWER" VALUE="0"/>
        <PARAMETER NAME="C_USE_MIN_O_JITTER" VALUE="0"/>
        <PARAMETER NAME="C_USE_MAX_I_JITTER" VALUE="0"/>
        <PARAMETER NAME="C_USE_DYN_PHASE_SHIFT" VALUE="0"/>
        <PARAMETER NAME="C_OPTIMIZE_CLOCKING_STRUCTURE_EN" VALUE="1"/>
        <PARAMETER NAME="C_USE_INCLK_SWITCHOVER" VALUE="0"/>
        <PARAMETER NAME="C_USE_DYN_RECONFIG" VALUE="0"/>
        <PARAMETER NAME="C_USE_SPREAD_SPECTRUM" VALUE="0"/>
        <PARAMETER NAME="C_USE_FAST_SIMULATION" VALUE="0"/>
        <PARAMETER NAME="C_PRIMTYPE_SEL" VALUE="AUTO"/>
        <PARAMETER NAME="C_USE_CLK_VALID" VALUE="0"/>
        <PARAMETER NAME="C_PRIM_IN_FREQ" VALUE="256.000"/>
        <PARAMETER NAME="C_PRIM_IN_TIMEPERIOD" VALUE="10.000"/>
        <PARAMETER NAME="C_IN_FREQ_UNITS" VALUE="Units_MHz"/>
        <PARAMETER NAME="C_SECONDARY_IN_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_SECONDARY_IN_TIMEPERIOD" VALUE="10.000"/>
        <PARAMETER NAME="C_FEEDBACK_SOURCE" VALUE="FDBK_AUTO"/>
        <PARAMETER NAME="C_PRIM_SOURCE" VALUE="Global_buffer"/>
        <PARAMETER NAME="C_PHASESHIFT_MODE" VALUE="LATENCY"/>
        <PARAMETER NAME="C_SECONDARY_SOURCE" VALUE="Single_ended_clock_capable_pin"/>
        <PARAMETER NAME="C_CLKFB_IN_SIGNALING" VALUE="SINGLE"/>
        <PARAMETER NAME="C_USE_RESET" VALUE="1"/>
        <PARAMETER NAME="C_RESET_LOW" VALUE="0"/>
        <PARAMETER NAME="C_USE_LOCKED" VALUE="1"/>
        <PARAMETER NAME="C_USE_INCLK_STOPPED" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLKFB_STOPPED" VALUE="0"/>
        <PARAMETER NAME="C_USE_POWER_DOWN" VALUE="0"/>
        <PARAMETER NAME="C_USE_STATUS" VALUE="0"/>
        <PARAMETER NAME="C_USE_FREEZE" VALUE="0"/>
        <PARAMETER NAME="C_NUM_OUT_CLKS" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT1_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT2_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT3_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT4_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT5_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT6_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT7_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_INCLK_SUM_ROW0" VALUE="Input Clock   Freq (MHz)    Input Jitter (UI)"/>
        <PARAMETER NAME="C_INCLK_SUM_ROW1" VALUE="__primary_________256.000____________0.010"/>
        <PARAMETER NAME="C_INCLK_SUM_ROW2" VALUE="no_secondary_input_clock"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW0A" VALUE="Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW0B" VALUE="Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW1" VALUE="clk_out1__512.00000______0.000______50.0_______73.505_____77.298"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW2" VALUE="no_CLK_OUT2_output"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW3" VALUE="no_CLK_OUT3_output"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW4" VALUE="no_CLK_OUT4_output"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW5" VALUE="no_CLK_OUT5_output"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW6" VALUE="no_CLK_OUT6_output"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW7" VALUE="no_CLK_OUT7_output"/>
        <PARAMETER NAME="C_CLKOUT1_REQUESTED_OUT_FREQ" VALUE="512"/>
        <PARAMETER NAME="C_CLKOUT2_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT3_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT4_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT5_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT6_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT7_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT1_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT2_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT3_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT4_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT5_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT6_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT7_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT1_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT2_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT3_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT4_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT5_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT6_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT7_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT1_OUT_FREQ" VALUE="512.00000"/>
        <PARAMETER NAME="C_CLKOUT2_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT3_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT4_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT5_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT6_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT7_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT1_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT2_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT3_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT4_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT5_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT6_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT7_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT1_DUTY_CYCLE" VALUE="50.0"/>
        <PARAMETER NAME="C_CLKOUT2_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT3_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT4_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT5_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT6_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT7_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_USE_SAFE_CLOCK_STARTUP" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLOCK_SEQUENCING" VALUE="0"/>
        <PARAMETER NAME="C_CLKOUT1_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT2_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT3_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT4_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT5_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT6_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT7_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_NOTES" VALUE="None"/>
        <PARAMETER NAME="C_MMCM_BANDWIDTH" VALUE="OPTIMIZED"/>
        <PARAMETER NAME="C_MMCM_CLKFBOUT_MULT_F" VALUE="4.750"/>
        <PARAMETER NAME="C_MMCM_CLKIN1_PERIOD" VALUE="3.906"/>
        <PARAMETER NAME="C_MMCM_CLKIN2_PERIOD" VALUE="10.0"/>
        <PARAMETER NAME="C_MMCM_CLKOUT4_CASCADE" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLOCK_HOLD" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_COMPENSATION" VALUE="AUTO"/>
        <PARAMETER NAME="C_MMCM_DIVCLK_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_REF_JITTER1" VALUE="0.010"/>
        <PARAMETER NAME="C_MMCM_REF_JITTER2" VALUE="0.010"/>
        <PARAMETER NAME="C_MMCM_STARTUP_WAIT" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT0_DIVIDE_F" VALUE="2.375"/>
        <PARAMETER NAME="C_MMCM_CLKOUT1_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT2_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT3_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT4_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT5_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT6_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT6_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKFBOUT_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT0_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT1_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT2_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT3_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT4_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT5_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT6_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKFBOUT_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT0_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT1_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT2_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT3_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT4_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT5_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT6_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_PLL_NOTES" VALUE="No notes"/>
        <PARAMETER NAME="C_PLL_BANDWIDTH" VALUE="OPTIMIZED"/>
        <PARAMETER NAME="C_PLL_CLK_FEEDBACK" VALUE="CLKFBOUT"/>
        <PARAMETER NAME="C_PLL_CLKFBOUT_MULT" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKIN_PERIOD" VALUE="1.000"/>
        <PARAMETER NAME="C_PLL_COMPENSATION" VALUE="SYSTEM_SYNCHRONOUS"/>
        <PARAMETER NAME="C_PLL_DIVCLK_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_REF_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="C_PLL_CLKOUT0_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT1_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT2_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT3_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT4_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT5_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKFBOUT_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT0_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT1_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT2_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT3_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT4_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT5_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLOCK_MGR_TYPE" VALUE="NA"/>
        <PARAMETER NAME="C_OVERRIDE_MMCM" VALUE="0"/>
        <PARAMETER NAME="C_OVERRIDE_PLL" VALUE="0"/>
        <PARAMETER NAME="C_PRIMARY_PORT" VALUE="clk_in1"/>
        <PARAMETER NAME="C_SECONDARY_PORT" VALUE="clk_in2"/>
        <PARAMETER NAME="C_CLK_OUT1_PORT" VALUE="clk_out1"/>
        <PARAMETER NAME="C_CLK_OUT2_PORT" VALUE="clk_out2"/>
        <PARAMETER NAME="C_CLK_OUT3_PORT" VALUE="clk_out3"/>
        <PARAMETER NAME="C_CLK_OUT4_PORT" VALUE="clk_out4"/>
        <PARAMETER NAME="C_CLK_OUT5_PORT" VALUE="clk_out5"/>
        <PARAMETER NAME="C_CLK_OUT6_PORT" VALUE="clk_out6"/>
        <PARAMETER NAME="C_CLK_OUT7_PORT" VALUE="clk_out7"/>
        <PARAMETER NAME="C_RESET_PORT" VALUE="reset"/>
        <PARAMETER NAME="C_LOCKED_PORT" VALUE="locked"/>
        <PARAMETER NAME="C_CLKFB_IN_PORT" VALUE="clkfb_in"/>
        <PARAMETER NAME="C_CLKFB_IN_P_PORT" VALUE="clkfb_in_p"/>
        <PARAMETER NAME="C_CLKFB_IN_N_PORT" VALUE="clkfb_in_n"/>
        <PARAMETER NAME="C_CLKFB_OUT_PORT" VALUE="clkfb_out"/>
        <PARAMETER NAME="C_CLKFB_OUT_P_PORT" VALUE="clkfb_out_p"/>
        <PARAMETER NAME="C_CLKFB_OUT_N_PORT" VALUE="clkfb_out_n"/>
        <PARAMETER NAME="C_POWER_DOWN_PORT" VALUE="power_down"/>
        <PARAMETER NAME="C_DADDR_PORT" VALUE="daddr"/>
        <PARAMETER NAME="C_DCLK_PORT" VALUE="dclk"/>
        <PARAMETER NAME="C_DRDY_PORT" VALUE="drdy"/>
        <PARAMETER NAME="C_DWE_PORT" VALUE="dwe"/>
        <PARAMETER NAME="C_DIN_PORT" VALUE="din"/>
        <PARAMETER NAME="C_DOUT_PORT" VALUE="dout"/>
        <PARAMETER NAME="C_DEN_PORT" VALUE="den"/>
        <PARAMETER NAME="C_PSCLK_PORT" VALUE="psclk"/>
        <PARAMETER NAME="C_PSEN_PORT" VALUE="psen"/>
        <PARAMETER NAME="C_PSINCDEC_PORT" VALUE="psincdec"/>
        <PARAMETER NAME="C_PSDONE_PORT" VALUE="psdone"/>
        <PARAMETER NAME="C_CLK_VALID_PORT" VALUE="CLK_VALID"/>
        <PARAMETER NAME="C_STATUS_PORT" VALUE="STATUS"/>
        <PARAMETER NAME="C_CLK_IN_SEL_PORT" VALUE="clk_in_sel"/>
        <PARAMETER NAME="C_INPUT_CLK_STOPPED_PORT" VALUE="input_clk_stopped"/>
        <PARAMETER NAME="C_CLKFB_STOPPED_PORT" VALUE="clkfb_stopped"/>
        <PARAMETER NAME="C_CLKIN1_JITTER_PS" VALUE="39.06"/>
        <PARAMETER NAME="C_CLKIN2_JITTER_PS" VALUE="100.0"/>
        <PARAMETER NAME="C_PRIMITIVE" VALUE="MMCM"/>
        <PARAMETER NAME="C_SS_MODE" VALUE="CENTER_HIGH"/>
        <PARAMETER NAME="C_SS_MOD_PERIOD" VALUE="4000"/>
        <PARAMETER NAME="C_SS_MOD_TIME" VALUE="0.004"/>
        <PARAMETER NAME="C_HAS_CDDC" VALUE="0"/>
        <PARAMETER NAME="C_CDDCDONE_PORT" VALUE="cddcdone"/>
        <PARAMETER NAME="C_CDDCREQ_PORT" VALUE="cddcreq"/>
        <PARAMETER NAME="C_CLKOUTPHY_MODE" VALUE="VCO"/>
        <PARAMETER NAME="C_ENABLE_CLKOUTPHY" VALUE="0"/>
        <PARAMETER NAME="C_INTERFACE_SELECTION" VALUE="0"/>
        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="11"/>
        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_POWER_REG" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT0_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT0_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT1_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT1_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT2_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT2_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT3_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT3_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT4_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT4_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT5_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT5_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT6_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT6_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKFBOUT_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKFBOUT_2" VALUE="0000"/>
        <PARAMETER NAME="C_DIVCLK" VALUE="0000"/>
        <PARAMETER NAME="C_LOCK_1" VALUE="0000"/>
        <PARAMETER NAME="C_LOCK_2" VALUE="0000"/>
        <PARAMETER NAME="C_LOCK_3" VALUE="0000"/>
        <PARAMETER NAME="C_FILTER_1" VALUE="0000"/>
        <PARAMETER NAME="C_FILTER_2" VALUE="0000"/>
        <PARAMETER NAME="C_DIVIDE1_AUTO" VALUE="1"/>
        <PARAMETER NAME="C_DIVIDE2_AUTO" VALUE="0.42105263157894735"/>
        <PARAMETER NAME="C_DIVIDE3_AUTO" VALUE="0.42105263157894735"/>
        <PARAMETER NAME="C_DIVIDE4_AUTO" VALUE="0.42105263157894735"/>
        <PARAMETER NAME="C_DIVIDE5_AUTO" VALUE="0.42105263157894735"/>
        <PARAMETER NAME="C_DIVIDE6_AUTO" VALUE="0.42105263157894735"/>
        <PARAMETER NAME="C_DIVIDE7_AUTO" VALUE="0.42105263157894735"/>
        <PARAMETER NAME="C_PLLBUFGCEDIV" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV" VALUE="false"/>
        <PARAMETER NAME="C_PLLBUFGCEDIV1" VALUE="false"/>
        <PARAMETER NAME="C_PLLBUFGCEDIV2" VALUE="false"/>
        <PARAMETER NAME="C_PLLBUFGCEDIV3" VALUE="false"/>
        <PARAMETER NAME="C_PLLBUFGCEDIV4" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV1" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV2" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV3" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV4" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV5" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV6" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV7" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT1_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT2_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT3_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT4_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT5_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT6_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT7_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT0_ACTUAL_FREQ" VALUE="512.00000"/>
        <PARAMETER NAME="C_CLKOUT1_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT2_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT3_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT4_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT5_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT6_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_M_MAX" VALUE="128.000"/>
        <PARAMETER NAME="C_M_MIN" VALUE="2.000"/>
        <PARAMETER NAME="C_D_MAX" VALUE="93.000"/>
        <PARAMETER NAME="C_D_MIN" VALUE="1.000"/>
        <PARAMETER NAME="C_O_MAX" VALUE="128.000"/>
        <PARAMETER NAME="C_O_MIN" VALUE="1.000"/>
        <PARAMETER NAME="C_VCO_MIN" VALUE="800.000"/>
        <PARAMETER NAME="C_VCO_MAX" VALUE="1600.000"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_clk_adc0_x2_0"/>
        <PARAMETER NAME="USER_CLK_FREQ0" VALUE="100.0"/>
        <PARAMETER NAME="USER_CLK_FREQ1" VALUE="100.0"/>
        <PARAMETER NAME="USER_CLK_FREQ2" VALUE="100.0"/>
        <PARAMETER NAME="USER_CLK_FREQ3" VALUE="100.0"/>
        <PARAMETER NAME="ENABLE_CLOCK_MONITOR" VALUE="false"/>
        <PARAMETER NAME="OPTIMIZE_CLOCKING_STRUCTURE_EN" VALUE="true"/>
        <PARAMETER NAME="ENABLE_USER_CLOCK0" VALUE="false"/>
        <PARAMETER NAME="ENABLE_USER_CLOCK1" VALUE="false"/>
        <PARAMETER NAME="ENABLE_USER_CLOCK2" VALUE="false"/>
        <PARAMETER NAME="ENABLE_USER_CLOCK3" VALUE="false"/>
        <PARAMETER NAME="Enable_PLL0" VALUE="false"/>
        <PARAMETER NAME="Enable_PLL1" VALUE="false"/>
        <PARAMETER NAME="REF_CLK_FREQ" VALUE="100.0"/>
        <PARAMETER NAME="PRECISION" VALUE="1"/>
        <PARAMETER NAME="PRIMITIVE" VALUE="MMCM"/>
        <PARAMETER NAME="PRIMTYPE_SEL" VALUE="mmcm_adv"/>
        <PARAMETER NAME="CLOCK_MGR_TYPE" VALUE="auto"/>
        <PARAMETER NAME="USE_FREQ_SYNTH" VALUE="true"/>
        <PARAMETER NAME="USE_SPREAD_SPECTRUM" VALUE="false"/>
        <PARAMETER NAME="USE_PHASE_ALIGNMENT" VALUE="false"/>
        <PARAMETER NAME="USE_MIN_POWER" VALUE="false"/>
        <PARAMETER NAME="USE_DYN_PHASE_SHIFT" VALUE="false"/>
        <PARAMETER NAME="USE_DYN_RECONFIG" VALUE="false"/>
        <PARAMETER NAME="JITTER_SEL" VALUE="No_Jitter"/>
        <PARAMETER NAME="PRIM_IN_FREQ" VALUE="256.000"/>
        <PARAMETER NAME="PRIM_IN_TIMEPERIOD" VALUE="10.000"/>
        <PARAMETER NAME="IN_FREQ_UNITS" VALUE="Units_MHz"/>
        <PARAMETER NAME="PHASESHIFT_MODE" VALUE="LATENCY"/>
        <PARAMETER NAME="IN_JITTER_UNITS" VALUE="Units_UI"/>
        <PARAMETER NAME="RELATIVE_INCLK" VALUE="REL_PRIMARY"/>
        <PARAMETER NAME="USE_INCLK_SWITCHOVER" VALUE="false"/>
        <PARAMETER NAME="SECONDARY_IN_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="SECONDARY_IN_TIMEPERIOD" VALUE="10.000"/>
        <PARAMETER NAME="SECONDARY_PORT" VALUE="clk_in2"/>
        <PARAMETER NAME="SECONDARY_SOURCE" VALUE="Single_ended_clock_capable_pin"/>
        <PARAMETER NAME="JITTER_OPTIONS" VALUE="UI"/>
        <PARAMETER NAME="CLKIN1_UI_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="CLKIN2_UI_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="PRIM_IN_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="SECONDARY_IN_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="CLKIN1_JITTER_PS" VALUE="39.06"/>
        <PARAMETER NAME="CLKIN2_JITTER_PS" VALUE="100.0"/>
        <PARAMETER NAME="CLKOUT1_USED" VALUE="true"/>
        <PARAMETER NAME="CLKOUT2_USED" VALUE="false"/>
        <PARAMETER NAME="CLKOUT3_USED" VALUE="false"/>
        <PARAMETER NAME="CLKOUT4_USED" VALUE="false"/>
        <PARAMETER NAME="CLKOUT5_USED" VALUE="false"/>
        <PARAMETER NAME="CLKOUT6_USED" VALUE="false"/>
        <PARAMETER NAME="CLKOUT7_USED" VALUE="false"/>
        <PARAMETER NAME="NUM_OUT_CLKS" VALUE="1"/>
        <PARAMETER NAME="CLK_OUT1_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT2_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT3_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT4_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT5_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT6_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT7_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="PRIMARY_PORT" VALUE="clk_in1"/>
        <PARAMETER NAME="CLK_OUT1_PORT" VALUE="clk_out1"/>
        <PARAMETER NAME="CLK_OUT2_PORT" VALUE="clk_out2"/>
        <PARAMETER NAME="CLK_OUT3_PORT" VALUE="clk_out3"/>
        <PARAMETER NAME="CLK_OUT4_PORT" VALUE="clk_out4"/>
        <PARAMETER NAME="CLK_OUT5_PORT" VALUE="clk_out5"/>
        <PARAMETER NAME="CLK_OUT6_PORT" VALUE="clk_out6"/>
        <PARAMETER NAME="CLK_OUT7_PORT" VALUE="clk_out7"/>
        <PARAMETER NAME="DADDR_PORT" VALUE="daddr"/>
        <PARAMETER NAME="DCLK_PORT" VALUE="dclk"/>
        <PARAMETER NAME="DRDY_PORT" VALUE="drdy"/>
        <PARAMETER NAME="DWE_PORT" VALUE="dwe"/>
        <PARAMETER NAME="DIN_PORT" VALUE="din"/>
        <PARAMETER NAME="DOUT_PORT" VALUE="dout"/>
        <PARAMETER NAME="DEN_PORT" VALUE="den"/>
        <PARAMETER NAME="PSCLK_PORT" VALUE="psclk"/>
        <PARAMETER NAME="PSEN_PORT" VALUE="psen"/>
        <PARAMETER NAME="PSINCDEC_PORT" VALUE="psincdec"/>
        <PARAMETER NAME="PSDONE_PORT" VALUE="psdone"/>
        <PARAMETER NAME="CLKOUT1_REQUESTED_OUT_FREQ" VALUE="512"/>
        <PARAMETER NAME="CLKOUT1_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT1_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT2_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT2_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT2_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT3_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT3_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT3_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT4_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT4_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT4_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT5_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT5_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT5_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT6_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT6_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT6_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT7_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT7_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT7_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="USE_MAX_I_JITTER" VALUE="false"/>
        <PARAMETER NAME="USE_MIN_O_JITTER" VALUE="false"/>
        <PARAMETER NAME="CLKOUT1_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT2_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT3_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT4_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT5_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT6_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT7_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="PRIM_SOURCE" VALUE="Global_buffer"/>
        <PARAMETER NAME="CLKOUT1_DRIVES" VALUE="Buffer"/>
        <PARAMETER NAME="CLKOUT2_DRIVES" VALUE="Buffer"/>
        <PARAMETER NAME="CLKOUT3_DRIVES" VALUE="Buffer"/>
        <PARAMETER NAME="CLKOUT4_DRIVES" VALUE="Buffer"/>
        <PARAMETER NAME="CLKOUT5_DRIVES" VALUE="Buffer"/>
        <PARAMETER NAME="CLKOUT6_DRIVES" VALUE="Buffer"/>
        <PARAMETER NAME="CLKOUT7_DRIVES" VALUE="Buffer"/>
        <PARAMETER NAME="FEEDBACK_SOURCE" VALUE="FDBK_AUTO"/>
        <PARAMETER NAME="CLKFB_IN_SIGNALING" VALUE="SINGLE"/>
        <PARAMETER NAME="CLKFB_IN_PORT" VALUE="clkfb_in"/>
        <PARAMETER NAME="CLKFB_IN_P_PORT" VALUE="clkfb_in_p"/>
        <PARAMETER NAME="CLKFB_IN_N_PORT" VALUE="clkfb_in_n"/>
        <PARAMETER NAME="CLKFB_OUT_PORT" VALUE="clkfb_out"/>
        <PARAMETER NAME="CLKFB_OUT_P_PORT" VALUE="clkfb_out_p"/>
        <PARAMETER NAME="CLKFB_OUT_N_PORT" VALUE="clkfb_out_n"/>
        <PARAMETER NAME="PLATFORM" VALUE="UNKNOWN"/>
        <PARAMETER NAME="SUMMARY_STRINGS" VALUE="empty"/>
        <PARAMETER NAME="USE_LOCKED" VALUE="true"/>
        <PARAMETER NAME="CALC_DONE" VALUE="empty"/>
        <PARAMETER NAME="USE_RESET" VALUE="true"/>
        <PARAMETER NAME="USE_POWER_DOWN" VALUE="false"/>
        <PARAMETER NAME="USE_STATUS" VALUE="false"/>
        <PARAMETER NAME="USE_FREEZE" VALUE="false"/>
        <PARAMETER NAME="USE_CLK_VALID" VALUE="false"/>
        <PARAMETER NAME="USE_INCLK_STOPPED" VALUE="false"/>
        <PARAMETER NAME="USE_CLKFB_STOPPED" VALUE="false"/>
        <PARAMETER NAME="RESET_PORT" VALUE="reset"/>
        <PARAMETER NAME="LOCKED_PORT" VALUE="locked"/>
        <PARAMETER NAME="POWER_DOWN_PORT" VALUE="power_down"/>
        <PARAMETER NAME="CLK_VALID_PORT" VALUE="CLK_VALID"/>
        <PARAMETER NAME="STATUS_PORT" VALUE="STATUS"/>
        <PARAMETER NAME="CLK_IN_SEL_PORT" VALUE="clk_in_sel"/>
        <PARAMETER NAME="INPUT_CLK_STOPPED_PORT" VALUE="input_clk_stopped"/>
        <PARAMETER NAME="CLKFB_STOPPED_PORT" VALUE="clkfb_stopped"/>
        <PARAMETER NAME="SS_MODE" VALUE="CENTER_HIGH"/>
        <PARAMETER NAME="SS_MOD_FREQ" VALUE="250"/>
        <PARAMETER NAME="SS_MOD_TIME" VALUE="0.004"/>
        <PARAMETER NAME="OVERRIDE_MMCM" VALUE="false"/>
        <PARAMETER NAME="MMCM_NOTES" VALUE="None"/>
        <PARAMETER NAME="MMCM_DIVCLK_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_BANDWIDTH" VALUE="OPTIMIZED"/>
        <PARAMETER NAME="MMCM_CLKFBOUT_MULT_F" VALUE="4.750"/>
        <PARAMETER NAME="MMCM_CLKFBOUT_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKFBOUT_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKIN1_PERIOD" VALUE="3.906"/>
        <PARAMETER NAME="MMCM_CLKIN2_PERIOD" VALUE="10.0"/>
        <PARAMETER NAME="MMCM_CLKOUT4_CASCADE" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLOCK_HOLD" VALUE="false"/>
        <PARAMETER NAME="MMCM_COMPENSATION" VALUE="AUTO"/>
        <PARAMETER NAME="MMCM_REF_JITTER1" VALUE="0.010"/>
        <PARAMETER NAME="MMCM_REF_JITTER2" VALUE="0.010"/>
        <PARAMETER NAME="MMCM_STARTUP_WAIT" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT0_DIVIDE_F" VALUE="2.375"/>
        <PARAMETER NAME="MMCM_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT0_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT0_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT1_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT1_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT1_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT2_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT2_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT2_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT3_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT3_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT3_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT4_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT4_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT4_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT5_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT5_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT5_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT6_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT6_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT6_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT6_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="OVERRIDE_PLL" VALUE="false"/>
        <PARAMETER NAME="PLL_NOTES" VALUE="None"/>
        <PARAMETER NAME="PLL_BANDWIDTH" VALUE="OPTIMIZED"/>
        <PARAMETER NAME="PLL_CLKFBOUT_MULT" VALUE="4"/>
        <PARAMETER NAME="PLL_CLKFBOUT_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLK_FEEDBACK" VALUE="CLKFBOUT"/>
        <PARAMETER NAME="PLL_DIVCLK_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKIN_PERIOD" VALUE="10.000"/>
        <PARAMETER NAME="PLL_COMPENSATION" VALUE="SYSTEM_SYNCHRONOUS"/>
        <PARAMETER NAME="PLL_REF_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="PLL_CLKOUT0_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT0_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLKOUT1_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT1_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLKOUT2_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT2_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLKOUT3_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT3_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLKOUT4_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT4_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLKOUT5_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT5_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="RESET_TYPE" VALUE="ACTIVE_HIGH"/>
        <PARAMETER NAME="USE_SAFE_CLOCK_STARTUP" VALUE="false"/>
        <PARAMETER NAME="USE_CLOCK_SEQUENCING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT1_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT2_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT3_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT4_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT5_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT6_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT7_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="CLK_IN1_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="CLK_IN2_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="DIFF_CLK_IN1_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="DIFF_CLK_IN2_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="AUTO_PRIMITIVE" VALUE="MMCM"/>
        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="ENABLE_CDDC" VALUE="false"/>
        <PARAMETER NAME="CDDCDONE_PORT" VALUE="cddcdone"/>
        <PARAMETER NAME="CDDCREQ_PORT" VALUE="cddcreq"/>
        <PARAMETER NAME="ENABLE_CLKOUTPHY" VALUE="false"/>
        <PARAMETER NAME="CLKOUTPHY_REQUESTED_FREQ" VALUE="600.000"/>
        <PARAMETER NAME="CLKOUT1_JITTER" VALUE="73.505"/>
        <PARAMETER NAME="CLKOUT1_PHASE_ERROR" VALUE="77.298"/>
        <PARAMETER NAME="CLKOUT2_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT2_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT3_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT3_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT4_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT4_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT5_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT5_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT6_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT6_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT7_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT7_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="INPUT_MODE" VALUE="frequency"/>
        <PARAMETER NAME="INTERFACE_SELECTION" VALUE="Enable_AXI"/>
        <PARAMETER NAME="AXI_DRP" VALUE="false"/>
        <PARAMETER NAME="PHASE_DUTY_CONFIG" VALUE="false"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="reset" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="rst_adc0_peripheral_reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0" PORT="peripheral_reset"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="256000000" DIR="I" NAME="clk_in1" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_adc0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_adc0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="512000000" DIR="O" NAME="clk_out1" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axis_aclk"/>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axis_aclk"/>
            <CONNECTION INSTANCE="axis_broadcaster_0" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_broadcaster_1" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_clock_converter_0" PORT="s_axis_aclk"/>
            <CONNECTION INSTANCE="axis_dwidth_converter_0" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_register_slice_0" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_register_slice_1" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="aclk"/>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axis_aclk"/>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="slowest_sync_clk"/>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="m0_axis_aclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="locked" SIGIS="undef" SIGNAME="clk_adc0_x2_locked">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="dcm_locked"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="10" FULLNAME="/clk_core" HWVERSION="6.0" INSTANCE="clk_core" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="clk_wiz" VLNV="xilinx.com:ip:clk_wiz:6.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=clk_wiz;v=v6_0;d=pg065-clk-wiz.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_CLKOUT2_USED" VALUE="0"/>
        <PARAMETER NAME="C_USER_CLK_FREQ0" VALUE="100.0"/>
        <PARAMETER NAME="C_AUTO_PRIMITIVE" VALUE="MMCM"/>
        <PARAMETER NAME="C_USER_CLK_FREQ1" VALUE="100.0"/>
        <PARAMETER NAME="C_USER_CLK_FREQ2" VALUE="100.0"/>
        <PARAMETER NAME="C_USER_CLK_FREQ3" VALUE="100.0"/>
        <PARAMETER NAME="C_ENABLE_CLOCK_MONITOR" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_USER_CLOCK0" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_USER_CLOCK1" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_USER_CLOCK2" VALUE="0"/>
        <PARAMETER NAME="C_ENABLE_USER_CLOCK3" VALUE="0"/>
        <PARAMETER NAME="C_Enable_PLL0" VALUE="0"/>
        <PARAMETER NAME="C_Enable_PLL1" VALUE="0"/>
        <PARAMETER NAME="C_REF_CLK_FREQ" VALUE="100.0"/>
        <PARAMETER NAME="C_PRECISION" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT3_USED" VALUE="0"/>
        <PARAMETER NAME="C_CLKOUT4_USED" VALUE="0"/>
        <PARAMETER NAME="C_CLKOUT5_USED" VALUE="0"/>
        <PARAMETER NAME="C_CLKOUT6_USED" VALUE="0"/>
        <PARAMETER NAME="C_CLKOUT7_USED" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLKOUT1_BAR" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLKOUT2_BAR" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLKOUT3_BAR" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLKOUT4_BAR" VALUE="0"/>
        <PARAMETER NAME="c_component_name" VALUE="d_1_clk_adc0_x2_1"/>
        <PARAMETER NAME="C_PLATFORM" VALUE="UNKNOWN"/>
        <PARAMETER NAME="C_USE_FREQ_SYNTH" VALUE="1"/>
        <PARAMETER NAME="C_USE_PHASE_ALIGNMENT" VALUE="0"/>
        <PARAMETER NAME="C_PRIM_IN_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="C_SECONDARY_IN_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="C_JITTER_SEL" VALUE="No_Jitter"/>
        <PARAMETER NAME="C_USE_MIN_POWER" VALUE="0"/>
        <PARAMETER NAME="C_USE_MIN_O_JITTER" VALUE="0"/>
        <PARAMETER NAME="C_USE_MAX_I_JITTER" VALUE="0"/>
        <PARAMETER NAME="C_USE_DYN_PHASE_SHIFT" VALUE="0"/>
        <PARAMETER NAME="C_OPTIMIZE_CLOCKING_STRUCTURE_EN" VALUE="1"/>
        <PARAMETER NAME="C_USE_INCLK_SWITCHOVER" VALUE="0"/>
        <PARAMETER NAME="C_USE_DYN_RECONFIG" VALUE="0"/>
        <PARAMETER NAME="C_USE_SPREAD_SPECTRUM" VALUE="0"/>
        <PARAMETER NAME="C_USE_FAST_SIMULATION" VALUE="0"/>
        <PARAMETER NAME="C_PRIMTYPE_SEL" VALUE="AUTO"/>
        <PARAMETER NAME="C_USE_CLK_VALID" VALUE="0"/>
        <PARAMETER NAME="C_PRIM_IN_FREQ" VALUE="99.999"/>
        <PARAMETER NAME="C_PRIM_IN_TIMEPERIOD" VALUE="10.000"/>
        <PARAMETER NAME="C_IN_FREQ_UNITS" VALUE="Units_MHz"/>
        <PARAMETER NAME="C_SECONDARY_IN_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_SECONDARY_IN_TIMEPERIOD" VALUE="10.000"/>
        <PARAMETER NAME="C_FEEDBACK_SOURCE" VALUE="FDBK_AUTO"/>
        <PARAMETER NAME="C_PRIM_SOURCE" VALUE="Global_buffer"/>
        <PARAMETER NAME="C_PHASESHIFT_MODE" VALUE="LATENCY"/>
        <PARAMETER NAME="C_SECONDARY_SOURCE" VALUE="Single_ended_clock_capable_pin"/>
        <PARAMETER NAME="C_CLKFB_IN_SIGNALING" VALUE="SINGLE"/>
        <PARAMETER NAME="C_USE_RESET" VALUE="1"/>
        <PARAMETER NAME="C_RESET_LOW" VALUE="0"/>
        <PARAMETER NAME="C_USE_LOCKED" VALUE="1"/>
        <PARAMETER NAME="C_USE_INCLK_STOPPED" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLKFB_STOPPED" VALUE="0"/>
        <PARAMETER NAME="C_USE_POWER_DOWN" VALUE="0"/>
        <PARAMETER NAME="C_USE_STATUS" VALUE="0"/>
        <PARAMETER NAME="C_USE_FREEZE" VALUE="0"/>
        <PARAMETER NAME="C_NUM_OUT_CLKS" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT1_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT2_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT3_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT4_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT5_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT6_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_CLKOUT7_DRIVES" VALUE="BUFG"/>
        <PARAMETER NAME="C_INCLK_SUM_ROW0" VALUE="Input Clock   Freq (MHz)    Input Jitter (UI)"/>
        <PARAMETER NAME="C_INCLK_SUM_ROW1" VALUE="__primary__________99.999____________0.010"/>
        <PARAMETER NAME="C_INCLK_SUM_ROW2" VALUE="no_secondary_input_clock"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW0A" VALUE="Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW0B" VALUE="Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW1" VALUE="clk_out1__199.99800______0.000______50.0______102.087_____87.181"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW2" VALUE="no_CLK_OUT2_output"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW3" VALUE="no_CLK_OUT3_output"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW4" VALUE="no_CLK_OUT4_output"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW5" VALUE="no_CLK_OUT5_output"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW6" VALUE="no_CLK_OUT6_output"/>
        <PARAMETER NAME="C_OUTCLK_SUM_ROW7" VALUE="no_CLK_OUT7_output"/>
        <PARAMETER NAME="C_CLKOUT1_REQUESTED_OUT_FREQ" VALUE="199.998"/>
        <PARAMETER NAME="C_CLKOUT2_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT3_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT4_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT5_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT6_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT7_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT1_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT2_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT3_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT4_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT5_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT6_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT7_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT1_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT2_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT3_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT4_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT5_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT6_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT7_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT1_OUT_FREQ" VALUE="199.99800"/>
        <PARAMETER NAME="C_CLKOUT2_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT3_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT4_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT5_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT6_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT7_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT1_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT2_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT3_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT4_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT5_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT6_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT7_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLKOUT1_DUTY_CYCLE" VALUE="50.0"/>
        <PARAMETER NAME="C_CLKOUT2_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT3_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT4_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT5_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT6_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_CLKOUT7_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="C_USE_SAFE_CLOCK_STARTUP" VALUE="0"/>
        <PARAMETER NAME="C_USE_CLOCK_SEQUENCING" VALUE="0"/>
        <PARAMETER NAME="C_CLKOUT1_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT2_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT3_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT4_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT5_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT6_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_CLKOUT7_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_NOTES" VALUE="None"/>
        <PARAMETER NAME="C_MMCM_BANDWIDTH" VALUE="OPTIMIZED"/>
        <PARAMETER NAME="C_MMCM_CLKFBOUT_MULT_F" VALUE="12.000"/>
        <PARAMETER NAME="C_MMCM_CLKIN1_PERIOD" VALUE="10.000"/>
        <PARAMETER NAME="C_MMCM_CLKIN2_PERIOD" VALUE="10.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT4_CASCADE" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLOCK_HOLD" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_COMPENSATION" VALUE="AUTO"/>
        <PARAMETER NAME="C_MMCM_DIVCLK_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_REF_JITTER1" VALUE="0.010"/>
        <PARAMETER NAME="C_MMCM_REF_JITTER2" VALUE="0.010"/>
        <PARAMETER NAME="C_MMCM_STARTUP_WAIT" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT0_DIVIDE_F" VALUE="6.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT1_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT2_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT3_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT4_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT5_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT6_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_MMCM_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKOUT6_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_MMCM_CLKFBOUT_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT0_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT1_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT2_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT3_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT4_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT5_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKOUT6_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_MMCM_CLKFBOUT_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT0_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT1_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT2_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT3_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT4_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT5_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_MMCM_CLKOUT6_USE_FINE_PS" VALUE="FALSE"/>
        <PARAMETER NAME="C_PLL_NOTES" VALUE="No notes"/>
        <PARAMETER NAME="C_PLL_BANDWIDTH" VALUE="OPTIMIZED"/>
        <PARAMETER NAME="C_PLL_CLK_FEEDBACK" VALUE="CLKFBOUT"/>
        <PARAMETER NAME="C_PLL_CLKFBOUT_MULT" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKIN_PERIOD" VALUE="1.000"/>
        <PARAMETER NAME="C_PLL_COMPENSATION" VALUE="SYSTEM_SYNCHRONOUS"/>
        <PARAMETER NAME="C_PLL_DIVCLK_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_REF_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="C_PLL_CLKOUT0_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT1_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT2_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT3_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT4_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT5_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="C_PLL_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="C_PLL_CLKFBOUT_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT0_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT1_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT2_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT3_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT4_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_PLL_CLKOUT5_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="C_CLOCK_MGR_TYPE" VALUE="NA"/>
        <PARAMETER NAME="C_OVERRIDE_MMCM" VALUE="0"/>
        <PARAMETER NAME="C_OVERRIDE_PLL" VALUE="0"/>
        <PARAMETER NAME="C_PRIMARY_PORT" VALUE="clk_in1"/>
        <PARAMETER NAME="C_SECONDARY_PORT" VALUE="clk_in2"/>
        <PARAMETER NAME="C_CLK_OUT1_PORT" VALUE="clk_out1"/>
        <PARAMETER NAME="C_CLK_OUT2_PORT" VALUE="clk_out2"/>
        <PARAMETER NAME="C_CLK_OUT3_PORT" VALUE="clk_out3"/>
        <PARAMETER NAME="C_CLK_OUT4_PORT" VALUE="clk_out4"/>
        <PARAMETER NAME="C_CLK_OUT5_PORT" VALUE="clk_out5"/>
        <PARAMETER NAME="C_CLK_OUT6_PORT" VALUE="clk_out6"/>
        <PARAMETER NAME="C_CLK_OUT7_PORT" VALUE="clk_out7"/>
        <PARAMETER NAME="C_RESET_PORT" VALUE="reset"/>
        <PARAMETER NAME="C_LOCKED_PORT" VALUE="locked"/>
        <PARAMETER NAME="C_CLKFB_IN_PORT" VALUE="clkfb_in"/>
        <PARAMETER NAME="C_CLKFB_IN_P_PORT" VALUE="clkfb_in_p"/>
        <PARAMETER NAME="C_CLKFB_IN_N_PORT" VALUE="clkfb_in_n"/>
        <PARAMETER NAME="C_CLKFB_OUT_PORT" VALUE="clkfb_out"/>
        <PARAMETER NAME="C_CLKFB_OUT_P_PORT" VALUE="clkfb_out_p"/>
        <PARAMETER NAME="C_CLKFB_OUT_N_PORT" VALUE="clkfb_out_n"/>
        <PARAMETER NAME="C_POWER_DOWN_PORT" VALUE="power_down"/>
        <PARAMETER NAME="C_DADDR_PORT" VALUE="daddr"/>
        <PARAMETER NAME="C_DCLK_PORT" VALUE="dclk"/>
        <PARAMETER NAME="C_DRDY_PORT" VALUE="drdy"/>
        <PARAMETER NAME="C_DWE_PORT" VALUE="dwe"/>
        <PARAMETER NAME="C_DIN_PORT" VALUE="din"/>
        <PARAMETER NAME="C_DOUT_PORT" VALUE="dout"/>
        <PARAMETER NAME="C_DEN_PORT" VALUE="den"/>
        <PARAMETER NAME="C_PSCLK_PORT" VALUE="psclk"/>
        <PARAMETER NAME="C_PSEN_PORT" VALUE="psen"/>
        <PARAMETER NAME="C_PSINCDEC_PORT" VALUE="psincdec"/>
        <PARAMETER NAME="C_PSDONE_PORT" VALUE="psdone"/>
        <PARAMETER NAME="C_CLK_VALID_PORT" VALUE="CLK_VALID"/>
        <PARAMETER NAME="C_STATUS_PORT" VALUE="STATUS"/>
        <PARAMETER NAME="C_CLK_IN_SEL_PORT" VALUE="clk_in_sel"/>
        <PARAMETER NAME="C_INPUT_CLK_STOPPED_PORT" VALUE="input_clk_stopped"/>
        <PARAMETER NAME="C_CLKFB_STOPPED_PORT" VALUE="clkfb_stopped"/>
        <PARAMETER NAME="C_CLKIN1_JITTER_PS" VALUE="100.0"/>
        <PARAMETER NAME="C_CLKIN2_JITTER_PS" VALUE="100.0"/>
        <PARAMETER NAME="C_PRIMITIVE" VALUE="MMCM"/>
        <PARAMETER NAME="C_SS_MODE" VALUE="CENTER_HIGH"/>
        <PARAMETER NAME="C_SS_MOD_PERIOD" VALUE="4000"/>
        <PARAMETER NAME="C_SS_MOD_TIME" VALUE="0.004"/>
        <PARAMETER NAME="C_HAS_CDDC" VALUE="0"/>
        <PARAMETER NAME="C_CDDCDONE_PORT" VALUE="cddcdone"/>
        <PARAMETER NAME="C_CDDCREQ_PORT" VALUE="cddcreq"/>
        <PARAMETER NAME="C_CLKOUTPHY_MODE" VALUE="VCO"/>
        <PARAMETER NAME="C_ENABLE_CLKOUTPHY" VALUE="0"/>
        <PARAMETER NAME="C_INTERFACE_SELECTION" VALUE="0"/>
        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="11"/>
        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_POWER_REG" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT0_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT0_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT1_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT1_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT2_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT2_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT3_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT3_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT4_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT4_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT5_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT5_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT6_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKOUT6_2" VALUE="0000"/>
        <PARAMETER NAME="C_CLKFBOUT_1" VALUE="0000"/>
        <PARAMETER NAME="C_CLKFBOUT_2" VALUE="0000"/>
        <PARAMETER NAME="C_DIVCLK" VALUE="0000"/>
        <PARAMETER NAME="C_LOCK_1" VALUE="0000"/>
        <PARAMETER NAME="C_LOCK_2" VALUE="0000"/>
        <PARAMETER NAME="C_LOCK_3" VALUE="0000"/>
        <PARAMETER NAME="C_FILTER_1" VALUE="0000"/>
        <PARAMETER NAME="C_FILTER_2" VALUE="0000"/>
        <PARAMETER NAME="C_DIVIDE1_AUTO" VALUE="1"/>
        <PARAMETER NAME="C_DIVIDE2_AUTO" VALUE="0.16666666666666666"/>
        <PARAMETER NAME="C_DIVIDE3_AUTO" VALUE="0.16666666666666666"/>
        <PARAMETER NAME="C_DIVIDE4_AUTO" VALUE="0.16666666666666666"/>
        <PARAMETER NAME="C_DIVIDE5_AUTO" VALUE="0.16666666666666666"/>
        <PARAMETER NAME="C_DIVIDE6_AUTO" VALUE="0.16666666666666666"/>
        <PARAMETER NAME="C_DIVIDE7_AUTO" VALUE="0.16666666666666666"/>
        <PARAMETER NAME="C_PLLBUFGCEDIV" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV" VALUE="false"/>
        <PARAMETER NAME="C_PLLBUFGCEDIV1" VALUE="false"/>
        <PARAMETER NAME="C_PLLBUFGCEDIV2" VALUE="false"/>
        <PARAMETER NAME="C_PLLBUFGCEDIV3" VALUE="false"/>
        <PARAMETER NAME="C_PLLBUFGCEDIV4" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV1" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV2" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV3" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV4" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV5" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV6" VALUE="false"/>
        <PARAMETER NAME="C_MMCMBUFGCEDIV7" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT1_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT2_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT3_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT4_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT5_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT6_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT7_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="C_CLKOUT0_ACTUAL_FREQ" VALUE="199.99800"/>
        <PARAMETER NAME="C_CLKOUT1_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT2_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT3_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT4_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT5_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_CLKOUT6_ACTUAL_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="C_M_MAX" VALUE="128.000"/>
        <PARAMETER NAME="C_M_MIN" VALUE="2.000"/>
        <PARAMETER NAME="C_D_MAX" VALUE="93.000"/>
        <PARAMETER NAME="C_D_MIN" VALUE="1.000"/>
        <PARAMETER NAME="C_O_MAX" VALUE="128.000"/>
        <PARAMETER NAME="C_O_MIN" VALUE="1.000"/>
        <PARAMETER NAME="C_VCO_MIN" VALUE="800.000"/>
        <PARAMETER NAME="C_VCO_MAX" VALUE="1600.000"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_clk_adc0_x2_1"/>
        <PARAMETER NAME="USER_CLK_FREQ0" VALUE="100.0"/>
        <PARAMETER NAME="USER_CLK_FREQ1" VALUE="100.0"/>
        <PARAMETER NAME="USER_CLK_FREQ2" VALUE="100.0"/>
        <PARAMETER NAME="USER_CLK_FREQ3" VALUE="100.0"/>
        <PARAMETER NAME="ENABLE_CLOCK_MONITOR" VALUE="false"/>
        <PARAMETER NAME="OPTIMIZE_CLOCKING_STRUCTURE_EN" VALUE="true"/>
        <PARAMETER NAME="ENABLE_USER_CLOCK0" VALUE="false"/>
        <PARAMETER NAME="ENABLE_USER_CLOCK1" VALUE="false"/>
        <PARAMETER NAME="ENABLE_USER_CLOCK2" VALUE="false"/>
        <PARAMETER NAME="ENABLE_USER_CLOCK3" VALUE="false"/>
        <PARAMETER NAME="Enable_PLL0" VALUE="false"/>
        <PARAMETER NAME="Enable_PLL1" VALUE="false"/>
        <PARAMETER NAME="REF_CLK_FREQ" VALUE="100.0"/>
        <PARAMETER NAME="PRECISION" VALUE="1"/>
        <PARAMETER NAME="PRIMITIVE" VALUE="MMCM"/>
        <PARAMETER NAME="PRIMTYPE_SEL" VALUE="mmcm_adv"/>
        <PARAMETER NAME="CLOCK_MGR_TYPE" VALUE="auto"/>
        <PARAMETER NAME="USE_FREQ_SYNTH" VALUE="true"/>
        <PARAMETER NAME="USE_SPREAD_SPECTRUM" VALUE="false"/>
        <PARAMETER NAME="USE_PHASE_ALIGNMENT" VALUE="false"/>
        <PARAMETER NAME="USE_MIN_POWER" VALUE="false"/>
        <PARAMETER NAME="USE_DYN_PHASE_SHIFT" VALUE="false"/>
        <PARAMETER NAME="USE_DYN_RECONFIG" VALUE="false"/>
        <PARAMETER NAME="JITTER_SEL" VALUE="No_Jitter"/>
        <PARAMETER NAME="PRIM_IN_FREQ" VALUE="99.999"/>
        <PARAMETER NAME="PRIM_IN_TIMEPERIOD" VALUE="10.000"/>
        <PARAMETER NAME="IN_FREQ_UNITS" VALUE="Units_MHz"/>
        <PARAMETER NAME="PHASESHIFT_MODE" VALUE="LATENCY"/>
        <PARAMETER NAME="IN_JITTER_UNITS" VALUE="Units_UI"/>
        <PARAMETER NAME="RELATIVE_INCLK" VALUE="REL_PRIMARY"/>
        <PARAMETER NAME="USE_INCLK_SWITCHOVER" VALUE="false"/>
        <PARAMETER NAME="SECONDARY_IN_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="SECONDARY_IN_TIMEPERIOD" VALUE="10.000"/>
        <PARAMETER NAME="SECONDARY_PORT" VALUE="clk_in2"/>
        <PARAMETER NAME="SECONDARY_SOURCE" VALUE="Single_ended_clock_capable_pin"/>
        <PARAMETER NAME="JITTER_OPTIONS" VALUE="UI"/>
        <PARAMETER NAME="CLKIN1_UI_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="CLKIN2_UI_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="PRIM_IN_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="SECONDARY_IN_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="CLKIN1_JITTER_PS" VALUE="100.0"/>
        <PARAMETER NAME="CLKIN2_JITTER_PS" VALUE="100.0"/>
        <PARAMETER NAME="CLKOUT1_USED" VALUE="true"/>
        <PARAMETER NAME="CLKOUT2_USED" VALUE="false"/>
        <PARAMETER NAME="CLKOUT3_USED" VALUE="false"/>
        <PARAMETER NAME="CLKOUT4_USED" VALUE="false"/>
        <PARAMETER NAME="CLKOUT5_USED" VALUE="false"/>
        <PARAMETER NAME="CLKOUT6_USED" VALUE="false"/>
        <PARAMETER NAME="CLKOUT7_USED" VALUE="false"/>
        <PARAMETER NAME="NUM_OUT_CLKS" VALUE="1"/>
        <PARAMETER NAME="CLK_OUT1_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT2_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT3_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT4_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT5_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT6_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="CLK_OUT7_USE_FINE_PS_GUI" VALUE="false"/>
        <PARAMETER NAME="PRIMARY_PORT" VALUE="clk_in1"/>
        <PARAMETER NAME="CLK_OUT1_PORT" VALUE="clk_out1"/>
        <PARAMETER NAME="CLK_OUT2_PORT" VALUE="clk_out2"/>
        <PARAMETER NAME="CLK_OUT3_PORT" VALUE="clk_out3"/>
        <PARAMETER NAME="CLK_OUT4_PORT" VALUE="clk_out4"/>
        <PARAMETER NAME="CLK_OUT5_PORT" VALUE="clk_out5"/>
        <PARAMETER NAME="CLK_OUT6_PORT" VALUE="clk_out6"/>
        <PARAMETER NAME="CLK_OUT7_PORT" VALUE="clk_out7"/>
        <PARAMETER NAME="DADDR_PORT" VALUE="daddr"/>
        <PARAMETER NAME="DCLK_PORT" VALUE="dclk"/>
        <PARAMETER NAME="DRDY_PORT" VALUE="drdy"/>
        <PARAMETER NAME="DWE_PORT" VALUE="dwe"/>
        <PARAMETER NAME="DIN_PORT" VALUE="din"/>
        <PARAMETER NAME="DOUT_PORT" VALUE="dout"/>
        <PARAMETER NAME="DEN_PORT" VALUE="den"/>
        <PARAMETER NAME="PSCLK_PORT" VALUE="psclk"/>
        <PARAMETER NAME="PSEN_PORT" VALUE="psen"/>
        <PARAMETER NAME="PSINCDEC_PORT" VALUE="psincdec"/>
        <PARAMETER NAME="PSDONE_PORT" VALUE="psdone"/>
        <PARAMETER NAME="CLKOUT1_REQUESTED_OUT_FREQ" VALUE="199.998"/>
        <PARAMETER NAME="CLKOUT1_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT1_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT2_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT2_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT2_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT3_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT3_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT3_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT4_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT4_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT4_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT5_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT5_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT5_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT6_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT6_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT6_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="CLKOUT7_REQUESTED_OUT_FREQ" VALUE="100.000"/>
        <PARAMETER NAME="CLKOUT7_REQUESTED_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="CLKOUT7_REQUESTED_DUTY_CYCLE" VALUE="50.000"/>
        <PARAMETER NAME="USE_MAX_I_JITTER" VALUE="false"/>
        <PARAMETER NAME="USE_MIN_O_JITTER" VALUE="false"/>
        <PARAMETER NAME="CLKOUT1_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT2_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT3_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT4_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT5_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT6_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT7_MATCHED_ROUTING" VALUE="false"/>
        <PARAMETER NAME="PRIM_SOURCE" VALUE="Global_buffer"/>
        <PARAMETER NAME="CLKOUT1_DRIVES" VALUE="Buffer"/>
        <PARAMETER NAME="CLKOUT2_DRIVES" VALUE="Buffer"/>
        <PARAMETER NAME="CLKOUT3_DRIVES" VALUE="Buffer"/>
        <PARAMETER NAME="CLKOUT4_DRIVES" VALUE="Buffer"/>
        <PARAMETER NAME="CLKOUT5_DRIVES" VALUE="Buffer"/>
        <PARAMETER NAME="CLKOUT6_DRIVES" VALUE="Buffer"/>
        <PARAMETER NAME="CLKOUT7_DRIVES" VALUE="Buffer"/>
        <PARAMETER NAME="FEEDBACK_SOURCE" VALUE="FDBK_AUTO"/>
        <PARAMETER NAME="CLKFB_IN_SIGNALING" VALUE="SINGLE"/>
        <PARAMETER NAME="CLKFB_IN_PORT" VALUE="clkfb_in"/>
        <PARAMETER NAME="CLKFB_IN_P_PORT" VALUE="clkfb_in_p"/>
        <PARAMETER NAME="CLKFB_IN_N_PORT" VALUE="clkfb_in_n"/>
        <PARAMETER NAME="CLKFB_OUT_PORT" VALUE="clkfb_out"/>
        <PARAMETER NAME="CLKFB_OUT_P_PORT" VALUE="clkfb_out_p"/>
        <PARAMETER NAME="CLKFB_OUT_N_PORT" VALUE="clkfb_out_n"/>
        <PARAMETER NAME="PLATFORM" VALUE="UNKNOWN"/>
        <PARAMETER NAME="SUMMARY_STRINGS" VALUE="empty"/>
        <PARAMETER NAME="USE_LOCKED" VALUE="true"/>
        <PARAMETER NAME="CALC_DONE" VALUE="empty"/>
        <PARAMETER NAME="USE_RESET" VALUE="true"/>
        <PARAMETER NAME="USE_POWER_DOWN" VALUE="false"/>
        <PARAMETER NAME="USE_STATUS" VALUE="false"/>
        <PARAMETER NAME="USE_FREEZE" VALUE="false"/>
        <PARAMETER NAME="USE_CLK_VALID" VALUE="false"/>
        <PARAMETER NAME="USE_INCLK_STOPPED" VALUE="false"/>
        <PARAMETER NAME="USE_CLKFB_STOPPED" VALUE="false"/>
        <PARAMETER NAME="RESET_PORT" VALUE="reset"/>
        <PARAMETER NAME="LOCKED_PORT" VALUE="locked"/>
        <PARAMETER NAME="POWER_DOWN_PORT" VALUE="power_down"/>
        <PARAMETER NAME="CLK_VALID_PORT" VALUE="CLK_VALID"/>
        <PARAMETER NAME="STATUS_PORT" VALUE="STATUS"/>
        <PARAMETER NAME="CLK_IN_SEL_PORT" VALUE="clk_in_sel"/>
        <PARAMETER NAME="INPUT_CLK_STOPPED_PORT" VALUE="input_clk_stopped"/>
        <PARAMETER NAME="CLKFB_STOPPED_PORT" VALUE="clkfb_stopped"/>
        <PARAMETER NAME="SS_MODE" VALUE="CENTER_HIGH"/>
        <PARAMETER NAME="SS_MOD_FREQ" VALUE="250"/>
        <PARAMETER NAME="SS_MOD_TIME" VALUE="0.004"/>
        <PARAMETER NAME="OVERRIDE_MMCM" VALUE="false"/>
        <PARAMETER NAME="MMCM_NOTES" VALUE="None"/>
        <PARAMETER NAME="MMCM_DIVCLK_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_BANDWIDTH" VALUE="OPTIMIZED"/>
        <PARAMETER NAME="MMCM_CLKFBOUT_MULT_F" VALUE="12.000"/>
        <PARAMETER NAME="MMCM_CLKFBOUT_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKFBOUT_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKIN1_PERIOD" VALUE="10.000"/>
        <PARAMETER NAME="MMCM_CLKIN2_PERIOD" VALUE="10.000"/>
        <PARAMETER NAME="MMCM_CLKOUT4_CASCADE" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLOCK_HOLD" VALUE="false"/>
        <PARAMETER NAME="MMCM_COMPENSATION" VALUE="AUTO"/>
        <PARAMETER NAME="MMCM_REF_JITTER1" VALUE="0.010"/>
        <PARAMETER NAME="MMCM_REF_JITTER2" VALUE="0.010"/>
        <PARAMETER NAME="MMCM_STARTUP_WAIT" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT0_DIVIDE_F" VALUE="6.000"/>
        <PARAMETER NAME="MMCM_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT0_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT0_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT1_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT1_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT1_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT2_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT2_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT2_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT3_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT3_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT3_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT4_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT4_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT4_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT5_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT5_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT5_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="MMCM_CLKOUT6_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="MMCM_CLKOUT6_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="MMCM_CLKOUT6_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="MMCM_CLKOUT6_USE_FINE_PS" VALUE="false"/>
        <PARAMETER NAME="OVERRIDE_PLL" VALUE="false"/>
        <PARAMETER NAME="PLL_NOTES" VALUE="None"/>
        <PARAMETER NAME="PLL_BANDWIDTH" VALUE="OPTIMIZED"/>
        <PARAMETER NAME="PLL_CLKFBOUT_MULT" VALUE="4"/>
        <PARAMETER NAME="PLL_CLKFBOUT_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLK_FEEDBACK" VALUE="CLKFBOUT"/>
        <PARAMETER NAME="PLL_DIVCLK_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKIN_PERIOD" VALUE="10.000"/>
        <PARAMETER NAME="PLL_COMPENSATION" VALUE="SYSTEM_SYNCHRONOUS"/>
        <PARAMETER NAME="PLL_REF_JITTER" VALUE="0.010"/>
        <PARAMETER NAME="PLL_CLKOUT0_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT0_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT0_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLKOUT1_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT1_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT1_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLKOUT2_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT2_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT2_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLKOUT3_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT3_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT3_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLKOUT4_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT4_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT4_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="PLL_CLKOUT5_DIVIDE" VALUE="1"/>
        <PARAMETER NAME="PLL_CLKOUT5_DUTY_CYCLE" VALUE="0.500"/>
        <PARAMETER NAME="PLL_CLKOUT5_PHASE" VALUE="0.000"/>
        <PARAMETER NAME="RESET_TYPE" VALUE="ACTIVE_HIGH"/>
        <PARAMETER NAME="USE_SAFE_CLOCK_STARTUP" VALUE="false"/>
        <PARAMETER NAME="USE_CLOCK_SEQUENCING" VALUE="false"/>
        <PARAMETER NAME="CLKOUT1_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT2_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT3_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT4_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT5_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT6_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="CLKOUT7_SEQUENCE_NUMBER" VALUE="1"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="CLK_IN1_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="CLK_IN2_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="DIFF_CLK_IN1_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="DIFF_CLK_IN2_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="AUTO_PRIMITIVE" VALUE="MMCM"/>
        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="ENABLE_CDDC" VALUE="false"/>
        <PARAMETER NAME="CDDCDONE_PORT" VALUE="cddcdone"/>
        <PARAMETER NAME="CDDCREQ_PORT" VALUE="cddcreq"/>
        <PARAMETER NAME="ENABLE_CLKOUTPHY" VALUE="false"/>
        <PARAMETER NAME="CLKOUTPHY_REQUESTED_FREQ" VALUE="600.000"/>
        <PARAMETER NAME="CLKOUT1_JITTER" VALUE="102.087"/>
        <PARAMETER NAME="CLKOUT1_PHASE_ERROR" VALUE="87.181"/>
        <PARAMETER NAME="CLKOUT2_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT2_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT3_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT3_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT4_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT4_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT5_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT5_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT6_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT6_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT7_JITTER" VALUE="0.0"/>
        <PARAMETER NAME="CLKOUT7_PHASE_ERROR" VALUE="0.0"/>
        <PARAMETER NAME="INPUT_MODE" VALUE="frequency"/>
        <PARAMETER NAME="INTERFACE_SELECTION" VALUE="Enable_AXI"/>
        <PARAMETER NAME="AXI_DRP" VALUE="false"/>
        <PARAMETER NAME="PHASE_DUTY_CONFIG" VALUE="false"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="reset" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="rst_100_peripheral_reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_reset"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="clk_in1" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="199998000" DIR="O" NAME="clk_out1" SIGIS="clk" SIGNAME="clk_core_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_core" PORT="slowest_sync_clk"/>
            <CONNECTION INSTANCE="qick_processor_0" PORT="c_clk_i"/>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_1" PORT="m_axis_aclk"/>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_0" PORT="m_axis_aclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="locked" SIGIS="undef" SIGNAME="clk_core_locked">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_core" PORT="dcm_locked"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="25" FULLNAME="/dac_bias_spi" HWVERSION="3.2" INSTANCE="dac_bias_spi" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_quad_spi" VLNV="xilinx.com:ip:axi_quad_spi:3.2">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_quad_spi;v=v3_2;d=pg153-axi-quad-spi.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="AXI_LITE" NAME="Reg" RANGE="4096" USAGE="register">
          <REGISTERS>
            <REGISTER NAME="XIP_Config_Reg">
              <PROPERTY NAME="DESCRIPTION" VALUE="XIP Configuration Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x60"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="CPHA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPHA&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="XIP_Status_Reg">
              <PROPERTY NAME="DESCRIPTION" VALUE="XIP Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x64"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x1"/>
              <FIELDS>
                <FIELD NAME="RX_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receiver Empty.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="RX_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receiver Full.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Master_MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Master mode fault. This bit is set to 1 if the spisel line is deasserted.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA Error.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="AXI_Transaction_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="AXI Transaction Error.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SRR">
              <PROPERTY NAME="DESCRIPTION" VALUE="Software Reset Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x40"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="The only allowed operation on this register is a write of 0x0000000a, which resets the AXI Quad SPI core.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPICR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x60"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x180"/>
              <FIELDS>
                <FIELD NAME="LOOP">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Local loopback mode&#xA;Enables local loopback operation and is functional only in standard SPI master mode.&#xA;When set to:   0 - Normal operation.   1 - Loopback mode. The transmitter output is internally connected to the receiver input. The receiver and transmitter operate normally, except that received data (from remote slave) is ignored.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SPE">
                  <PROPERTY NAME="DESCRIPTION" VALUE="SPI system enable&#xA;When set to:&#xA;  0 - SPI system disabled. Both master and slave outputs are in 3-state and slave inputs are ignored.&#xA;  1 - SPI system enabled. Master outputs active (for example, IO0 (MOSI) and SCK in idle state) and slave outputs become active if SS becomes asserted. The master starts transferring when transmit data is available.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Master">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Master (SPI master mode)&#xA;Setting this bit configures the SPI device as a master or a slave.&#xA;When set to:&#xA;  0 - Slave configuration.&#xA;  1 - Master configuration.&#xA;In dual/quad SPI mode only the master mode of the core is allowed.&#xA;Standard Slave mode is not supported for SCK ratio = 2&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Clock polarity&#xA;Setting this bit defines clock polarity.&#xA;When set to:&#xA;  0 - Active-High clock; SCK idles Low.&#xA;  1 - Active-Low clock; SCK idles High.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPHA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Clock phase&#xA;Setting this bit selects one of two fundamentally different transfer formats.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_FIFO_Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit FIFO reset&#xA;When written to 1, this bit forces a reset of the transmit FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0.&#xA;When set to:   0 - Transmit FIFO normal operation.   1 - Reset transmit FIFO pointer&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="RX_FIFO_Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive FIFO reset&#xA;When written to 1, this bit forces a reset of the receive FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0.&#xA;When set to:   0 - Receive FIFO normal operation.   1 - Reset receive FIFO pointer.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Manual_Slave_Select_Assertion_Enable">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Manual slave select assertion enable&#xA;This bit forces the data in the slave select register to be asserted on the slave select output anytime the device is configured as a master and the device is enabled (SPE asserted).&#xA;This bit has no effect on slave operation.&#xA;When set to:   0 - Slave select output asserted by master core logic.   1 - Slave select output follows data in slave select register. The manual slave assertion mode is supported in standard SPI mode only.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Master_Transaction_Inhibit">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Master transaction inhibit&#xA;This bit inhibits master transactions.&#xA;This bit has no effect on slave operation.&#xA;When set to:   0 - Master transactions enabled.   1 - Master transactions disabled. This bit immediately inhibits the transaction. Setting this bit while transfer is in progress would result in unpredictable outcome&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="LSB_First">
                  <PROPERTY NAME="DESCRIPTION" VALUE="LSB first&#xA;This bit selects LSB first data transfer format.&#xA;The default transfer format is MSB first.&#xA;When set to:&#xA;  0 - MSB first transfer format.&#xA;  1 - LSB first transfer format.&#xA;In Dual/Quad SPI mode, only the MSB first mode of the core is allowed.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPISR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x64"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0A5"/>
              <FIELDS>
                <FIELD NAME="RX_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive Empty.&#xA;When a receive FIFO exists, this bit is set High when the receive FIFO is empty. The occupancy of the FIFO is decremented with each FIFO read operation.&#xA;Note: When FIFOs do not exist, this bit is set High when the receive register has been read (this option is available only in standard SPI mode). This bit is cleared at the end of a successful SPI transfer. For dual/quad SPI mode, the FIFO is always present in the core.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="RX_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive full.&#xA;When a receive FIFO exists, this bit is set High when the receive FIFO is full. The occupancy of the FIFO is incremented with the completion of each SPI transaction.&#xA;Note: When FIFOs do not exist, this bit is set High when an SPI transfer has completed (this option is available only in standard SPI mode). Rx_Empty and Rx_Full are complements in this case&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit empty.&#xA;When a transmit FIFO exists, this bit is set to High when the transmit FIFO is empty. This bit goes High as soon as the TX FIFO becomes empty. While this bit is High, the last byte of the data that is to be transmitted would still be in the pipeline.&#xA;The occupancy of the FIFO is decremented with the completion of each SPI transfer.&#xA;Note: When FIFOs do not exist, this bit is set with the completion of an SPI transfer (this option is available only in standard SPI mode). Either with or without FIFOs, this bit is cleared on an AXI write to the FIFO or transmit register. For Dual/Quad SPI mode, the FIFO is always present in the core.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit full.&#xA;When a transmit FIFO exists, this bit is set High when the transmit FIFO is full.&#xA;Note: When FIFOs do not exist, this bit is set High when an AXI write to the transmit register has been made (this option is available only in standard SPI mode). This bit is cleared when the SPI transfer is completed&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Mode-fault error flag.&#xA;This flag is set if the SS signal goes active while the SPI device is configured as a master. MODF is automatically cleared by reading the SPISR. &#xA;A Low-to-High MODF transition generates a single-cycle strobe interrupt.   0 - No error.   1 - Error condition detected&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Mode_Select">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave_Mode_Select flag.&#xA;This flag is asserted when the core is configured in slave mode. Slave_Mode_Select is activated as soon as the master SPI core asserts the chip select pin for the core.&#xA;1 - Default in standard mode.&#xA;0 - Asserted when core configured in slave mode and selected by external SPI master.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA_Error flag.&#xA;When set to:   0 - Default.   1 - The CPOL and CPHA are set to 01 or 10. When the SPI memory is chosen as either Winbond, Micron or Spansion, and CPOL and CPHA are configured as 01 or 10, this bit is set.&#xA;These memories support CPOL=CPHA mode in 00 or in 11 mode. CPOL_CPHA_Error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_mode_error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave mode error flag.&#xA;When set to:   1 - This bit is set when the core is configured with dual or quad SPI mode and the master is set to 0 in the control register (SPICR).   0 - Master mode is set in the control register (SPICR). Note: Quad SPI mode, only the master mode of the core is allowed. Slave mode error flag is only applicable when the core is configured either in dual or qu ad mode in legacy or enhanced AXI4 mode interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MSB_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="MSB error flag.&#xA;When set to:   0 - Default.   1 - This bit is set when the core is configured to transfer the SPI transactions in either dual or quad SPI mode and LSB first bit is set in the control register (SPICR). Note: In dual/quad SPI mode, only the MSB first mode of the core is allowed. MSB error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Loopback_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Loopback error flag.&#xA;When set to:   0 - Default. The loopback bit in the control register is at default state.   1 - When the SPI command, address, and data bits are set to be transferred in other than standard SPI protocol mode and this bit is set in control register (SPICR). Note: Loopback is only allowed when the core is configured in standard mode. Other modes setting of the bit causes an error and the interrupt bit is set in legacy or enhanced mode AXI4 interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Command_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Command error flag.&#xA;When set to:   0 - Default.   1 - When the core is configured in dual/quad SPI mode and the first entry in the SPI DTR FIFO (after reset) do not match with the supported command list for the particular memory, this bit is set. Note: Command error is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_SSR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Slave Select Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x70"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0xFFFF"/>
              <FIELDS>
                <FIELD NAME="Selected_Slave">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Active-Low, one-hot encoded slave select&#xA;The slaves are numbered right to left starting at zero with the LSB. The slave numbers correspond to the indexes of signal SS&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_TXFIFO_OR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Transmit FIFO Occupancy Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x74"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Occupancy_Value">
                  <PROPERTY NAME="DESCRIPTION" VALUE="The binary value plus 1 yields the occupancy.&#xA;Bit width is log(FIFO Depth). &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_RXFIFO_OR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Receive FIFO Occupancy Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x78"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Occupancy_Value">
                  <PROPERTY NAME="DESCRIPTION" VALUE="The binary value plus 1 yields the occupancy. &#xA;Bit width is log(FIFO Depth). &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="DGIER">
              <PROPERTY NAME="DESCRIPTION" VALUE="Device Global Interrupt Enable Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="GIE">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Global Interrupt Enable.&#xA;Allows passing all individually enabled interrupts to the interrupt controller.&#xA;When set to:   0 - Disabled.   1 - Enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="31"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="31"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_DTR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Data Transmit Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x68"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="TX_Data">
                  <PROPERTY NAME="DESCRIPTION" VALUE="SPI Transmit Data.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_DRR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Data Receive Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x6C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="RX_Data">
                  <PROPERTY NAME="DESCRIPTION" VALUE="SPI Receive Data&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IPISR">
              <PROPERTY NAME="DESCRIPTION" VALUE="IP Interrupt Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x20"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Mode-fault error.&#xA;This interrupt is generated if the SS signal goes active while the SPI device is configured as a master. This bit is set immediately on SS going active.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave mode-fault error.&#xA;This interrupt is generated if the SS signal goes active while the SPI device is configured as a slave, but is not enabled.&#xA;This bit is set immediately on SS going active and continually set if SS is active and the device is not enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit register/FIFO empty.&#xA;It is set when the last byte of data has been transferred out to the external flash memory.&#xA;In the context of the M68HC11 reference manual, when configured without FIFOs, this interrupt is equivalent in information content to the complement of the SPI transfer complete flag (SPIF ) interrupt bit.&#xA;In master mode if this bit is set to 1, no more SPI transfers are permitted&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Underrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit register/FIFO underrun.&#xA;This bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register when data is requested from an empty transmit register/FIFO by the SPI core logic to perform a SPI transfer.&#xA;This can occur only when the SPI device is configured as a slave in standard SPI configuration and is enabled by the SPE bit as set. All zeros are loaded in the shift register and transmitted by the slave in an under-run condition&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data receive register/FIFO full.&#xA;Without FIFOs, this bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register (An element can be a byte, half-word, or word depending on the value of Transfer Width).&#xA;With FIFOs, this bit is set at the end of the SPI element transfer, when the receive FIFO has been completely filled by a one-clock period strobe to the interrupt register.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Overrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data receive register/FIFO overrun.&#xA;This bit is set by a one-clock period strobe to the interrupt register when an attempt to write data to a full receive register or FIFO is made by the SPI core logic to complete a SPI transfer.&#xA;This can occur when the SPI device is in either master or slave mode (in standard SPI mode) or if the IP is configured in SPI master mode (dual or quad SPI mode).&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TXFIFO_Half_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit FIFO half empty.&#xA;In standard SPI configuration, IPISR Bit[6] is the transmit FIFO half-empty interrupt. &#xA;In dual or quad SPI configuration, based on the FIFO depth, this bit is set at half-empty condition.&#xA;Note: This interrupt exists only if the AXI Quad SPI core is configured with FIFOs (In standard, dual or quad SPI mode).&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Select_Mode">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave select mode.&#xA;The assertion of this bit is applicable only when the core is configured in slave mode in standard SPI configuration. &#xA;This bit is set when the other SPI master core selects the core by asserting the slave select line. This bit is set by a one-clock period strobe to the interrupt register.&#xA;Note: This bit is applicable only in standard SPI slave mode&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Not_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DRR not empty.&#xA;The assertion of this bit is applicable only in the case where FIFO Depth is 16 or 256 and the core is configured in slave mode and standard SPI mode. This bit is set when the DRR FIFO receives the first data value during the SPI transaction.&#xA;This bit is set by a one-clock period strobe to the interrupt register when the core receives the first data beat.&#xA;Note: The assertion of this bit is applicable only when the FIFO Depth parameter is 16 or 256 and the core is configured in slave mode in standard SPI mode. When FIFO Depth is set to 0, this bit always returns 0. This bit has no significance in dual/quad mode&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA error.&#xA;This flag is asserted when:&#xA;  The core is configured in either dual or quad SPI mode and&#xA;  The CPOL - CPHA control register bits are set to 01 or 10.&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Mode_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="I/O mode instruction error.&#xA;This flag is asserted when:&#xA;  The core is configured in either dual or quad SPI mode and&#xA;  The core is configured in master = 0 in control register (SPICR(2)).&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MSB_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="MSB error.&#xA;This flag is asserted when:&#xA;  The core is configured in either dual or quad SPI mode and&#xA;  The LSB First bit in the control register (SPICR) is set to 1.&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Loopback_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Loopback error.&#xA;This flag is asserted when:&#xA;  The core is configured in dual or quad SPI transfer mode and&#xA;  The LOOP bit is set in control register (SPICR(0)).&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Command_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Command error.&#xA;This flag is asserted when:   The core is configured in dual/quad SPI mode and   The first entry in the SPI DTR FIFO (after reset) does not match with the supported command list for particular memory. When the SPI command in DTR FIFO does not match with the internal supported command list, the core completes the SPI transactions in standard SPI format. This bit is set to show this behavior of the core.&#xA;In standard SPI mode this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IPIER">
              <PROPERTY NAME="DESCRIPTION" VALUE="IP Interrupt Enable Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x28"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Mode-fault error flag.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave mode-fault error flag.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit register/FIFO empty.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Underrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit FIFO underrun.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data receive register/FIFO full.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Overrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive FIFO overrun.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_FIFO_Half_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit FIFO half empty.   0 - Disabled.   1 - Enabled. Note: This bit is meaningful only if the AXI Quad SPI core is configured with FIFOs.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Select_Mode">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave_Select_Mode.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in slave mode by selecting the active-Low status on spisel.&#xA;In master mode, setting this bit has no effect.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Not_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DRR_Not_Empty.   0 - Disabled.   1 - Enabled. Note: The setting of this bit is applicable only when FIFO Depth is set to 1 and the core is configured in slave mode of standard SPI mode.&#xA;If FIFO Depth is set to 0, the setting of this bit has no effect. This is allowed only in standard SPI configuration. It means this bit is not set in the IPIER register. Therefore, this bit should only be used when FIFO Depth is set to 1 and when the core is configured in slave mode.&#xA;This bit has no significance in dual or quad mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Mode_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="I/O mode instruction error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MSB_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="MSB_Error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Loopback_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Loopback Error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Command_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Command_Error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
          </REGISTERS>
        </ADDRESSBLOCK>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="Async_Clk" VALUE="0"/>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_SELECT_XPM" VALUE="0"/>
        <PARAMETER NAME="C_SUB_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_INSTANCE" VALUE="axi_quad_spi_inst"/>
        <PARAMETER NAME="C_SPI_MEM_ADDR_BITS" VALUE="24"/>
        <PARAMETER NAME="C_TYPE_OF_AXI4_INTERFACE" VALUE="0"/>
        <PARAMETER NAME="C_XIP_MODE" VALUE="0"/>
        <PARAMETER NAME="C_XIP_PERF_MODE" VALUE="1"/>
        <PARAMETER NAME="C_BYTE_LEVEL_INTERRUPT_EN" VALUE="0"/>
        <PARAMETER NAME="C_UC_FAMILY" VALUE="1"/>
        <PARAMETER NAME="C_FIFO_DEPTH" VALUE="16"/>
        <PARAMETER NAME="C_SCK_RATIO" VALUE="16"/>
        <PARAMETER NAME="C_DUAL_QUAD_MODE" VALUE="0"/>
        <PARAMETER NAME="C_NUM_SS_BITS" VALUE="4"/>
        <PARAMETER NAME="C_NUM_TRANSFER_BITS" VALUE="8"/>
        <PARAMETER NAME="C_NEW_SEQ_EN" VALUE="1"/>
        <PARAMETER NAME="C_SPI_MODE" VALUE="0"/>
        <PARAMETER NAME="C_USE_STARTUP" VALUE="0"/>
        <PARAMETER NAME="C_USE_STARTUP_EXT" VALUE="0"/>
        <PARAMETER NAME="C_SPI_MEMORY" VALUE="1"/>
        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="7"/>
        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXI4_ADDR_WIDTH" VALUE="24"/>
        <PARAMETER NAME="C_S_AXI4_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXI4_ID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_SHARED_STARTUP" VALUE="0"/>
        <PARAMETER NAME="C_LSB_STUP" VALUE="0"/>
        <PARAMETER NAME="C_USE_STARTUP_INT" VALUE="0"/>
        <PARAMETER NAME="UC_FAMILY" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_dac_bias_spi_0"/>
        <PARAMETER NAME="Master_mode" VALUE="1"/>
        <PARAMETER NAME="FIFO_INCLUDED" VALUE="1"/>
        <PARAMETER NAME="Multiples16" VALUE="1"/>
        <PARAMETER NAME="C_SCK_RATIO1" VALUE="1"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="QSPI_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0259000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0259FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="ext_spi_clk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="io0_i" SIGIS="undef"/>
        <PORT DIR="O" NAME="io0_o" SIGIS="undef" SIGNAME="dac_bias_spi_io0_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="BIAS_SDI"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="io0_t" SIGIS="undef"/>
        <PORT DIR="I" NAME="io1_i" SIGIS="undef" SIGNAME="External_Ports_BIAS_SDO">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="BIAS_SDO"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="io1_o" SIGIS="undef"/>
        <PORT DIR="O" NAME="io1_t" SIGIS="undef"/>
        <PORT DIR="I" NAME="sck_i" SIGIS="undef"/>
        <PORT DIR="O" NAME="sck_o" SIGIS="undef" SIGNAME="dac_bias_spi_sck_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="BIAS_SCLK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="sck_t" SIGIS="undef"/>
        <PORT DIR="I" LEFT="3" NAME="ss_i" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="3" NAME="ss_o" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_ss_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="BIAS_S"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ss_t" SIGIS="undef"/>
        <PORT DIR="O" NAME="ip2intc_irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="SPI_0" TYPE="INITIATOR" VLNV="xilinx.com:interface:spi:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="IO0_I" PHYSICAL="io0_i"/>
            <PORTMAP LOGICAL="IO0_O" PHYSICAL="io0_o"/>
            <PORTMAP LOGICAL="IO0_T" PHYSICAL="io0_t"/>
            <PORTMAP LOGICAL="IO1_I" PHYSICAL="io1_i"/>
            <PORTMAP LOGICAL="IO1_O" PHYSICAL="io1_o"/>
            <PORTMAP LOGICAL="IO1_T" PHYSICAL="io1_t"/>
            <PORTMAP LOGICAL="SCK_I" PHYSICAL="sck_i"/>
            <PORTMAP LOGICAL="SCK_O" PHYSICAL="sck_o"/>
            <PORTMAP LOGICAL="SCK_T" PHYSICAL="sck_t"/>
            <PORTMAP LOGICAL="SS_I" PHYSICAL="ss_i"/>
            <PORTMAP LOGICAL="SS_O" PHYSICAL="ss_o"/>
            <PORTMAP LOGICAL="SS_T" PHYSICAL="ss_t"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M28_AXI" DATAWIDTH="32" NAME="AXI_LITE" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="7"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="16" FULLNAME="/ddr4_0" HWVERSION="2.2" INSTANCE="ddr4_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="ddr4" VLNV="xilinx.com:ip:ddr4:2.2">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=ddr4;v=v2_2;d=pg150-ultrascale-memory-ip.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="C0_DDR4_MEMORY_MAP" NAME="C0_DDR4_ADDRESS_BLOCK" RANGE="4294967296" USAGE="memory"/>
      </ADDRESSBLOCKS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="C0_DDR4_MEMORY_MAP" NAME="C0_DDR4_ADDRESS_BLOCK" RANGE="4294967296" USAGE="memory"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="C0.DDR4_Mem_Add_Map" VALUE="ROW_COLUMN_BANK"/>
        <PARAMETER NAME="System_Clock" VALUE="Differential"/>
        <PARAMETER NAME="C0.ControllerType" VALUE="DDR4_SDRAM"/>
        <PARAMETER NAME="C0.APP_ADDR_WIDTH" VALUE="29"/>
        <PARAMETER NAME="C0.MEM_TYPE" VALUE="DDR4"/>
        <PARAMETER NAME="C0.BUFG_LOC_1" VALUE="X0Y46"/>
        <PARAMETER NAME="C0.BUFG_LOC_2" VALUE="X0Y7"/>
        <PARAMETER NAME="C0.BUFG_DIV_LOC_1" VALUE="X0Y7"/>
        <PARAMETER NAME="C0.BUFG_DIV_LOC_2" VALUE="X0Y6"/>
        <PARAMETER NAME="C0.PBLOCK_SLICE_LOC" VALUE="0"/>
        <PARAMETER NAME="C0.PBLOCK_RAMB36_LOC" VALUE="0"/>
        <PARAMETER NAME="C0.PBLOCK_RAMB18_LOC" VALUE="0"/>
        <PARAMETER NAME="C0.PBLOCK_SLICE_LOC_SC" VALUE="0"/>
        <PARAMETER NAME="C0.PBLOCK_RAMB36_LOC_SC" VALUE="0"/>
        <PARAMETER NAME="C0.PBLOCK_RAMB18_LOC_SC" VALUE="0"/>
        <PARAMETER NAME="C0.MMCM_IDX_BANK" VALUE="1"/>
        <PARAMETER NAME="C0.CENTER_BANK_CLOCK_REGION" VALUE="0"/>
        <PARAMETER NAME="C0.CENTER_BANK_MMCME3_ADV_SITE" VALUE="0"/>
        <PARAMETER NAME="C0.SYSCLK_CENTER_INFO" VALUE="TRUE"/>
        <PARAMETER NAME="PING_PONG_PHY" VALUE="1"/>
        <PARAMETER NAME="C0.DDR4_CS_ADDR" VALUE="29"/>
        <PARAMETER NAME="C0.DDR4_VrefVoltage" VALUE="0.84"/>
        <PARAMETER NAME="C0.DDR4_AL" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_DQ_WIDTH" VALUE="64"/>
        <PARAMETER NAME="C0.DDR4_nCK_PER_CLK" VALUE="4"/>
        <PARAMETER NAME="C0.DDR4_DM_WIDTH" VALUE="8"/>
        <PARAMETER NAME="C0.DDR4_DQS_WIDTH" VALUE="8"/>
        <PARAMETER NAME="C0.DDR4_nCS_PER_RANK" VALUE="1"/>
        <PARAMETER NAME="C0.DDR4_MEM_DEVICE_WIDTH" VALUE="16"/>
        <PARAMETER NAME="C0.DDR4_USE_DM_PORT" VALUE="1"/>
        <PARAMETER NAME="C0.DDR4_USE_CS_PORT" VALUE="1"/>
        <PARAMETER NAME="C0.DDR4_ROW_WIDTH" VALUE="16"/>
        <PARAMETER NAME="C0.DDR4_ADDR_WIDTH" VALUE="17"/>
        <PARAMETER NAME="C0.DDR4_BANK_WIDTH" VALUE="2"/>
        <PARAMETER NAME="C0.DDR4_BANK_GROUP_WIDTH" VALUE="1"/>
        <PARAMETER NAME="LR_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C0.DDR4_CK_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C0.DDR4_CKE_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C0.DDR4_CS_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C0.DDR4_ODT_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C0.DDR4_MEMORY_TYPE" VALUE="Components"/>
        <PARAMETER NAME="C0.DDR4_MEMORY_PART" VALUE="MT40A512M16LY-075"/>
        <PARAMETER NAME="C0.DDR4_DATA_MASK" VALUE="8"/>
        <PARAMETER NAME="C0.DDR4_COLUMN_WIDTH" VALUE="10"/>
        <PARAMETER NAME="C0.DDR4_SPEED_GRADE" VALUE="075"/>
        <PARAMETER NAME="C0.DDR4_MEM_DENSITY" VALUE="8Gb"/>
        <PARAMETER NAME="C0.DDR4_MEM_DENSITY_MB" VALUE="8192"/>
        <PARAMETER NAME="C0.DDR4_MEM_DENSITY_GB" VALUE="8"/>
        <PARAMETER NAME="C0.DDR4_COMP_DENSITY" VALUE="8Gb"/>
        <PARAMETER NAME="C0.DDR4_MEM_COMP_WIDTH" VALUE="16"/>
        <PARAMETER NAME="C0.DDR4_DATABITS_PER_STROBE" VALUE="8"/>
        <PARAMETER NAME="C0.DDR4_MODEL_SPEED_GRADE" VALUE="DDR4_750_Timing"/>
        <PARAMETER NAME="C0.DDR4_RANK_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C0.DDR4_IO_VOLTAGE" VALUE="1.2V"/>
        <PARAMETER NAME="C0.DDR4_MIN_PERIOD" VALUE="750"/>
        <PARAMETER NAME="C0.DDR4_MAX_PERIOD" VALUE="1600"/>
        <PARAMETER NAME="C0.DDR4_MR0" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_MR2" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_nAL" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_BURST_MODE" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_BURST_TYPE" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_CL" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_CWL" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_OUTPUT_DRV" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_RTT_NOM" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_RTT_WR" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_MEM" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_DBAW" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_tCK" VALUE="750"/>
        <PARAMETER NAME="C0.DDR4_Configuration" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_tCKE" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_tFAW" VALUE="40"/>
        <PARAMETER NAME="C0.DDR4_tFAW_dlr" VALUE="16"/>
        <PARAMETER NAME="C0.DDR4_tMRD" VALUE="2"/>
        <PARAMETER NAME="C0.DDR4_tRAS" VALUE="43"/>
        <PARAMETER NAME="C0.DDR4_tRCD" VALUE="19"/>
        <PARAMETER NAME="C0.DDR4_tREFI" VALUE="10400"/>
        <PARAMETER NAME="C0.DDR4_tRFC" VALUE="467"/>
        <PARAMETER NAME="C0.DDR4_tRFC_dlr" VALUE="160"/>
        <PARAMETER NAME="C0.DDR4_tRP" VALUE="19"/>
        <PARAMETER NAME="C0.DDR4_tWR" VALUE="20"/>
        <PARAMETER NAME="C0.DDR4_tRRD"/>
        <PARAMETER NAME="C0.DDR4_tRTP" VALUE="10"/>
        <PARAMETER NAME="C0.DDR4_tRRD_S" VALUE="8"/>
        <PARAMETER NAME="C0.DDR4_tRRD_L" VALUE="9"/>
        <PARAMETER NAME="C0.DDR4_tRRD_dlr" VALUE="4"/>
        <PARAMETER NAME="C0.DDR4_tWTR"/>
        <PARAMETER NAME="C0.DDR4_tWTR_S" VALUE="4"/>
        <PARAMETER NAME="C0.DDR4_tWTR_L" VALUE="10"/>
        <PARAMETER NAME="C0.DDR4_tXPR" VALUE="120"/>
        <PARAMETER NAME="C0.DDR4_tZQI" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_tZQCS" VALUE="128"/>
        <PARAMETER NAME="C0.DDR4_tZQINIT" VALUE="256"/>
        <PARAMETER NAME="C0.DDR4_tCCD_3ds" VALUE="5"/>
        <PARAMETER NAME="C0.DDR4_CLKOUTPHY_MODE" VALUE="VCO_2X"/>
        <PARAMETER NAME="C0.DDR4_CLKOUT0_DIVIDE" VALUE="3"/>
        <PARAMETER NAME="C0.DDR4_CLKOUT1_DIVIDE" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_CLKFBOUT_MULT" VALUE="10"/>
        <PARAMETER NAME="C0.DDR4_DIVCLK_DIVIDE" VALUE="3"/>
        <PARAMETER NAME="CAL_INPUT_CLK_PERIOD" VALUE="3334"/>
        <PARAMETER NAME="C0.DDR4_CLKIN_PERIOD" VALUE="3334"/>
        <PARAMETER NAME="C0.DDR4_HR_MIN_FREQ" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_DCI_CASCADE_CUTOFF" VALUE="938"/>
        <PARAMETER NAME="C0.DDR4_IS_FASTER_SPEED_RAM" VALUE="No"/>
        <PARAMETER NAME="C0.DDR4_AXI_ID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C0.DDR4_AXI_ADDR_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C0.DDR4_AXI_DATA_WIDTH" VALUE="512"/>
        <PARAMETER NAME="C0.DDR4_MEM_SIZE" VALUE="4294967296"/>
        <PARAMETER NAME="C0.DDR4_UI_CLOCK" VALUE="333250000"/>
        <PARAMETER NAME="C0.DDR4_CA_MIRROR" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_IS_CUSTOM" VALUE="false"/>
        <PARAMETER NAME="C0.DDR4_AUTO_AP_COL_A3" VALUE="false"/>
        <PARAMETER NAME="C0.DDR4_MCS_ECC" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_Slot" VALUE="1"/>
        <PARAMETER NAME="C0.APP_DATA_WIDTH" VALUE="512"/>
        <PARAMETER NAME="C0.APP_MASK_WIDTH" VALUE="64"/>
        <PARAMETER NAME="C0.DDR4_StackHeight" VALUE="1"/>
        <PARAMETER NAME="CUSTOM_PART_ATTRIBUTES" VALUE="NONE"/>
        <PARAMETER NAME="M_ADDN_UI_CLKOUT1_FREQ_HZ" VALUE="100"/>
        <PARAMETER NAME="M_ADDN_UI_CLKOUT2_FREQ_HZ" VALUE="0.0"/>
        <PARAMETER NAME="M_ADDN_UI_CLKOUT3_FREQ_HZ" VALUE="0.0"/>
        <PARAMETER NAME="M_ADDN_UI_CLKOUT4_FREQ_HZ" VALUE="0.0"/>
        <PARAMETER NAME="M_ADDN_UI_CLKOUT1_PHASE" VALUE="0"/>
        <PARAMETER NAME="M_ADDN_UI_CLKOUT2_PHASE" VALUE="0"/>
        <PARAMETER NAME="M_ADDN_UI_CLKOUT3_PHASE" VALUE="0"/>
        <PARAMETER NAME="M_ADDN_UI_CLKOUT4_PHASE" VALUE="0"/>
        <PARAMETER NAME="CLKOUT0_DIVIDE" VALUE="0"/>
        <PARAMETER NAME="CLKOUT1_DIVIDE" VALUE="10"/>
        <PARAMETER NAME="CLKOUT2_DIVIDE" VALUE="0"/>
        <PARAMETER NAME="CLKOUT3_DIVIDE" VALUE="0"/>
        <PARAMETER NAME="CLKOUT4_DIVIDE" VALUE="0"/>
        <PARAMETER NAME="CLKOUT6_DIVIDE" VALUE="0"/>
        <PARAMETER NAME="Debug_Signal" VALUE="Disable"/>
        <PARAMETER NAME="Simulation_Mode" VALUE="BFM"/>
        <PARAMETER NAME="C0.DDR4_Ecc" VALUE="false"/>
        <PARAMETER NAME="IOPowerReduction" VALUE="OFF"/>
        <PARAMETER NAME="Enable_SysPorts" VALUE="true"/>
        <PARAMETER NAME="Phy_Only" VALUE="Complete_Memory_Controller"/>
        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="C0_CLOCK_BOARD_INTERFACE" VALUE="default_sysclk1_300mhz"/>
        <PARAMETER NAME="IS_FROM_PHY" VALUE="1"/>
        <PARAMETER NAME="RECONFIG_XSDB_SAVE_RESTORE" VALUE="false"/>
        <PARAMETER NAME="AL_SEL" VALUE="0"/>
        <PARAMETER NAME="Example_TG" VALUE="SIMPLE_TG"/>
        <PARAMETER NAME="C0.DDR4_Clamshell" VALUE="false"/>
        <PARAMETER NAME="C0.MIGRATION" VALUE="false"/>
        <PARAMETER NAME="TIMING_OP1" VALUE="false"/>
        <PARAMETER NAME="TIMING_OP2" VALUE="false"/>
        <PARAMETER NAME="TIMING_3DS" VALUE="false"/>
        <PARAMETER NAME="SET_DW_TO_40" VALUE="false"/>
        <PARAMETER NAME="DIFF_TERM_SYSCLK" VALUE="false"/>
        <PARAMETER NAME="C0_DDR4_BOARD_INTERFACE" VALUE="ddr4_sdram_075"/>
        <PARAMETER NAME="C0.DDR4_TimePeriod" VALUE="750"/>
        <PARAMETER NAME="C0.DDR4_InputClockPeriod" VALUE="3334"/>
        <PARAMETER NAME="C0.DDR4_Specify_MandD" VALUE="false"/>
        <PARAMETER NAME="C0.DDR4_PhyClockRatio" VALUE="4:1"/>
        <PARAMETER NAME="C0.DDR4_MemoryType" VALUE="Components"/>
        <PARAMETER NAME="C0.DDR4_MemoryPart" VALUE="MT40A512M16LY-075"/>
        <PARAMETER NAME="C0.DDR4_MemoryVoltage" VALUE="1.2V"/>
        <PARAMETER NAME="C0.DDR4_DataWidth" VALUE="64"/>
        <PARAMETER NAME="C0.DDR4_DataMask" VALUE="DM_NO_DBI"/>
        <PARAMETER NAME="C0.DDR4_AxiSelection" VALUE="true"/>
        <PARAMETER NAME="C0.DDR4_Ordering" VALUE="Normal"/>
        <PARAMETER NAME="C0.DDR4_BurstLength" VALUE="8"/>
        <PARAMETER NAME="C0.DDR4_BurstType" VALUE="Sequential"/>
        <PARAMETER NAME="C0.DDR4_OutputDriverImpedenceControl" VALUE="RZQ/7"/>
        <PARAMETER NAME="C0.DDR4_OnDieTermination" VALUE="RZQ/6"/>
        <PARAMETER NAME="C0.DDR4_CasLatency" VALUE="19"/>
        <PARAMETER NAME="C0.DDR4_CasWriteLatency" VALUE="14"/>
        <PARAMETER NAME="C0.DDR4_ChipSelect" VALUE="true"/>
        <PARAMETER NAME="C0.DDR4_isCKEShared" VALUE="false"/>
        <PARAMETER NAME="C0.DDR4_AxiDataWidth" VALUE="512"/>
        <PARAMETER NAME="C0.DDR4_AxiArbitrationScheme" VALUE="RD_PRI_REG"/>
        <PARAMETER NAME="C0.DDR4_AxiNarrowBurst" VALUE="false"/>
        <PARAMETER NAME="C0.DDR4_AxiAddressWidth" VALUE="32"/>
        <PARAMETER NAME="C0.DDR4_AxiIDWidth" VALUE="1"/>
        <PARAMETER NAME="C0.DDR4_Capacity" VALUE="512"/>
        <PARAMETER NAME="C0.DDR4_MemoryName" VALUE="MainMemory"/>
        <PARAMETER NAME="C0.DDR4_AutoPrecharge" VALUE="false"/>
        <PARAMETER NAME="C0.DDR4_UserRefresh_ZQCS" VALUE="false"/>
        <PARAMETER NAME="C0.DDR4_CustomParts" VALUE="no_file_loaded"/>
        <PARAMETER NAME="C0.DDR4_isCustom" VALUE="false"/>
        <PARAMETER NAME="C0.DDR4_SELF_REFRESH" VALUE="false"/>
        <PARAMETER NAME="C0.DDR4_SAVE_RESTORE" VALUE="false"/>
        <PARAMETER NAME="C0.DDR4_RESTORE_CRC" VALUE="false"/>
        <PARAMETER NAME="ADDN_UI_CLKOUT1_FREQ_HZ" VALUE="100"/>
        <PARAMETER NAME="ADDN_UI_CLKOUT2_FREQ_HZ" VALUE="None"/>
        <PARAMETER NAME="ADDN_UI_CLKOUT3_FREQ_HZ" VALUE="None"/>
        <PARAMETER NAME="ADDN_UI_CLKOUT4_FREQ_HZ" VALUE="None"/>
        <PARAMETER NAME="CLKOUT6" VALUE="false"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_ddr4_0_0"/>
        <PARAMETER NAME="No_Controller" VALUE="1"/>
        <PARAMETER NAME="Reference_Clock" VALUE="Differential"/>
        <PARAMETER NAME="IO_Power_Reduction" VALUE="false"/>
        <PARAMETER NAME="DCI_Cascade" VALUE="false"/>
        <PARAMETER NAME="Default_Bank_Selections" VALUE="false"/>
        <PARAMETER NAME="PARTIAL_RECONFIG_FLOW_MIG" VALUE="false"/>
        <PARAMETER NAME="MCS_DBG_EN" VALUE="false"/>
        <PARAMETER NAME="C0.DDR4_CK_SKEW_0" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_CK_SKEW_1" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_CK_SKEW_2" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_CK_SKEW_3" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_0" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_1" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_2" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_3" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_4" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_5" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_6" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_7" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_8" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_9" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_10" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_11" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_12" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_13" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_14" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_15" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_16" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ADDR_SKEW_17" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_BA_SKEW_0" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_BA_SKEW_1" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_BG_SKEW_0" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_BG_SKEW_1" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_CS_SKEW_0" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_CS_SKEW_1" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_CS_SKEW_2" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_CS_SKEW_3" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_CKE_SKEW_0" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_CKE_SKEW_1" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_CKE_SKEW_2" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_CKE_SKEW_3" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ACT_SKEW" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_PAR_SKEW" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ODT_SKEW_0" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ODT_SKEW_1" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ODT_SKEW_2" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_ODT_SKEW_3" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_LR_SKEW_0" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_LR_SKEW_1" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_TREFI" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_TRFC" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_TRFC_DLR" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_TXPR" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_nCK_TREFI" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_nCK_TRFC" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_nCK_TRFC_DLR" VALUE="0"/>
        <PARAMETER NAME="C0.DDR4_nCK_TXPR" VALUE="5"/>
        <PARAMETER NAME="C0.ADDR_WIDTH" VALUE="17"/>
        <PARAMETER NAME="C0.BANK_GROUP_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C0.LR_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C0.CK_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C0.CKE_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C0.CS_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C0.ODT_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C0.StackHeight" VALUE="1"/>
        <PARAMETER NAME="C0.DDR4_Enable_LVAUX" VALUE="false"/>
        <PARAMETER NAME="C0.DDR4_EN_PARITY" VALUE="false"/>
        <PARAMETER NAME="EN_PP_4R_MIR" VALUE="false"/>
        <PARAMETER NAME="MCS_WO_DSP" VALUE="false"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0x500000000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0x5FFFFFFFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" NAME="c0_init_calib_complete" SIGIS="undef"/>
        <PORT DIR="O" NAME="dbg_clk" SIGIS="undef"/>
        <PORT DIR="I" NAME="c0_sys_clk_p" SIGIS="clk" SIGNAME="ddr4_0_c0_sys_clk_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="sys_clk_ddr4_clk_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="c0_sys_clk_n" SIGIS="clk" SIGNAME="ddr4_0_c0_sys_clk_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="sys_clk_ddr4_clk_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="511" NAME="dbg_bus" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="16" NAME="c0_ddr4_adr" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_adr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="ddr4_pl_adr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="c0_ddr4_ba" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_ba">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="ddr4_pl_ba"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="c0_ddr4_cke" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_cke">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="ddr4_pl_cke"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="c0_ddr4_cs_n" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_cs_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="ddr4_pl_cs_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" LEFT="7" NAME="c0_ddr4_dm_dbi_n" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_dm_dbi_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="ddr4_pl_dm_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" LEFT="63" NAME="c0_ddr4_dq" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_dq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="ddr4_pl_dq"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" LEFT="7" NAME="c0_ddr4_dqs_c" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_dqs_c">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="ddr4_pl_dqs_c"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="IO" LEFT="7" NAME="c0_ddr4_dqs_t" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_dqs_t">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="ddr4_pl_dqs_t"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="c0_ddr4_odt" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_odt">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="ddr4_pl_odt"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="c0_ddr4_bg" RIGHT="0" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_bg">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="ddr4_pl_bg"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="c0_ddr4_reset_n" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_reset_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="ddr4_pl_reset_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="c0_ddr4_act_n" SIGIS="undef" SIGNAME="ddr4_0_c0_ddr4_act_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="ddr4_pl_act_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="c0_ddr4_ck_c" RIGHT="0" SIGIS="clk" SIGNAME="ddr4_0_c0_ddr4_ck_c">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="ddr4_pl_ck_c"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="c0_ddr4_ck_t" RIGHT="0" SIGIS="clk" SIGNAME="ddr4_0_c0_ddr4_ck_t">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="ddr4_pl_ck_t"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="333250000" DIR="O" NAME="c0_ddr4_ui_clk" SIGIS="clk" SIGNAME="ddr4_0_c0_ddr4_ui_clk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_clock_converter_0" PORT="m_axis_aclk"/>
            <CONNECTION INSTANCE="rst_ddr4" PORT="slowest_sync_clk"/>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxihpm1_fpd_aclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="c0_ddr4_ui_clk_sync_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="ddr4_0_c0_ddr4_ui_clk_sync_rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ddr4" PORT="ext_reset_in"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="c0_ddr4_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_ddr4_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_ddr4" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="c0_ddr4_s_axi_awid" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="c0_ddr4_s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="c0_ddr4_s_axi_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="c0_ddr4_s_axi_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="c0_ddr4_s_axi_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="c0_ddr4_s_axi_awlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="c0_ddr4_s_axi_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="c0_ddr4_s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="c0_ddr4_s_axi_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="c0_ddr4_s_axi_awvalid" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="c0_ddr4_s_axi_awready" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="511" NAME="c0_ddr4_s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="63" NAME="c0_ddr4_s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="c0_ddr4_s_axi_wlast" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="c0_ddr4_s_axi_wvalid" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="c0_ddr4_s_axi_wready" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="c0_ddr4_s_axi_bready" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="c0_ddr4_s_axi_bid" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="1" NAME="c0_ddr4_s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="c0_ddr4_s_axi_bvalid" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="c0_ddr4_s_axi_arid" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="31" NAME="c0_ddr4_s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="c0_ddr4_s_axi_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="c0_ddr4_s_axi_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="c0_ddr4_s_axi_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="c0_ddr4_s_axi_arlock" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="c0_ddr4_s_axi_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="c0_ddr4_s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="c0_ddr4_s_axi_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="c0_ddr4_s_axi_arvalid" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="c0_ddr4_s_axi_arready" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="c0_ddr4_s_axi_rready" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="c0_ddr4_s_axi_rlast" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="c0_ddr4_s_axi_rvalid" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="c0_ddr4_s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="c0_ddr4_s_axi_rid" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="511" NAME="c0_ddr4_s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_M00_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="M00_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="100000000" DIR="O" NAME="addn_ui_clkout1" SIGIS="clk"/>
        <PORT DIR="I" NAME="sys_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="rst_100_bus_struct_reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="bus_struct_reset"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="External_Interface_sys_clk_ddr4" NAME="C0_SYS_CLK" TYPE="TARGET" VLNV="xilinx.com:interface:diff_clock:1.0">
          <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="300000000"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="CLK_N" PHYSICAL="c0_sys_clk_n"/>
            <PORTMAP LOGICAL="CLK_P" PHYSICAL="c0_sys_clk_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ddr4_0_C0_DDR4" DATAWIDTH="64" NAME="C0_DDR4" TYPE="INITIATOR" VLNV="xilinx.com:interface:ddr4:1.0">
          <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
          <PARAMETER NAME="TIMEPERIOD_PS" VALUE="750"/>
          <PARAMETER NAME="MEMORY_TYPE" VALUE="Components"/>
          <PARAMETER NAME="MEMORY_PART" VALUE="MT40A512M16LY-075"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="64"/>
          <PARAMETER NAME="CS_ENABLED" VALUE="true"/>
          <PARAMETER NAME="DATA_MASK_ENABLED" VALUE="DM_NO_DBI"/>
          <PARAMETER NAME="SLOT" VALUE="Single"/>
          <PARAMETER NAME="CUSTOM_PARTS" VALUE="no_file_loaded"/>
          <PARAMETER NAME="MEM_ADDR_MAP" VALUE="ROW_COLUMN_BANK"/>
          <PARAMETER NAME="BURST_LENGTH" VALUE="8"/>
          <PARAMETER NAME="AXI_ARBITRATION_SCHEME" VALUE="RD_PRI_REG"/>
          <PARAMETER NAME="CAS_LATENCY" VALUE="19"/>
          <PARAMETER NAME="CAS_WRITE_LATENCY" VALUE="14"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ACT_N" PHYSICAL="c0_ddr4_act_n"/>
            <PORTMAP LOGICAL="ADR" PHYSICAL="c0_ddr4_adr"/>
            <PORTMAP LOGICAL="BA" PHYSICAL="c0_ddr4_ba"/>
            <PORTMAP LOGICAL="BG" PHYSICAL="c0_ddr4_bg"/>
            <PORTMAP LOGICAL="CK_C" PHYSICAL="c0_ddr4_ck_c"/>
            <PORTMAP LOGICAL="CK_T" PHYSICAL="c0_ddr4_ck_t"/>
            <PORTMAP LOGICAL="CKE" PHYSICAL="c0_ddr4_cke"/>
            <PORTMAP LOGICAL="CS_N" PHYSICAL="c0_ddr4_cs_n"/>
            <PORTMAP LOGICAL="DM_N" PHYSICAL="c0_ddr4_dm_dbi_n"/>
            <PORTMAP LOGICAL="DQ" PHYSICAL="c0_ddr4_dq"/>
            <PORTMAP LOGICAL="DQS_C" PHYSICAL="c0_ddr4_dqs_c"/>
            <PORTMAP LOGICAL="DQS_T" PHYSICAL="c0_ddr4_dqs_t"/>
            <PORTMAP LOGICAL="ODT" PHYSICAL="c0_ddr4_odt"/>
            <PORTMAP LOGICAL="RESET_N" PHYSICAL="c0_ddr4_reset_n"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_smc_1_M00_AXI" DATAWIDTH="512" NAME="C0_DDR4_S_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="FREQ_HZ" VALUE="333250000"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="512"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="1"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="32"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
          <PARAMETER NAME="PHASE" VALUE="0.00"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_ddr4_0_0_c0_ddr4_ui_clk"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="c0_ddr4_s_axi_araddr"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="c0_ddr4_s_axi_arburst"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="c0_ddr4_s_axi_arcache"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="c0_ddr4_s_axi_arid"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="c0_ddr4_s_axi_arlen"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="c0_ddr4_s_axi_arlock"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="c0_ddr4_s_axi_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="c0_ddr4_s_axi_arqos"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="c0_ddr4_s_axi_arready"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="c0_ddr4_s_axi_arsize"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="c0_ddr4_s_axi_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="c0_ddr4_s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="c0_ddr4_s_axi_awburst"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="c0_ddr4_s_axi_awcache"/>
            <PORTMAP LOGICAL="AWID" PHYSICAL="c0_ddr4_s_axi_awid"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="c0_ddr4_s_axi_awlen"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="c0_ddr4_s_axi_awlock"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="c0_ddr4_s_axi_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="c0_ddr4_s_axi_awqos"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="c0_ddr4_s_axi_awready"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="c0_ddr4_s_axi_awsize"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="c0_ddr4_s_axi_awvalid"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="c0_ddr4_s_axi_bid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="c0_ddr4_s_axi_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="c0_ddr4_s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="c0_ddr4_s_axi_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="c0_ddr4_s_axi_rdata"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="c0_ddr4_s_axi_rid"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="c0_ddr4_s_axi_rlast"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="c0_ddr4_s_axi_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="c0_ddr4_s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="c0_ddr4_s_axi_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="c0_ddr4_s_axi_wdata"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="c0_ddr4_s_axi_wlast"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="c0_ddr4_s_axi_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="c0_ddr4_s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="c0_ddr4_s_axi_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="25" FULLNAME="/lo_spi" HWVERSION="3.2" INSTANCE="lo_spi" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_quad_spi" VLNV="xilinx.com:ip:axi_quad_spi:3.2">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_quad_spi;v=v3_2;d=pg153-axi-quad-spi.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="AXI_LITE" NAME="Reg" RANGE="4096" USAGE="register">
          <REGISTERS>
            <REGISTER NAME="XIP_Config_Reg">
              <PROPERTY NAME="DESCRIPTION" VALUE="XIP Configuration Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x60"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="CPHA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPHA&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="XIP_Status_Reg">
              <PROPERTY NAME="DESCRIPTION" VALUE="XIP Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x64"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x1"/>
              <FIELDS>
                <FIELD NAME="RX_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receiver Empty.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="RX_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receiver Full.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Master_MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Master mode fault. This bit is set to 1 if the spisel line is deasserted.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA Error.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="AXI_Transaction_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="AXI Transaction Error.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SRR">
              <PROPERTY NAME="DESCRIPTION" VALUE="Software Reset Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x40"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="The only allowed operation on this register is a write of 0x0000000a, which resets the AXI Quad SPI core.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPICR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x60"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x180"/>
              <FIELDS>
                <FIELD NAME="LOOP">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Local loopback mode&#xA;Enables local loopback operation and is functional only in standard SPI master mode.&#xA;When set to:   0 - Normal operation.   1 - Loopback mode. The transmitter output is internally connected to the receiver input. The receiver and transmitter operate normally, except that received data (from remote slave) is ignored.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SPE">
                  <PROPERTY NAME="DESCRIPTION" VALUE="SPI system enable&#xA;When set to:&#xA;  0 - SPI system disabled. Both master and slave outputs are in 3-state and slave inputs are ignored.&#xA;  1 - SPI system enabled. Master outputs active (for example, IO0 (MOSI) and SCK in idle state) and slave outputs become active if SS becomes asserted. The master starts transferring when transmit data is available.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Master">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Master (SPI master mode)&#xA;Setting this bit configures the SPI device as a master or a slave.&#xA;When set to:&#xA;  0 - Slave configuration.&#xA;  1 - Master configuration.&#xA;In dual/quad SPI mode only the master mode of the core is allowed.&#xA;Standard Slave mode is not supported for SCK ratio = 2&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Clock polarity&#xA;Setting this bit defines clock polarity.&#xA;When set to:&#xA;  0 - Active-High clock; SCK idles Low.&#xA;  1 - Active-Low clock; SCK idles High.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPHA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Clock phase&#xA;Setting this bit selects one of two fundamentally different transfer formats.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_FIFO_Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit FIFO reset&#xA;When written to 1, this bit forces a reset of the transmit FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0.&#xA;When set to:   0 - Transmit FIFO normal operation.   1 - Reset transmit FIFO pointer&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="RX_FIFO_Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive FIFO reset&#xA;When written to 1, this bit forces a reset of the receive FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0.&#xA;When set to:   0 - Receive FIFO normal operation.   1 - Reset receive FIFO pointer.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Manual_Slave_Select_Assertion_Enable">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Manual slave select assertion enable&#xA;This bit forces the data in the slave select register to be asserted on the slave select output anytime the device is configured as a master and the device is enabled (SPE asserted).&#xA;This bit has no effect on slave operation.&#xA;When set to:   0 - Slave select output asserted by master core logic.   1 - Slave select output follows data in slave select register. The manual slave assertion mode is supported in standard SPI mode only.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Master_Transaction_Inhibit">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Master transaction inhibit&#xA;This bit inhibits master transactions.&#xA;This bit has no effect on slave operation.&#xA;When set to:   0 - Master transactions enabled.   1 - Master transactions disabled. This bit immediately inhibits the transaction. Setting this bit while transfer is in progress would result in unpredictable outcome&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="LSB_First">
                  <PROPERTY NAME="DESCRIPTION" VALUE="LSB first&#xA;This bit selects LSB first data transfer format.&#xA;The default transfer format is MSB first.&#xA;When set to:&#xA;  0 - MSB first transfer format.&#xA;  1 - LSB first transfer format.&#xA;In Dual/Quad SPI mode, only the MSB first mode of the core is allowed.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPISR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x64"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0A5"/>
              <FIELDS>
                <FIELD NAME="RX_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive Empty.&#xA;When a receive FIFO exists, this bit is set High when the receive FIFO is empty. The occupancy of the FIFO is decremented with each FIFO read operation.&#xA;Note: When FIFOs do not exist, this bit is set High when the receive register has been read (this option is available only in standard SPI mode). This bit is cleared at the end of a successful SPI transfer. For dual/quad SPI mode, the FIFO is always present in the core.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="RX_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive full.&#xA;When a receive FIFO exists, this bit is set High when the receive FIFO is full. The occupancy of the FIFO is incremented with the completion of each SPI transaction.&#xA;Note: When FIFOs do not exist, this bit is set High when an SPI transfer has completed (this option is available only in standard SPI mode). Rx_Empty and Rx_Full are complements in this case&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit empty.&#xA;When a transmit FIFO exists, this bit is set to High when the transmit FIFO is empty. This bit goes High as soon as the TX FIFO becomes empty. While this bit is High, the last byte of the data that is to be transmitted would still be in the pipeline.&#xA;The occupancy of the FIFO is decremented with the completion of each SPI transfer.&#xA;Note: When FIFOs do not exist, this bit is set with the completion of an SPI transfer (this option is available only in standard SPI mode). Either with or without FIFOs, this bit is cleared on an AXI write to the FIFO or transmit register. For Dual/Quad SPI mode, the FIFO is always present in the core.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit full.&#xA;When a transmit FIFO exists, this bit is set High when the transmit FIFO is full.&#xA;Note: When FIFOs do not exist, this bit is set High when an AXI write to the transmit register has been made (this option is available only in standard SPI mode). This bit is cleared when the SPI transfer is completed&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Mode-fault error flag.&#xA;This flag is set if the SS signal goes active while the SPI device is configured as a master. MODF is automatically cleared by reading the SPISR. &#xA;A Low-to-High MODF transition generates a single-cycle strobe interrupt.   0 - No error.   1 - Error condition detected&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Mode_Select">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave_Mode_Select flag.&#xA;This flag is asserted when the core is configured in slave mode. Slave_Mode_Select is activated as soon as the master SPI core asserts the chip select pin for the core.&#xA;1 - Default in standard mode.&#xA;0 - Asserted when core configured in slave mode and selected by external SPI master.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA_Error flag.&#xA;When set to:   0 - Default.   1 - The CPOL and CPHA are set to 01 or 10. When the SPI memory is chosen as either Winbond, Micron or Spansion, and CPOL and CPHA are configured as 01 or 10, this bit is set.&#xA;These memories support CPOL=CPHA mode in 00 or in 11 mode. CPOL_CPHA_Error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_mode_error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave mode error flag.&#xA;When set to:   1 - This bit is set when the core is configured with dual or quad SPI mode and the master is set to 0 in the control register (SPICR).   0 - Master mode is set in the control register (SPICR). Note: Quad SPI mode, only the master mode of the core is allowed. Slave mode error flag is only applicable when the core is configured either in dual or qu ad mode in legacy or enhanced AXI4 mode interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MSB_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="MSB error flag.&#xA;When set to:   0 - Default.   1 - This bit is set when the core is configured to transfer the SPI transactions in either dual or quad SPI mode and LSB first bit is set in the control register (SPICR). Note: In dual/quad SPI mode, only the MSB first mode of the core is allowed. MSB error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Loopback_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Loopback error flag.&#xA;When set to:   0 - Default. The loopback bit in the control register is at default state.   1 - When the SPI command, address, and data bits are set to be transferred in other than standard SPI protocol mode and this bit is set in control register (SPICR). Note: Loopback is only allowed when the core is configured in standard mode. Other modes setting of the bit causes an error and the interrupt bit is set in legacy or enhanced mode AXI4 interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Command_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Command error flag.&#xA;When set to:   0 - Default.   1 - When the core is configured in dual/quad SPI mode and the first entry in the SPI DTR FIFO (after reset) do not match with the supported command list for the particular memory, this bit is set. Note: Command error is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_SSR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Slave Select Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x70"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0xFFFF"/>
              <FIELDS>
                <FIELD NAME="Selected_Slave">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Active-Low, one-hot encoded slave select&#xA;The slaves are numbered right to left starting at zero with the LSB. The slave numbers correspond to the indexes of signal SS&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="3"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_TXFIFO_OR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Transmit FIFO Occupancy Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x74"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Occupancy_Value">
                  <PROPERTY NAME="DESCRIPTION" VALUE="The binary value plus 1 yields the occupancy.&#xA;Bit width is log(FIFO Depth). &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_RXFIFO_OR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Receive FIFO Occupancy Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x78"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Occupancy_Value">
                  <PROPERTY NAME="DESCRIPTION" VALUE="The binary value plus 1 yields the occupancy. &#xA;Bit width is log(FIFO Depth). &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="DGIER">
              <PROPERTY NAME="DESCRIPTION" VALUE="Device Global Interrupt Enable Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="GIE">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Global Interrupt Enable.&#xA;Allows passing all individually enabled interrupts to the interrupt controller.&#xA;When set to:   0 - Disabled.   1 - Enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="31"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="31"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_DTR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Data Transmit Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x68"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="TX_Data">
                  <PROPERTY NAME="DESCRIPTION" VALUE="SPI Transmit Data.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_DRR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Data Receive Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x6C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="RX_Data">
                  <PROPERTY NAME="DESCRIPTION" VALUE="SPI Receive Data&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IPISR">
              <PROPERTY NAME="DESCRIPTION" VALUE="IP Interrupt Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x20"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Mode-fault error.&#xA;This interrupt is generated if the SS signal goes active while the SPI device is configured as a master. This bit is set immediately on SS going active.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave mode-fault error.&#xA;This interrupt is generated if the SS signal goes active while the SPI device is configured as a slave, but is not enabled.&#xA;This bit is set immediately on SS going active and continually set if SS is active and the device is not enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit register/FIFO empty.&#xA;It is set when the last byte of data has been transferred out to the external flash memory.&#xA;In the context of the M68HC11 reference manual, when configured without FIFOs, this interrupt is equivalent in information content to the complement of the SPI transfer complete flag (SPIF ) interrupt bit.&#xA;In master mode if this bit is set to 1, no more SPI transfers are permitted&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Underrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit register/FIFO underrun.&#xA;This bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register when data is requested from an empty transmit register/FIFO by the SPI core logic to perform a SPI transfer.&#xA;This can occur only when the SPI device is configured as a slave in standard SPI configuration and is enabled by the SPE bit as set. All zeros are loaded in the shift register and transmitted by the slave in an under-run condition&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data receive register/FIFO full.&#xA;Without FIFOs, this bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register (An element can be a byte, half-word, or word depending on the value of Transfer Width).&#xA;With FIFOs, this bit is set at the end of the SPI element transfer, when the receive FIFO has been completely filled by a one-clock period strobe to the interrupt register.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Overrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data receive register/FIFO overrun.&#xA;This bit is set by a one-clock period strobe to the interrupt register when an attempt to write data to a full receive register or FIFO is made by the SPI core logic to complete a SPI transfer.&#xA;This can occur when the SPI device is in either master or slave mode (in standard SPI mode) or if the IP is configured in SPI master mode (dual or quad SPI mode).&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TXFIFO_Half_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit FIFO half empty.&#xA;In standard SPI configuration, IPISR Bit[6] is the transmit FIFO half-empty interrupt. &#xA;In dual or quad SPI configuration, based on the FIFO depth, this bit is set at half-empty condition.&#xA;Note: This interrupt exists only if the AXI Quad SPI core is configured with FIFOs (In standard, dual or quad SPI mode).&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Select_Mode">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave select mode.&#xA;The assertion of this bit is applicable only when the core is configured in slave mode in standard SPI configuration. &#xA;This bit is set when the other SPI master core selects the core by asserting the slave select line. This bit is set by a one-clock period strobe to the interrupt register.&#xA;Note: This bit is applicable only in standard SPI slave mode&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Not_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DRR not empty.&#xA;The assertion of this bit is applicable only in the case where FIFO Depth is 16 or 256 and the core is configured in slave mode and standard SPI mode. This bit is set when the DRR FIFO receives the first data value during the SPI transaction.&#xA;This bit is set by a one-clock period strobe to the interrupt register when the core receives the first data beat.&#xA;Note: The assertion of this bit is applicable only when the FIFO Depth parameter is 16 or 256 and the core is configured in slave mode in standard SPI mode. When FIFO Depth is set to 0, this bit always returns 0. This bit has no significance in dual/quad mode&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA error.&#xA;This flag is asserted when:&#xA;  The core is configured in either dual or quad SPI mode and&#xA;  The CPOL - CPHA control register bits are set to 01 or 10.&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Mode_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="I/O mode instruction error.&#xA;This flag is asserted when:&#xA;  The core is configured in either dual or quad SPI mode and&#xA;  The core is configured in master = 0 in control register (SPICR(2)).&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MSB_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="MSB error.&#xA;This flag is asserted when:&#xA;  The core is configured in either dual or quad SPI mode and&#xA;  The LSB First bit in the control register (SPICR) is set to 1.&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Loopback_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Loopback error.&#xA;This flag is asserted when:&#xA;  The core is configured in dual or quad SPI transfer mode and&#xA;  The LOOP bit is set in control register (SPICR(0)).&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Command_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Command error.&#xA;This flag is asserted when:   The core is configured in dual/quad SPI mode and   The first entry in the SPI DTR FIFO (after reset) does not match with the supported command list for particular memory. When the SPI command in DTR FIFO does not match with the internal supported command list, the core completes the SPI transactions in standard SPI format. This bit is set to show this behavior of the core.&#xA;In standard SPI mode this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IPIER">
              <PROPERTY NAME="DESCRIPTION" VALUE="IP Interrupt Enable Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x28"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Mode-fault error flag.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave mode-fault error flag.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit register/FIFO empty.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Underrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit FIFO underrun.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data receive register/FIFO full.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Overrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive FIFO overrun.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_FIFO_Half_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit FIFO half empty.   0 - Disabled.   1 - Enabled. Note: This bit is meaningful only if the AXI Quad SPI core is configured with FIFOs.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Select_Mode">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave_Select_Mode.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in slave mode by selecting the active-Low status on spisel.&#xA;In master mode, setting this bit has no effect.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Not_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DRR_Not_Empty.   0 - Disabled.   1 - Enabled. Note: The setting of this bit is applicable only when FIFO Depth is set to 1 and the core is configured in slave mode of standard SPI mode.&#xA;If FIFO Depth is set to 0, the setting of this bit has no effect. This is allowed only in standard SPI configuration. It means this bit is not set in the IPIER register. Therefore, this bit should only be used when FIFO Depth is set to 1 and when the core is configured in slave mode.&#xA;This bit has no significance in dual or quad mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Mode_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="I/O mode instruction error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MSB_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="MSB_Error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Loopback_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Loopback Error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Command_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Command_Error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
          </REGISTERS>
        </ADDRESSBLOCK>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="Async_Clk" VALUE="0"/>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_SELECT_XPM" VALUE="0"/>
        <PARAMETER NAME="C_SUB_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_INSTANCE" VALUE="axi_quad_spi_inst"/>
        <PARAMETER NAME="C_SPI_MEM_ADDR_BITS" VALUE="24"/>
        <PARAMETER NAME="C_TYPE_OF_AXI4_INTERFACE" VALUE="0"/>
        <PARAMETER NAME="C_XIP_MODE" VALUE="0"/>
        <PARAMETER NAME="C_XIP_PERF_MODE" VALUE="1"/>
        <PARAMETER NAME="C_BYTE_LEVEL_INTERRUPT_EN" VALUE="0"/>
        <PARAMETER NAME="C_UC_FAMILY" VALUE="1"/>
        <PARAMETER NAME="C_FIFO_DEPTH" VALUE="16"/>
        <PARAMETER NAME="C_SCK_RATIO" VALUE="16"/>
        <PARAMETER NAME="C_DUAL_QUAD_MODE" VALUE="0"/>
        <PARAMETER NAME="C_NUM_SS_BITS" VALUE="3"/>
        <PARAMETER NAME="C_NUM_TRANSFER_BITS" VALUE="8"/>
        <PARAMETER NAME="C_NEW_SEQ_EN" VALUE="1"/>
        <PARAMETER NAME="C_SPI_MODE" VALUE="0"/>
        <PARAMETER NAME="C_USE_STARTUP" VALUE="0"/>
        <PARAMETER NAME="C_USE_STARTUP_EXT" VALUE="0"/>
        <PARAMETER NAME="C_SPI_MEMORY" VALUE="1"/>
        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="7"/>
        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXI4_ADDR_WIDTH" VALUE="24"/>
        <PARAMETER NAME="C_S_AXI4_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXI4_ID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_SHARED_STARTUP" VALUE="0"/>
        <PARAMETER NAME="C_LSB_STUP" VALUE="0"/>
        <PARAMETER NAME="C_USE_STARTUP_INT" VALUE="0"/>
        <PARAMETER NAME="UC_FAMILY" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_lo_spi_0"/>
        <PARAMETER NAME="Master_mode" VALUE="1"/>
        <PARAMETER NAME="FIFO_INCLUDED" VALUE="1"/>
        <PARAMETER NAME="Multiples16" VALUE="1"/>
        <PARAMETER NAME="C_SCK_RATIO1" VALUE="1"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="QSPI_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA025A000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA025AFFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="ext_spi_clk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="lo_spi_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="lo_spi_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="lo_spi_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="lo_spi_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="lo_spi_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="lo_spi_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="lo_spi_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="lo_spi_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="lo_spi_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="lo_spi_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="io0_i" SIGIS="undef"/>
        <PORT DIR="O" NAME="io0_o" SIGIS="undef" SIGNAME="lo_spi_io0_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="LO_MOSI"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="io0_t" SIGIS="undef"/>
        <PORT DIR="I" NAME="io1_i" SIGIS="undef" SIGNAME="lo_spi_mux_v2_0_sdo_out">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi_mux_v2_0" PORT="sdo_out"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="io1_o" SIGIS="undef"/>
        <PORT DIR="O" NAME="io1_t" SIGIS="undef"/>
        <PORT DIR="I" NAME="sck_i" SIGIS="undef"/>
        <PORT DIR="O" NAME="sck_o" SIGIS="undef" SIGNAME="lo_spi_sck_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="LO_SCLK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="sck_t" SIGIS="undef"/>
        <PORT DIR="I" LEFT="2" NAME="ss_i" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="ss_o" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_ss_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi_mux_v2_0" PORT="ss_in"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ss_t" SIGIS="undef"/>
        <PORT DIR="O" NAME="ip2intc_irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="SPI_0" TYPE="INITIATOR" VLNV="xilinx.com:interface:spi:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="IO0_I" PHYSICAL="io0_i"/>
            <PORTMAP LOGICAL="IO0_O" PHYSICAL="io0_o"/>
            <PORTMAP LOGICAL="IO0_T" PHYSICAL="io0_t"/>
            <PORTMAP LOGICAL="IO1_I" PHYSICAL="io1_i"/>
            <PORTMAP LOGICAL="IO1_O" PHYSICAL="io1_o"/>
            <PORTMAP LOGICAL="IO1_T" PHYSICAL="io1_t"/>
            <PORTMAP LOGICAL="SCK_I" PHYSICAL="sck_i"/>
            <PORTMAP LOGICAL="SCK_O" PHYSICAL="sck_o"/>
            <PORTMAP LOGICAL="SCK_T" PHYSICAL="sck_t"/>
            <PORTMAP LOGICAL="SS_I" PHYSICAL="ss_i"/>
            <PORTMAP LOGICAL="SS_O" PHYSICAL="ss_o"/>
            <PORTMAP LOGICAL="SS_T" PHYSICAL="ss_t"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M29_AXI" DATAWIDTH="32" NAME="AXI_LITE" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="7"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="1" FULLNAME="/lo_spi_mux_v2_0" HWVERSION="1.0" INSTANCE="lo_spi_mux_v2_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="lo_spi_mux_v2" VLNV="xilinx.com:module_ref:lo_spi_mux_v2:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="Component_Name" VALUE="d_1_lo_spi_mux_v2_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="2" NAME="ss_in" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_ss_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="ss_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ss0_out" SIGIS="undef" SIGNAME="lo_spi_mux_v2_0_ss0_out">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="LO_CS0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ss1_out" SIGIS="undef" SIGNAME="lo_spi_mux_v2_0_ss1_out">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="LO_CS1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ss2_out" SIGIS="undef" SIGNAME="lo_spi_mux_v2_0_ss2_out">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="LO_CS2"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="sdo0_in" SIGIS="undef" SIGNAME="External_Ports_LO_MISO0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="LO_MISO0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="sdo1_in" SIGIS="undef" SIGNAME="External_Ports_LO_MISO1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="LO_MISO1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="sdo2_in" SIGIS="undef" SIGNAME="External_Ports_LO_MISO2">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="LO_MISO2"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="sdo_out" SIGIS="undef" SIGNAME="lo_spi_mux_v2_0_sdo_out">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="io1_i"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="7" FULLNAME="/lo_sync_constant_0" HWVERSION="1.1" INSTANCE="lo_sync_constant_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconstant" VLNV="xilinx.com:ip:xlconstant:1.1">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="CONST_WIDTH" VALUE="1"/>
        <PARAMETER NAME="CONST_VAL" VALUE="0x0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_lo_sync_constant_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="O" LEFT="0" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="lo_sync_constant_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="LO_SYNC"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="3" FULLNAME="/mr_buffer_et_0" HWVERSION="1.0" INSTANCE="mr_buffer_et_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="mr_buffer_et" VLNV="user.org:user:mr_buffer_et:1.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="s00_axi" NAME="reg0" RANGE="4096" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="NM" VALUE="8"/>
        <PARAMETER NAME="N" VALUE="10"/>
        <PARAMETER NAME="B" VALUE="32"/>
        <PARAMETER NAME="C_S00_AXI_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S00_AXI_ADDR_WIDTH" VALUE="6"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_mr_buffer_et_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0257000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA0257FFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="trigger" SIGIS="undef" SIGNAME="qick_vec2bit_1_dout3">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_vec2bit_1" PORT="dout3"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s00_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s00_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s00_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s00_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s00_axi_awvalid" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s00_axi_awready" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s00_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s00_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s00_axi_wvalid" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s00_axi_wready" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s00_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s00_axi_bvalid" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s00_axi_bready" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="s00_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s00_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s00_axi_arvalid" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s00_axi_arready" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s00_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s00_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s00_axi_rvalid" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s00_axi_rready" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="512000000" DIR="I" NAME="s00_axis_aclk" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s00_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_adc0_x2_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s00_axis_tready" SIGIS="undef" SIGNAME="axis_switch_mr_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="255" NAME="s00_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s00_axis_tstrb" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="s00_axis_tlast" SIGIS="undef"/>
        <PORT DIR="I" NAME="s00_axis_tvalid" SIGIS="undef" SIGNAME="axis_switch_mr_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="m00_axis_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m00_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m00_axis_tvalid" SIGIS="undef" SIGNAME="axi_dma_mr_s_axis_s2mm_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axis_s2mm_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="m00_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axis_s2mm_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axis_s2mm_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="m00_axis_tstrb" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" NAME="m00_axis_tlast" SIGIS="undef" SIGNAME="axi_dma_mr_s_axis_s2mm_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axis_s2mm_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m00_axis_tready" SIGIS="undef" SIGNAME="axi_dma_mr_s_axis_s2mm_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axis_s2mm_tready"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="mr_buffer_et_0_m00_axis" NAME="m00_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="4"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m00_axis_tdata"/>
            <PORTMAP LOGICAL="TSTRB" PHYSICAL="m00_axis_tstrb"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m00_axis_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m00_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m00_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_switch_mr_M00_AXIS" NAME="s00_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s00_axis_tdata"/>
            <PORTMAP LOGICAL="TSTRB" PHYSICAL="s00_axis_tstrb"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="s00_axis_tlast"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s00_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s00_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M24_AXI" DATAWIDTH="32" NAME="s00_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="6"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s00_axi_awaddr"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="s00_axi_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s00_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s00_axi_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s00_axi_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s00_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s00_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s00_axi_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s00_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s00_axi_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s00_axi_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s00_axi_araddr"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="s00_axi_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s00_axi_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s00_axi_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s00_axi_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s00_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s00_axi_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s00_axi_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="27" FULLNAME="/ps8_0_axi_periph" HWVERSION="2.1" INSTANCE="ps8_0_axi_periph" IPTYPE="BUS" IS_ENABLE="1" MODCLASS="BUS" MODTYPE="axi_interconnect" VLNV="xilinx.com:ip:axi_interconnect:2.1">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_interconnect;v=v2_1;d=pg059-axi-interconnect.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="NUM_SI" VALUE="1"/>
        <PARAMETER NAME="NUM_MI" VALUE="31"/>
        <PARAMETER NAME="STRATEGY" VALUE="0"/>
        <PARAMETER NAME="ENABLE_ADVANCED_OPTIONS" VALUE="0"/>
        <PARAMETER NAME="ENABLE_PROTOCOL_CHECKERS" VALUE="0"/>
        <PARAMETER NAME="XBAR_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="PCHK_WAITS" VALUE="0"/>
        <PARAMETER NAME="PCHK_MAX_RD_BURSTS" VALUE="2"/>
        <PARAMETER NAME="PCHK_MAX_WR_BURSTS" VALUE="2"/>
        <PARAMETER NAME="SYNCHRONIZATION_STAGES" VALUE="3"/>
        <PARAMETER NAME="M00_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M01_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M02_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M03_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M04_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M05_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M06_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M07_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M08_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M09_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M10_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M11_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M12_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M13_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M14_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M15_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M16_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M17_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M18_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M19_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M20_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M21_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M22_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M23_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M24_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M25_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M26_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M27_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M28_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M29_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M30_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M31_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M32_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M33_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M34_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M35_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M36_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M37_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M38_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M39_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M40_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M41_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M42_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M43_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M44_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M45_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M46_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M47_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M48_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M49_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M50_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M51_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M52_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M53_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M54_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M55_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M56_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M57_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M58_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M59_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M60_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M61_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M62_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M63_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="M00_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M01_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M02_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M03_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M04_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M05_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M06_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M07_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M08_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M09_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M10_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M11_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M12_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M13_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M14_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M15_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M16_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M17_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M18_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M19_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M20_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M21_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M22_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M23_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M24_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M25_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M26_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M27_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M28_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M29_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M30_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M31_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M32_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M33_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M34_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M35_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M36_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M37_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M38_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M39_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M40_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M41_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M42_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M43_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M44_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M45_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M46_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M47_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M48_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M49_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M50_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M51_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M52_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M53_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M54_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M55_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M56_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M57_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M58_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M59_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M60_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M61_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M62_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M63_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S00_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S01_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S02_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S03_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S04_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S05_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S06_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S07_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S08_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S09_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S10_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S11_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S12_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S13_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S14_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S15_HAS_REGSLICE" VALUE="0"/>
        <PARAMETER NAME="S00_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S01_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S02_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S03_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S04_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S05_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S06_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S07_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S08_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S09_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S10_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S11_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S12_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S13_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S14_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="S15_HAS_DATA_FIFO" VALUE="0"/>
        <PARAMETER NAME="M00_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M01_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M02_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M03_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M04_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M05_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M06_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M07_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M08_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M09_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M10_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M11_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M12_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M13_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M14_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M15_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M16_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M17_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M18_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M19_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M20_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M21_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M22_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M23_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M24_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M25_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M26_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M27_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M28_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M29_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M30_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M31_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M32_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M33_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M34_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M35_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M36_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M37_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M38_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M39_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M40_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M41_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M42_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M43_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M44_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M45_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M46_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M47_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M48_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M49_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M50_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M51_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M52_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M53_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M54_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M55_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M56_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M57_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M58_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M59_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M60_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M61_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M62_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M63_ISSUANCE" VALUE="0"/>
        <PARAMETER NAME="M00_SECURE" VALUE="0"/>
        <PARAMETER NAME="M01_SECURE" VALUE="0"/>
        <PARAMETER NAME="M02_SECURE" VALUE="0"/>
        <PARAMETER NAME="M03_SECURE" VALUE="0"/>
        <PARAMETER NAME="M04_SECURE" VALUE="0"/>
        <PARAMETER NAME="M05_SECURE" VALUE="0"/>
        <PARAMETER NAME="M06_SECURE" VALUE="0"/>
        <PARAMETER NAME="M07_SECURE" VALUE="0"/>
        <PARAMETER NAME="M08_SECURE" VALUE="0"/>
        <PARAMETER NAME="M09_SECURE" VALUE="0"/>
        <PARAMETER NAME="M10_SECURE" VALUE="0"/>
        <PARAMETER NAME="M11_SECURE" VALUE="0"/>
        <PARAMETER NAME="M12_SECURE" VALUE="0"/>
        <PARAMETER NAME="M13_SECURE" VALUE="0"/>
        <PARAMETER NAME="M14_SECURE" VALUE="0"/>
        <PARAMETER NAME="M15_SECURE" VALUE="0"/>
        <PARAMETER NAME="M16_SECURE" VALUE="0"/>
        <PARAMETER NAME="M17_SECURE" VALUE="0"/>
        <PARAMETER NAME="M18_SECURE" VALUE="0"/>
        <PARAMETER NAME="M19_SECURE" VALUE="0"/>
        <PARAMETER NAME="M20_SECURE" VALUE="0"/>
        <PARAMETER NAME="M21_SECURE" VALUE="0"/>
        <PARAMETER NAME="M22_SECURE" VALUE="0"/>
        <PARAMETER NAME="M23_SECURE" VALUE="0"/>
        <PARAMETER NAME="M24_SECURE" VALUE="0"/>
        <PARAMETER NAME="M25_SECURE" VALUE="0"/>
        <PARAMETER NAME="M26_SECURE" VALUE="0"/>
        <PARAMETER NAME="M27_SECURE" VALUE="0"/>
        <PARAMETER NAME="M28_SECURE" VALUE="0"/>
        <PARAMETER NAME="M29_SECURE" VALUE="0"/>
        <PARAMETER NAME="M30_SECURE" VALUE="0"/>
        <PARAMETER NAME="M31_SECURE" VALUE="0"/>
        <PARAMETER NAME="M32_SECURE" VALUE="0"/>
        <PARAMETER NAME="M33_SECURE" VALUE="0"/>
        <PARAMETER NAME="M34_SECURE" VALUE="0"/>
        <PARAMETER NAME="M35_SECURE" VALUE="0"/>
        <PARAMETER NAME="M36_SECURE" VALUE="0"/>
        <PARAMETER NAME="M37_SECURE" VALUE="0"/>
        <PARAMETER NAME="M38_SECURE" VALUE="0"/>
        <PARAMETER NAME="M39_SECURE" VALUE="0"/>
        <PARAMETER NAME="M40_SECURE" VALUE="0"/>
        <PARAMETER NAME="M41_SECURE" VALUE="0"/>
        <PARAMETER NAME="M42_SECURE" VALUE="0"/>
        <PARAMETER NAME="M43_SECURE" VALUE="0"/>
        <PARAMETER NAME="M44_SECURE" VALUE="0"/>
        <PARAMETER NAME="M45_SECURE" VALUE="0"/>
        <PARAMETER NAME="M46_SECURE" VALUE="0"/>
        <PARAMETER NAME="M47_SECURE" VALUE="0"/>
        <PARAMETER NAME="M48_SECURE" VALUE="0"/>
        <PARAMETER NAME="M49_SECURE" VALUE="0"/>
        <PARAMETER NAME="M50_SECURE" VALUE="0"/>
        <PARAMETER NAME="M51_SECURE" VALUE="0"/>
        <PARAMETER NAME="M52_SECURE" VALUE="0"/>
        <PARAMETER NAME="M53_SECURE" VALUE="0"/>
        <PARAMETER NAME="M54_SECURE" VALUE="0"/>
        <PARAMETER NAME="M55_SECURE" VALUE="0"/>
        <PARAMETER NAME="M56_SECURE" VALUE="0"/>
        <PARAMETER NAME="M57_SECURE" VALUE="0"/>
        <PARAMETER NAME="M58_SECURE" VALUE="0"/>
        <PARAMETER NAME="M59_SECURE" VALUE="0"/>
        <PARAMETER NAME="M60_SECURE" VALUE="0"/>
        <PARAMETER NAME="M61_SECURE" VALUE="0"/>
        <PARAMETER NAME="M62_SECURE" VALUE="0"/>
        <PARAMETER NAME="M63_SECURE" VALUE="0"/>
        <PARAMETER NAME="S00_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S01_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S02_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S03_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S04_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S05_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S06_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S07_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S08_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S09_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S10_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S11_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S12_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S13_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S14_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="S15_ARB_PRIORITY" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_ps8_0_axi_periph_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="BUS"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="39" NAME="S00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S00_AXI_awlen" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awsize" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S00_AXI_awburst" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_awlock" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awcache" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_awqos" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_awvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_awready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="S00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="S00_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_wlast" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_wvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_wready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_bvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_bready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="39" NAME="S00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="S00_AXI_arlen" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arsize" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="S00_AXI_arburst" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_arlock" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arcache" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="S00_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="S00_AXI_arqos" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_arvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_arready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="S00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="S00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_rlast" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="S00_AXI_rvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="S00_AXI_rready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M00_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M00_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M00_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_wstrb" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M00_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M00_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M00_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M00_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M00_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M00_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M00_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M00_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M00_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M00_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M00_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M00_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axi_lite_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M01_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M01_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M01_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M01_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_awvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_AXI_awready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M01_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M01_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M01_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_wvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_AXI_wready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M01_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_AXI_bvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M01_AXI_bready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M01_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M01_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M01_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M01_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" NAME="M01_AXI_arvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_AXI_arready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M01_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M01_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M01_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" NAME="M01_AXI_rvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M01_AXI_rready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M02_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M02_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M03_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M03_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M04_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M04_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M05_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M05_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M06_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M06_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M07_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M07_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M08_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M08_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M09_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M09_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M10_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M10_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M11_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M11_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M12_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M12_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M13_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M13_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M14_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M14_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M15_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M15_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M16_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M16_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M17_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M17_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M18_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M18_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M19_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M19_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M20_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M20_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M21_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M21_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M22_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M22_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M23_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M23_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M24_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M24_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M25_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M25_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M26_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M26_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M27_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M27_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M28_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M28_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M29_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M29_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M30_ACLK" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M30_ARESETN" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M02_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M02_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M02_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M02_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M02_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M02_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M02_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M02_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M02_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M02_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M02_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M02_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M02_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M02_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M02_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M02_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M02_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M02_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M02_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M02_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M02_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M02_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M02_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M02_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M02_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M02_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M03_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M03_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M03_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M03_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M03_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M03_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M03_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M03_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M03_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M03_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M03_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M03_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M03_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M03_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M03_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M03_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M03_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M03_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M03_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M03_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M03_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M03_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M03_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M03_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M03_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M03_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M03_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M03_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M03_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M03_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M03_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M03_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M03_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M03_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M03_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M04_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M04_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M04_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M04_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M04_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M04_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M04_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M04_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M04_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M04_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M04_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M04_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M04_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M04_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M04_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M04_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M04_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M04_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M04_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M04_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M04_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M04_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M04_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M04_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M04_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M04_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M04_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M04_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M04_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M04_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M04_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M04_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M04_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M04_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M04_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M05_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M05_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M05_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M05_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M05_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M05_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M05_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M05_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M05_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M05_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M05_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M05_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M05_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M05_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M05_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M05_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M05_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M05_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M05_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M05_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M05_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M05_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M05_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M05_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M05_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M05_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M05_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M05_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M05_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M05_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M05_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M05_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M05_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M05_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M05_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M06_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M06_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M06_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M06_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M06_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M06_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M06_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M06_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M06_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M06_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M06_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M06_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M06_AXI_wstrb" SIGIS="undef"/>
        <PORT DIR="O" NAME="M06_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M06_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M06_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M06_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M06_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M06_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M06_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M06_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M06_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M06_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M06_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M06_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M06_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M06_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M06_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M06_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M06_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M06_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M06_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M06_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M06_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M06_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_s_axi_lite_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M07_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M07_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M07_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M07_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M07_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M07_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M07_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M07_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M07_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M07_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M07_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M07_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M07_AXI_wstrb" SIGIS="undef"/>
        <PORT DIR="O" NAME="M07_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M07_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M07_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M07_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M07_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M07_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M07_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M07_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M07_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M07_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M07_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M07_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M07_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M07_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M07_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M07_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M07_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M07_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M07_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M07_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M07_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M07_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_gen_s_axi_ctrl_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M08_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M08_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_awvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M08_AXI_awready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M08_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M08_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M08_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_wvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M08_AXI_wready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M08_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M08_AXI_bvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M08_AXI_bready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M08_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M08_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" NAME="M08_AXI_arvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M08_AXI_arready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M08_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M08_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M08_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" NAME="M08_AXI_rvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M08_AXI_rready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M09_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M09_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M09_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M09_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M09_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M09_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M09_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M09_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M09_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M09_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M09_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M09_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M09_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M09_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M09_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M09_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M09_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M09_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M09_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M09_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M09_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M09_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M09_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M09_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M09_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M09_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M09_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M09_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M09_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M09_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M09_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M09_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M09_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M09_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M09_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_0_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M10_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M10_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M10_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M10_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M10_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M10_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M10_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M10_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M10_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M10_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M10_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M10_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M10_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M10_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M10_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M10_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M10_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M10_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M10_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M10_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M10_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M10_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M10_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M10_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M10_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M10_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M10_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M10_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M10_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M10_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M10_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M10_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M10_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M10_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M10_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_avg_buffer_1_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M11_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M11_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M11_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M11_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M11_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M11_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M11_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M11_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M11_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M11_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M11_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M11_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M11_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M11_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M11_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M11_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M11_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M11_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M11_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M11_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M11_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M11_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M11_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M11_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M11_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M11_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M11_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M11_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M11_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M11_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M11_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M11_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M11_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M11_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M11_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M12_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M12_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M12_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M12_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M12_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M12_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M12_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M12_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M12_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M12_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M12_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M12_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M12_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M12_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M12_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M12_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M12_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M12_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M12_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M12_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M12_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M12_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M12_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M12_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M12_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M12_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M12_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M12_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M12_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M12_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M12_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M12_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M12_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M12_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M12_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M13_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M13_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M13_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M13_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M13_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M13_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M13_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M13_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M13_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M13_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M13_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M13_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M13_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M13_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M13_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M13_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M13_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M13_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M13_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M13_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M13_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M13_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M13_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M13_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M13_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M13_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M13_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M13_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M13_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M13_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M13_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M13_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M13_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M13_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M13_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M14_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M14_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M14_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M14_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M14_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M14_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M14_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M14_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M14_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M14_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M14_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M14_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M14_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M14_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M14_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M14_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M14_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M14_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M14_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M14_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M14_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M14_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M14_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M14_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M14_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M14_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M14_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M14_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M14_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M14_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M14_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M14_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M14_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M14_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M14_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M15_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M15_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M15_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M15_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M15_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M15_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M15_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M15_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M15_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M15_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M15_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M15_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M15_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M15_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M15_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M15_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M15_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M15_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M15_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M15_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M15_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M15_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M15_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M15_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M15_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M15_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M15_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M15_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M15_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M15_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M15_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M15_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M15_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M15_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M15_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_0_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M16_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M16_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M16_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M16_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M16_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M16_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M16_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M16_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M16_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M16_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M16_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M16_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M16_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M16_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M16_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M16_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M16_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M16_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M16_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M16_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M16_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M16_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M16_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M16_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M16_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M16_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M16_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M16_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M16_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M16_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M16_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M16_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M16_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M16_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M16_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_readout_v2_1_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M17_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M17_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M17_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M17_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M17_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M17_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M17_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M17_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M17_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M17_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M17_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M17_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M17_AXI_wstrb" SIGIS="undef"/>
        <PORT DIR="O" NAME="M17_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M17_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M17_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M17_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M17_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M17_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M17_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M17_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M17_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M17_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M17_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M17_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M17_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M17_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M17_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M17_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M17_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M17_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M17_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M17_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M17_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M17_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_avg_s_axi_ctrl_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M18_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M18_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M18_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M18_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M18_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M18_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M18_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M18_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M18_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M18_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M18_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M18_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M18_AXI_wstrb" SIGIS="undef"/>
        <PORT DIR="O" NAME="M18_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M18_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M18_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M18_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M18_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M18_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M18_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M18_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M18_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M18_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M18_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M18_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M18_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M18_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M18_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M18_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M18_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M18_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M18_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M18_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M18_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M18_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_buf_s_axi_ctrl_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M19_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M19_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M19_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M19_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M19_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M19_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M19_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M19_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M19_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M19_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M19_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M19_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M19_AXI_wstrb" SIGIS="undef"/>
        <PORT DIR="O" NAME="M19_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M19_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M19_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M19_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M19_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M19_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M19_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M19_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M19_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M19_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M19_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M19_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M19_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M19_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M19_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M19_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M19_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M19_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M19_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M19_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M19_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M19_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s_axi_lite_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M20_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M20_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M20_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M20_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M20_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M20_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M20_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M20_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M20_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M20_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M20_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M20_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M20_AXI_wstrb" SIGIS="undef"/>
        <PORT DIR="O" NAME="M20_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M20_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M20_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M20_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M20_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M20_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M20_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M20_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M20_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M20_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M20_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M20_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M20_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M20_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M20_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M20_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M20_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M20_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M20_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M20_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M20_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M20_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s_axi_lite_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M21_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M21_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M21_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M21_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M21_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M21_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M21_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M21_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M21_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M21_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M21_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M21_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M21_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M21_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M21_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M21_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M21_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M21_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M21_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M21_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M21_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M21_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M21_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M21_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M21_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M21_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M21_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M21_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M21_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M21_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M21_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M21_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M21_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M21_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M21_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_buffer_ddr_v1_0_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M22_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M22_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M22_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M22_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M22_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M22_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M22_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M22_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M22_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M22_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M22_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M22_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M22_AXI_wstrb" SIGIS="undef"/>
        <PORT DIR="O" NAME="M22_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M22_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M22_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M22_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M22_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M22_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M22_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M22_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M22_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M22_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M22_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M22_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M22_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M22_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M22_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M22_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M22_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M22_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M22_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M22_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M22_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M22_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_ddr_s_axi_ctrl_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M23_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M23_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M23_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M23_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M23_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M23_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M23_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M23_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M23_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M23_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M23_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M23_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M23_AXI_wstrb" SIGIS="undef"/>
        <PORT DIR="O" NAME="M23_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M23_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M23_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M23_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M23_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M23_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M23_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M23_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M23_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M23_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M23_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M23_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M23_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M23_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M23_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M23_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M23_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M23_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M23_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M23_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M23_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M23_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axis_switch_mr_s_axi_ctrl_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M24_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M24_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M24_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M24_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M24_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M24_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M24_AXI_awprot" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M24_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M24_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M24_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M24_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M24_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M24_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M24_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M24_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M24_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M24_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M24_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M24_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M24_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M24_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M24_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M24_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M24_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M24_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" LEFT="2" NAME="M24_AXI_arprot" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M24_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M24_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M24_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M24_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M24_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M24_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M24_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M24_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M24_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="mr_buffer_et_0_s00_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M25_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M25_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M25_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M25_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M25_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M25_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M25_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M25_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M25_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M25_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M25_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M25_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M25_AXI_wstrb" SIGIS="undef"/>
        <PORT DIR="O" NAME="M25_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M25_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M25_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M25_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M25_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M25_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M25_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M25_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M25_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M25_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M25_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M25_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M25_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M25_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M25_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M25_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M25_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M25_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M25_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M25_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M25_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M25_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s_axi_lite_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M26_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M26_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M26_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M26_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M26_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M26_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M26_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M26_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M26_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M26_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M26_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M26_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M26_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M26_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M26_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M26_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M26_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M26_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M26_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M26_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M26_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M26_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M26_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M26_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M26_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M26_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M26_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M26_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M26_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M26_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M26_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M26_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M26_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M26_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M26_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="axi_intc_0_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M27_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M27_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M27_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M27_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M27_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M27_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M27_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M27_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M27_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M27_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M27_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M27_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M27_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M27_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M27_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M27_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M27_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M27_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M27_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M27_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M27_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M27_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M27_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M27_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M27_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M27_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M27_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M27_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M27_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M27_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M27_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M27_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M27_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M27_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M27_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="attn_spi_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M28_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M28_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M28_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M28_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M28_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M28_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M28_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M28_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M28_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M28_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M28_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M28_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M28_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M28_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M28_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M28_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M28_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M28_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M28_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M28_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M28_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M28_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M28_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M28_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M28_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M28_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M28_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M28_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M28_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M28_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M28_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M28_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M28_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M28_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M28_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="dac_bias_spi_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M29_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M29_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M29_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M29_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M29_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M29_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M29_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M29_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M29_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M29_AXI_awvalid" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M29_AXI_awready" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M29_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M29_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M29_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M29_AXI_wvalid" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M29_AXI_wready" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M29_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M29_AXI_bvalid" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M29_AXI_bready" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M29_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M29_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M29_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M29_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M29_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M29_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M29_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M29_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M29_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" LEFT="0" NAME="M29_AXI_arvalid" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="M29_AXI_arready" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M29_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M29_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M29_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="M29_AXI_rvalid" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="M29_AXI_rready" RIGHT="0" SIGIS="undef" SIGNAME="lo_spi_s_axi_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M30_AXI_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M30_AXI_awlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_awsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_awburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_awlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_awcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_awprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_awregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_awqos" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_awvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M30_AXI_awready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="M30_AXI_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="M30_AXI_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M30_AXI_wlast" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_wvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M30_AXI_wready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M30_AXI_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M30_AXI_bvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M30_AXI_bready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="M30_AXI_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M30_AXI_arlen" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_arsize" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_arburst" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_arlock" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_arcache" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_arprot" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_arregion" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_arqos" SIGIS="undef"/>
        <PORT DIR="O" NAME="M30_AXI_arvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M30_AXI_arready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="M30_AXI_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="M30_AXI_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="M30_AXI_rlast" SIGIS="undef"/>
        <PORT DIR="I" NAME="M30_AXI_rvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="M30_AXI_rready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="S00_AXI_arid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_arid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="S00_AXI_awid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="S00_AXI_bid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_bid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="S00_AXI_rid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxigp0_rid"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="zynq_ultra_ps_e_0_M_AXI_HPM0_FPD" DATAWIDTH="128" NAME="S00_AXI" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="S00_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="S00_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="S00_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="S00_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="S00_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="S00_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="S00_AXI_awprot"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="S00_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="S00_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="S00_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="S00_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="S00_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="S00_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="S00_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="S00_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="S00_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="S00_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="S00_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="S00_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="S00_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="S00_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="S00_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="S00_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="S00_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="S00_AXI_arprot"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="S00_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="S00_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="S00_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="S00_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="S00_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="S00_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="S00_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="S00_AXI_rready"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="S00_AXI_arid"/>
            <PORTMAP LOGICAL="AWID" PHYSICAL="S00_AXI_awid"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="S00_AXI_bid"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="S00_AXI_rid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M00_AXI" DATAWIDTH="32" NAME="M00_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M00_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M00_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M00_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M00_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M00_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M00_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M00_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M00_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M00_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M00_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M00_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M00_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M00_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M00_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M00_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M00_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M00_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M00_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M00_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M00_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M00_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M00_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M00_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M00_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M00_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M00_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M00_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M00_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M00_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M00_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M00_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M00_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M00_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M00_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M00_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M01_AXI" DATAWIDTH="32" NAME="M01_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M01_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M01_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M01_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M01_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M01_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M01_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M01_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M01_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M01_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M01_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M01_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M01_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M01_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M01_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M01_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M01_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M01_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M01_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M01_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M01_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M01_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M01_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M01_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M01_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M01_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M01_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M01_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M01_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M01_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M01_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M01_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M01_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M01_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M01_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M01_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M02_AXI" DATAWIDTH="32" NAME="M02_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M02_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M02_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M02_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M02_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M02_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M02_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M02_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M02_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M02_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M02_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M02_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M02_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M02_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M02_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M02_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M02_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M02_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M02_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M02_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M02_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M02_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M02_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M02_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M02_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M02_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M02_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M02_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M02_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M02_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M02_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M02_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M02_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M02_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M02_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M02_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M03_AXI" DATAWIDTH="32" NAME="M03_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M03_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M03_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M03_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M03_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M03_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M03_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M03_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M03_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M03_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M03_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M03_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M03_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M03_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M03_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M03_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M03_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M03_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M03_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M03_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M03_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M03_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M03_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M03_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M03_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M03_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M03_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M03_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M03_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M03_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M03_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M03_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M03_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M03_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M03_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M03_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M04_AXI" DATAWIDTH="32" NAME="M04_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M04_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M04_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M04_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M04_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M04_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M04_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M04_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M04_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M04_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M04_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M04_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M04_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M04_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M04_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M04_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M04_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M04_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M04_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M04_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M04_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M04_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M04_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M04_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M04_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M04_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M04_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M04_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M04_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M04_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M04_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M04_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M04_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M04_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M04_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M04_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M05_AXI" DATAWIDTH="32" NAME="M05_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M05_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M05_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M05_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M05_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M05_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M05_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M05_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M05_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M05_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M05_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M05_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M05_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M05_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M05_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M05_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M05_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M05_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M05_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M05_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M05_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M05_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M05_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M05_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M05_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M05_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M05_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M05_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M05_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M05_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M05_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M05_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M05_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M05_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M05_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M05_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M06_AXI" DATAWIDTH="32" NAME="M06_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M06_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M06_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M06_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M06_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M06_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M06_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M06_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M06_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M06_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M06_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M06_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M06_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M06_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M06_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M06_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M06_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M06_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M06_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M06_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M06_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M06_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M06_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M06_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M06_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M06_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M06_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M06_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M06_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M06_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M06_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M06_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M06_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M06_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M06_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M06_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M07_AXI" DATAWIDTH="32" NAME="M07_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M07_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M07_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M07_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M07_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M07_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M07_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M07_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M07_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M07_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M07_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M07_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M07_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M07_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M07_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M07_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M07_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M07_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M07_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M07_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M07_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M07_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M07_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M07_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M07_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M07_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M07_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M07_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M07_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M07_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M07_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M07_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M07_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M07_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M07_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M07_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M08_AXI" DATAWIDTH="32" NAME="M08_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M08_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M08_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M08_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M08_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M08_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M08_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M08_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M08_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M08_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M08_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M08_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M08_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M08_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M08_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M08_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M08_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M08_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M08_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M08_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M08_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M08_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M08_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M08_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M08_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M08_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M08_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M08_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M08_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M08_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M08_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M08_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M08_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M08_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M08_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M08_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M09_AXI" DATAWIDTH="32" NAME="M09_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M09_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M09_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M09_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M09_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M09_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M09_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M09_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M09_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M09_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M09_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M09_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M09_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M09_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M09_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M09_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M09_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M09_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M09_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M09_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M09_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M09_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M09_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M09_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M09_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M09_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M09_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M09_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M09_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M09_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M09_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M09_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M09_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M09_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M09_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M09_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M10_AXI" DATAWIDTH="32" NAME="M10_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M10_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M10_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M10_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M10_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M10_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M10_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M10_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M10_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M10_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M10_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M10_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M10_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M10_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M10_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M10_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M10_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M10_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M10_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M10_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M10_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M10_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M10_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M10_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M10_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M10_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M10_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M10_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M10_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M10_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M10_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M10_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M10_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M10_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M10_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M10_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M11_AXI" DATAWIDTH="32" NAME="M11_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M11_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M11_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M11_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M11_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M11_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M11_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M11_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M11_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M11_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M11_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M11_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M11_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M11_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M11_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M11_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M11_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M11_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M11_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M11_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M11_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M11_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M11_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M11_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M11_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M11_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M11_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M11_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M11_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M11_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M11_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M11_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M11_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M11_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M11_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M11_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M12_AXI" DATAWIDTH="32" NAME="M12_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M12_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M12_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M12_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M12_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M12_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M12_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M12_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M12_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M12_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M12_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M12_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M12_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M12_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M12_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M12_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M12_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M12_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M12_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M12_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M12_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M12_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M12_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M12_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M12_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M12_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M12_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M12_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M12_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M12_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M12_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M12_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M12_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M12_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M12_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M12_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M13_AXI" DATAWIDTH="32" NAME="M13_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M13_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M13_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M13_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M13_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M13_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M13_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M13_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M13_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M13_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M13_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M13_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M13_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M13_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M13_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M13_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M13_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M13_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M13_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M13_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M13_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M13_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M13_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M13_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M13_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M13_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M13_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M13_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M13_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M13_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M13_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M13_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M13_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M13_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M13_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M13_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M14_AXI" DATAWIDTH="32" NAME="M14_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M14_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M14_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M14_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M14_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M14_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M14_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M14_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M14_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M14_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M14_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M14_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M14_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M14_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M14_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M14_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M14_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M14_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M14_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M14_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M14_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M14_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M14_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M14_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M14_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M14_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M14_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M14_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M14_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M14_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M14_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M14_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M14_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M14_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M14_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M14_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M15_AXI" DATAWIDTH="32" NAME="M15_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M15_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M15_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M15_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M15_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M15_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M15_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M15_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M15_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M15_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M15_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M15_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M15_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M15_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M15_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M15_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M15_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M15_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M15_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M15_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M15_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M15_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M15_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M15_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M15_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M15_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M15_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M15_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M15_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M15_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M15_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M15_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M15_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M15_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M15_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M15_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M16_AXI" DATAWIDTH="32" NAME="M16_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M16_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M16_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M16_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M16_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M16_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M16_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M16_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M16_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M16_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M16_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M16_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M16_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M16_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M16_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M16_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M16_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M16_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M16_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M16_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M16_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M16_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M16_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M16_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M16_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M16_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M16_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M16_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M16_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M16_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M16_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M16_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M16_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M16_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M16_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M16_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M17_AXI" DATAWIDTH="32" NAME="M17_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M17_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M17_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M17_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M17_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M17_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M17_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M17_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M17_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M17_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M17_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M17_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M17_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M17_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M17_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M17_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M17_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M17_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M17_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M17_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M17_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M17_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M17_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M17_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M17_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M17_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M17_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M17_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M17_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M17_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M17_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M17_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M17_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M17_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M17_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M17_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M18_AXI" DATAWIDTH="32" NAME="M18_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M18_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M18_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M18_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M18_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M18_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M18_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M18_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M18_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M18_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M18_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M18_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M18_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M18_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M18_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M18_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M18_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M18_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M18_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M18_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M18_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M18_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M18_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M18_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M18_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M18_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M18_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M18_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M18_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M18_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M18_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M18_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M18_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M18_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M18_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M18_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M19_AXI" DATAWIDTH="32" NAME="M19_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M19_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M19_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M19_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M19_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M19_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M19_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M19_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M19_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M19_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M19_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M19_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M19_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M19_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M19_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M19_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M19_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M19_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M19_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M19_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M19_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M19_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M19_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M19_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M19_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M19_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M19_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M19_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M19_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M19_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M19_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M19_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M19_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M19_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M19_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M19_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M20_AXI" DATAWIDTH="32" NAME="M20_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M20_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M20_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M20_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M20_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M20_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M20_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M20_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M20_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M20_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M20_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M20_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M20_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M20_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M20_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M20_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M20_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M20_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M20_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M20_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M20_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M20_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M20_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M20_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M20_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M20_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M20_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M20_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M20_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M20_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M20_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M20_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M20_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M20_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M20_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M20_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M21_AXI" DATAWIDTH="32" NAME="M21_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M21_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M21_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M21_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M21_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M21_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M21_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M21_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M21_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M21_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M21_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M21_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M21_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M21_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M21_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M21_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M21_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M21_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M21_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M21_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M21_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M21_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M21_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M21_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M21_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M21_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M21_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M21_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M21_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M21_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M21_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M21_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M21_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M21_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M21_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M21_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M22_AXI" DATAWIDTH="32" NAME="M22_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M22_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M22_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M22_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M22_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M22_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M22_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M22_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M22_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M22_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M22_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M22_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M22_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M22_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M22_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M22_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M22_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M22_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M22_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M22_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M22_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M22_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M22_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M22_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M22_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M22_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M22_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M22_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M22_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M22_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M22_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M22_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M22_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M22_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M22_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M22_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M23_AXI" DATAWIDTH="32" NAME="M23_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M23_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M23_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M23_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M23_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M23_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M23_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M23_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M23_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M23_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M23_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M23_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M23_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M23_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M23_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M23_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M23_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M23_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M23_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M23_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M23_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M23_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M23_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M23_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M23_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M23_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M23_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M23_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M23_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M23_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M23_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M23_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M23_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M23_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M23_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M23_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M24_AXI" DATAWIDTH="32" NAME="M24_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M24_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M24_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M24_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M24_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M24_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M24_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M24_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M24_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M24_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M24_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M24_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M24_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M24_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M24_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M24_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M24_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M24_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M24_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M24_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M24_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M24_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M24_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M24_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M24_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M24_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M24_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M24_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M24_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M24_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M24_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M24_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M24_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M24_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M24_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M24_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M25_AXI" DATAWIDTH="32" NAME="M25_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M25_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M25_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M25_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M25_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M25_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M25_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M25_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M25_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M25_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M25_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M25_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M25_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M25_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M25_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M25_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M25_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M25_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M25_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M25_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M25_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M25_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M25_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M25_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M25_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M25_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M25_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M25_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M25_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M25_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M25_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M25_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M25_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M25_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M25_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M25_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M26_AXI" DATAWIDTH="32" NAME="M26_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M26_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M26_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M26_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M26_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M26_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M26_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M26_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M26_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M26_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M26_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M26_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M26_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M26_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M26_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M26_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M26_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M26_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M26_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M26_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M26_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M26_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M26_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M26_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M26_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M26_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M26_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M26_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M26_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M26_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M26_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M26_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M26_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M26_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M26_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M26_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M27_AXI" DATAWIDTH="32" NAME="M27_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M27_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M27_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M27_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M27_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M27_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M27_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M27_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M27_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M27_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M27_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M27_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M27_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M27_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M27_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M27_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M27_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M27_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M27_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M27_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M27_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M27_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M27_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M27_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M27_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M27_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M27_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M27_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M27_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M27_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M27_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M27_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M27_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M27_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M27_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M27_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M28_AXI" DATAWIDTH="32" NAME="M28_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M28_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M28_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M28_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M28_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M28_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M28_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M28_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M28_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M28_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M28_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M28_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M28_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M28_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M28_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M28_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M28_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M28_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M28_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M28_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M28_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M28_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M28_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M28_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M28_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M28_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M28_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M28_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M28_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M28_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M28_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M28_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M28_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M28_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M28_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M28_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M29_AXI" DATAWIDTH="32" NAME="M29_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M29_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M29_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M29_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M29_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M29_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M29_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M29_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M29_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M29_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M29_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M29_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M29_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M29_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M29_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M29_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M29_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M29_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M29_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M29_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M29_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M29_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M29_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M29_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M29_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M29_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M29_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M29_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M29_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M29_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M29_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M29_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M29_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M29_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M29_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M29_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M30_AXI" DATAWIDTH="32" NAME="M30_AXI" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="M30_AXI_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="M30_AXI_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="M30_AXI_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="M30_AXI_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="M30_AXI_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="M30_AXI_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="M30_AXI_awprot"/>
            <PORTMAP LOGICAL="AWREGION" PHYSICAL="M30_AXI_awregion"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="M30_AXI_awqos"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="M30_AXI_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="M30_AXI_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="M30_AXI_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="M30_AXI_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="M30_AXI_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="M30_AXI_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="M30_AXI_wready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="M30_AXI_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="M30_AXI_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="M30_AXI_bready"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="M30_AXI_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="M30_AXI_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="M30_AXI_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="M30_AXI_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="M30_AXI_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="M30_AXI_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="M30_AXI_arprot"/>
            <PORTMAP LOGICAL="ARREGION" PHYSICAL="M30_AXI_arregion"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="M30_AXI_arqos"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="M30_AXI_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="M30_AXI_arready"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="M30_AXI_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="M30_AXI_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="M30_AXI_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="M30_AXI_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="M30_AXI_rready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="25" FULLNAME="/psf_spi" HWVERSION="3.2" INSTANCE="psf_spi" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="MEMORY_CNTLR" MODTYPE="axi_quad_spi" VLNV="xilinx.com:ip:axi_quad_spi:3.2">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=axi_quad_spi;v=v3_2;d=pg153-axi-quad-spi.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="AXI_LITE" NAME="Reg" RANGE="4096" USAGE="register">
          <REGISTERS>
            <REGISTER NAME="XIP_Config_Reg">
              <PROPERTY NAME="DESCRIPTION" VALUE="XIP Configuration Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x60"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="CPHA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPHA&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="XIP_Status_Reg">
              <PROPERTY NAME="DESCRIPTION" VALUE="XIP Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x64"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="false"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x1"/>
              <FIELDS>
                <FIELD NAME="RX_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receiver Empty.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="RX_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receiver Full.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Master_MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Master mode fault. This bit is set to 1 if the spisel line is deasserted.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA Error.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="AXI_Transaction_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="AXI Transaction Error.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SRR">
              <PROPERTY NAME="DESCRIPTION" VALUE="Software Reset Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x40"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="The only allowed operation on this register is a write of 0x0000000a, which resets the AXI Quad SPI core.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPICR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Control Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x60"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x180"/>
              <FIELDS>
                <FIELD NAME="LOOP">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Local loopback mode&#xA;Enables local loopback operation and is functional only in standard SPI master mode.&#xA;When set to:   0 - Normal operation.   1 - Loopback mode. The transmitter output is internally connected to the receiver input. The receiver and transmitter operate normally, except that received data (from remote slave) is ignored.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="SPE">
                  <PROPERTY NAME="DESCRIPTION" VALUE="SPI system enable&#xA;When set to:&#xA;  0 - SPI system disabled. Both master and slave outputs are in 3-state and slave inputs are ignored.&#xA;  1 - SPI system enabled. Master outputs active (for example, IO0 (MOSI) and SCK in idle state) and slave outputs become active if SS becomes asserted. The master starts transferring when transmit data is available.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Master">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Master (SPI master mode)&#xA;Setting this bit configures the SPI device as a master or a slave.&#xA;When set to:&#xA;  0 - Slave configuration.&#xA;  1 - Master configuration.&#xA;In dual/quad SPI mode only the master mode of the core is allowed.&#xA;Standard Slave mode is not supported for SCK ratio = 2&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Clock polarity&#xA;Setting this bit defines clock polarity.&#xA;When set to:&#xA;  0 - Active-High clock; SCK idles Low.&#xA;  1 - Active-Low clock; SCK idles High.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPHA">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Clock phase&#xA;Setting this bit selects one of two fundamentally different transfer formats.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_FIFO_Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit FIFO reset&#xA;When written to 1, this bit forces a reset of the transmit FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0.&#xA;When set to:   0 - Transmit FIFO normal operation.   1 - Reset transmit FIFO pointer&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="RX_FIFO_Reset">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive FIFO reset&#xA;When written to 1, this bit forces a reset of the receive FIFO to the empty condition. One AXI clock cycle after reset, this bit is again set to 0.&#xA;When set to:   0 - Receive FIFO normal operation.   1 - Reset receive FIFO pointer.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Manual_Slave_Select_Assertion_Enable">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Manual slave select assertion enable&#xA;This bit forces the data in the slave select register to be asserted on the slave select output anytime the device is configured as a master and the device is enabled (SPE asserted).&#xA;This bit has no effect on slave operation.&#xA;When set to:   0 - Slave select output asserted by master core logic.   1 - Slave select output follows data in slave select register. The manual slave assertion mode is supported in standard SPI mode only.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Master_Transaction_Inhibit">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Master transaction inhibit&#xA;This bit inhibits master transactions.&#xA;This bit has no effect on slave operation.&#xA;When set to:   0 - Master transactions enabled.   1 - Master transactions disabled. This bit immediately inhibits the transaction. Setting this bit while transfer is in progress would result in unpredictable outcome&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="LSB_First">
                  <PROPERTY NAME="DESCRIPTION" VALUE="LSB first&#xA;This bit selects LSB first data transfer format.&#xA;The default transfer format is MSB first.&#xA;When set to:&#xA;  0 - MSB first transfer format.&#xA;  1 - LSB first transfer format.&#xA;In Dual/Quad SPI mode, only the MSB first mode of the core is allowed.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPISR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x64"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0A5"/>
              <FIELDS>
                <FIELD NAME="RX_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive Empty.&#xA;When a receive FIFO exists, this bit is set High when the receive FIFO is empty. The occupancy of the FIFO is decremented with each FIFO read operation.&#xA;Note: When FIFOs do not exist, this bit is set High when the receive register has been read (this option is available only in standard SPI mode). This bit is cleared at the end of a successful SPI transfer. For dual/quad SPI mode, the FIFO is always present in the core.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="RX_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive full.&#xA;When a receive FIFO exists, this bit is set High when the receive FIFO is full. The occupancy of the FIFO is incremented with the completion of each SPI transaction.&#xA;Note: When FIFOs do not exist, this bit is set High when an SPI transfer has completed (this option is available only in standard SPI mode). Rx_Empty and Rx_Full are complements in this case&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit empty.&#xA;When a transmit FIFO exists, this bit is set to High when the transmit FIFO is empty. This bit goes High as soon as the TX FIFO becomes empty. While this bit is High, the last byte of the data that is to be transmitted would still be in the pipeline.&#xA;The occupancy of the FIFO is decremented with the completion of each SPI transfer.&#xA;Note: When FIFOs do not exist, this bit is set with the completion of an SPI transfer (this option is available only in standard SPI mode). Either with or without FIFOs, this bit is cleared on an AXI write to the FIFO or transmit register. For Dual/Quad SPI mode, the FIFO is always present in the core.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit full.&#xA;When a transmit FIFO exists, this bit is set High when the transmit FIFO is full.&#xA;Note: When FIFOs do not exist, this bit is set High when an AXI write to the transmit register has been made (this option is available only in standard SPI mode). This bit is cleared when the SPI transfer is completed&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Mode-fault error flag.&#xA;This flag is set if the SS signal goes active while the SPI device is configured as a master. MODF is automatically cleared by reading the SPISR. &#xA;A Low-to-High MODF transition generates a single-cycle strobe interrupt.   0 - No error.   1 - Error condition detected&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Mode_Select">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave_Mode_Select flag.&#xA;This flag is asserted when the core is configured in slave mode. Slave_Mode_Select is activated as soon as the master SPI core asserts the chip select pin for the core.&#xA;1 - Default in standard mode.&#xA;0 - Asserted when core configured in slave mode and selected by external SPI master.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA_Error flag.&#xA;When set to:   0 - Default.   1 - The CPOL and CPHA are set to 01 or 10. When the SPI memory is chosen as either Winbond, Micron or Spansion, and CPOL and CPHA are configured as 01 or 10, this bit is set.&#xA;These memories support CPOL=CPHA mode in 00 or in 11 mode. CPOL_CPHA_Error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_mode_error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave mode error flag.&#xA;When set to:   1 - This bit is set when the core is configured with dual or quad SPI mode and the master is set to 0 in the control register (SPICR).   0 - Master mode is set in the control register (SPICR). Note: Quad SPI mode, only the master mode of the core is allowed. Slave mode error flag is only applicable when the core is configured either in dual or qu ad mode in legacy or enhanced AXI4 mode interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MSB_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="MSB error flag.&#xA;When set to:   0 - Default.   1 - This bit is set when the core is configured to transfer the SPI transactions in either dual or quad SPI mode and LSB first bit is set in the control register (SPICR). Note: In dual/quad SPI mode, only the MSB first mode of the core is allowed. MSB error flag is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Loopback_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Loopback error flag.&#xA;When set to:   0 - Default. The loopback bit in the control register is at default state.   1 - When the SPI command, address, and data bits are set to be transferred in other than standard SPI protocol mode and this bit is set in control register (SPICR). Note: Loopback is only allowed when the core is configured in standard mode. Other modes setting of the bit causes an error and the interrupt bit is set in legacy or enhanced mode AXI4 interface&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Command_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Command error flag.&#xA;When set to:   0 - Default.   1 - When the core is configured in dual/quad SPI mode and the first entry in the SPI DTR FIFO (after reset) do not match with the supported command list for the particular memory, this bit is set. Note: Command error is only applicable when the core is configured either in dual or quad mode in legacy or enhanced mode AXI4 interface.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_SSR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Slave Select Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x70"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0xFFFF"/>
              <FIELDS>
                <FIELD NAME="Selected_Slave">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Active-Low, one-hot encoded slave select&#xA;The slaves are numbered right to left starting at zero with the LSB. The slave numbers correspond to the indexes of signal SS&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="4"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_TXFIFO_OR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Transmit FIFO Occupancy Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x74"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Occupancy_Value">
                  <PROPERTY NAME="DESCRIPTION" VALUE="The binary value plus 1 yields the occupancy.&#xA;Bit width is log(FIFO Depth). &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_RXFIFO_OR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Receive FIFO Occupancy Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x78"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="Occupancy_Value">
                  <PROPERTY NAME="DESCRIPTION" VALUE="The binary value plus 1 yields the occupancy. &#xA;Bit width is log(FIFO Depth). &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="32"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="DGIER">
              <PROPERTY NAME="DESCRIPTION" VALUE="Device Global Interrupt Enable Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x1C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="GIE">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Global Interrupt Enable.&#xA;Allows passing all individually enabled interrupts to the interrupt controller.&#xA;When set to:   0 - Disabled.   1 - Enabled. &#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="31"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="31"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_DTR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Data Transmit Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x68"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="write-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="TX_Data">
                  <PROPERTY NAME="DESCRIPTION" VALUE="SPI Transmit Data.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="write-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="SPI_DRR">
              <PROPERTY NAME="DESCRIPTION" VALUE="SPI Data Receive Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x6C"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-only"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="RX_Data">
                  <PROPERTY NAME="DESCRIPTION" VALUE="SPI Receive Data&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-only"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="8"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IPISR">
              <PROPERTY NAME="DESCRIPTION" VALUE="IP Interrupt Status Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x20"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Mode-fault error.&#xA;This interrupt is generated if the SS signal goes active while the SPI device is configured as a master. This bit is set immediately on SS going active.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave mode-fault error.&#xA;This interrupt is generated if the SS signal goes active while the SPI device is configured as a slave, but is not enabled.&#xA;This bit is set immediately on SS going active and continually set if SS is active and the device is not enabled&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit register/FIFO empty.&#xA;It is set when the last byte of data has been transferred out to the external flash memory.&#xA;In the context of the M68HC11 reference manual, when configured without FIFOs, this interrupt is equivalent in information content to the complement of the SPI transfer complete flag (SPIF ) interrupt bit.&#xA;In master mode if this bit is set to 1, no more SPI transfers are permitted&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Underrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit register/FIFO underrun.&#xA;This bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register when data is requested from an empty transmit register/FIFO by the SPI core logic to perform a SPI transfer.&#xA;This can occur only when the SPI device is configured as a slave in standard SPI configuration and is enabled by the SPE bit as set. All zeros are loaded in the shift register and transmitted by the slave in an under-run condition&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data receive register/FIFO full.&#xA;Without FIFOs, this bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register (An element can be a byte, half-word, or word depending on the value of Transfer Width).&#xA;With FIFOs, this bit is set at the end of the SPI element transfer, when the receive FIFO has been completely filled by a one-clock period strobe to the interrupt register.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Overrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data receive register/FIFO overrun.&#xA;This bit is set by a one-clock period strobe to the interrupt register when an attempt to write data to a full receive register or FIFO is made by the SPI core logic to complete a SPI transfer.&#xA;This can occur when the SPI device is in either master or slave mode (in standard SPI mode) or if the IP is configured in SPI master mode (dual or quad SPI mode).&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TXFIFO_Half_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit FIFO half empty.&#xA;In standard SPI configuration, IPISR Bit[6] is the transmit FIFO half-empty interrupt. &#xA;In dual or quad SPI configuration, based on the FIFO depth, this bit is set at half-empty condition.&#xA;Note: This interrupt exists only if the AXI Quad SPI core is configured with FIFOs (In standard, dual or quad SPI mode).&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Select_Mode">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave select mode.&#xA;The assertion of this bit is applicable only when the core is configured in slave mode in standard SPI configuration. &#xA;This bit is set when the other SPI master core selects the core by asserting the slave select line. This bit is set by a one-clock period strobe to the interrupt register.&#xA;Note: This bit is applicable only in standard SPI slave mode&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Not_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DRR not empty.&#xA;The assertion of this bit is applicable only in the case where FIFO Depth is 16 or 256 and the core is configured in slave mode and standard SPI mode. This bit is set when the DRR FIFO receives the first data value during the SPI transaction.&#xA;This bit is set by a one-clock period strobe to the interrupt register when the core receives the first data beat.&#xA;Note: The assertion of this bit is applicable only when the FIFO Depth parameter is 16 or 256 and the core is configured in slave mode in standard SPI mode. When FIFO Depth is set to 0, this bit always returns 0. This bit has no significance in dual/quad mode&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA error.&#xA;This flag is asserted when:&#xA;  The core is configured in either dual or quad SPI mode and&#xA;  The CPOL - CPHA control register bits are set to 01 or 10.&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Mode_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="I/O mode instruction error.&#xA;This flag is asserted when:&#xA;  The core is configured in either dual or quad SPI mode and&#xA;  The core is configured in master = 0 in control register (SPICR(2)).&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MSB_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="MSB error.&#xA;This flag is asserted when:&#xA;  The core is configured in either dual or quad SPI mode and&#xA;  The LSB First bit in the control register (SPICR) is set to 1.&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Loopback_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Loopback error.&#xA;This flag is asserted when:&#xA;  The core is configured in dual or quad SPI transfer mode and&#xA;  The LOOP bit is set in control register (SPICR(0)).&#xA;In standard SPI mode, this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Command_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Command error.&#xA;This flag is asserted when:   The core is configured in dual/quad SPI mode and   The first entry in the SPI DTR FIFO (after reset) does not match with the supported command list for particular memory. When the SPI command in DTR FIFO does not match with the internal supported command list, the core completes the SPI transactions in standard SPI format. This bit is set to show this behavior of the core.&#xA;In standard SPI mode this bit is always in default state.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE="oneToToggle"/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
            <REGISTER NAME="IPIER">
              <PROPERTY NAME="DESCRIPTION" VALUE="IP Interrupt Enable Register"/>
              <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0x28"/>
              <PROPERTY NAME="SIZE" VALUE="32"/>
              <PROPERTY NAME="ACCESS" VALUE="read-write"/>
              <PROPERTY NAME="IS_ENABLED" VALUE="true"/>
              <PROPERTY NAME="RESET_VALUE" VALUE="0x0"/>
              <FIELDS>
                <FIELD NAME="MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Mode-fault error flag.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="0"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_MODF">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave mode-fault error flag.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="1"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit register/FIFO empty.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="2"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DTR_Underrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data transmit FIFO underrun.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="3"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Full">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Data receive register/FIFO full.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="4"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Overrun">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Receive FIFO overrun.&#xA;  0 - Disabled.&#xA;  1 - Enabled.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="5"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="TX_FIFO_Half_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Transmit FIFO half empty.   0 - Disabled.   1 - Enabled. Note: This bit is meaningful only if the AXI Quad SPI core is configured with FIFOs.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="6"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Select_Mode">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Slave_Select_Mode.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in slave mode by selecting the active-Low status on spisel.&#xA;In master mode, setting this bit has no effect.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="7"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="DRR_Not_Empty">
                  <PROPERTY NAME="DESCRIPTION" VALUE="DRR_Not_Empty.   0 - Disabled.   1 - Enabled. Note: The setting of this bit is applicable only when FIFO Depth is set to 1 and the core is configured in slave mode of standard SPI mode.&#xA;If FIFO Depth is set to 0, the setting of this bit has no effect. This is allowed only in standard SPI configuration. It means this bit is not set in the IPIER register. Therefore, this bit should only be used when FIFO Depth is set to 1 and when the core is configured in slave mode.&#xA;This bit has no significance in dual or quad mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="8"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="CPOL_CPHA_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="CPOL_CPHA error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="9"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Slave_Mode_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="I/O mode instruction error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="10"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="MSB_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="MSB_Error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="11"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Loopback_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Loopback Error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="12"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
                <FIELD NAME="Command_Error">
                  <PROPERTY NAME="DESCRIPTION" VALUE="Command_Error.   0 - Disabled.   1 - Enabled. This bit is applicable only when the core is configured in dual or quad SPI mode.&#xA;"/>
                  <PROPERTY NAME="ADDRESS_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="ACCESS" VALUE="read-write"/>
                  <PROPERTY NAME="MODIFIED_READ_VALUES" VALUE=""/>
                  <PROPERTY NAME="WRITE_CONSTRAINT" VALUE="0"/>
                  <PROPERTY NAME="READ_ACTION" VALUE=""/>
                  <PROPERTY NAME="BIT_OFFSET" VALUE="13"/>
                  <PROPERTY NAME="BIT_WIDTH" VALUE="1"/>
                </FIELD>
              </FIELDS>
            </REGISTER>
          </REGISTERS>
        </ADDRESSBLOCK>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="Async_Clk" VALUE="0"/>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_SELECT_XPM" VALUE="0"/>
        <PARAMETER NAME="C_SUB_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_INSTANCE" VALUE="axi_quad_spi_inst"/>
        <PARAMETER NAME="C_SPI_MEM_ADDR_BITS" VALUE="24"/>
        <PARAMETER NAME="C_TYPE_OF_AXI4_INTERFACE" VALUE="0"/>
        <PARAMETER NAME="C_XIP_MODE" VALUE="0"/>
        <PARAMETER NAME="C_XIP_PERF_MODE" VALUE="1"/>
        <PARAMETER NAME="C_BYTE_LEVEL_INTERRUPT_EN" VALUE="0"/>
        <PARAMETER NAME="C_UC_FAMILY" VALUE="1"/>
        <PARAMETER NAME="C_FIFO_DEPTH" VALUE="16"/>
        <PARAMETER NAME="C_SCK_RATIO" VALUE="16"/>
        <PARAMETER NAME="C_DUAL_QUAD_MODE" VALUE="0"/>
        <PARAMETER NAME="C_NUM_SS_BITS" VALUE="4"/>
        <PARAMETER NAME="C_NUM_TRANSFER_BITS" VALUE="8"/>
        <PARAMETER NAME="C_NEW_SEQ_EN" VALUE="1"/>
        <PARAMETER NAME="C_SPI_MODE" VALUE="0"/>
        <PARAMETER NAME="C_USE_STARTUP" VALUE="0"/>
        <PARAMETER NAME="C_USE_STARTUP_EXT" VALUE="0"/>
        <PARAMETER NAME="C_SPI_MEMORY" VALUE="1"/>
        <PARAMETER NAME="C_S_AXI_ADDR_WIDTH" VALUE="7"/>
        <PARAMETER NAME="C_S_AXI_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXI4_ADDR_WIDTH" VALUE="24"/>
        <PARAMETER NAME="C_S_AXI4_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_S_AXI4_ID_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_SHARED_STARTUP" VALUE="0"/>
        <PARAMETER NAME="C_LSB_STUP" VALUE="0"/>
        <PARAMETER NAME="C_USE_STARTUP_INT" VALUE="0"/>
        <PARAMETER NAME="UC_FAMILY" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_psf_spi_0"/>
        <PARAMETER NAME="Master_mode" VALUE="1"/>
        <PARAMETER NAME="FIFO_INCLUDED" VALUE="1"/>
        <PARAMETER NAME="Multiples16" VALUE="1"/>
        <PARAMETER NAME="C_SCK_RATIO1" VALUE="1"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="QSPI_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA025B000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA025BFFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="ext_spi_clk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="6" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M30_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="io0_i" SIGIS="undef"/>
        <PORT DIR="O" NAME="io0_o" SIGIS="undef" SIGNAME="psf_spi_io0_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="SDI"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="io0_t" SIGIS="undef"/>
        <PORT DIR="I" NAME="io1_i" SIGIS="undef" SIGNAME="External_Ports_SDO">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="SDO"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="io1_o" SIGIS="undef"/>
        <PORT DIR="O" NAME="io1_t" SIGIS="undef"/>
        <PORT DIR="I" NAME="sck_i" SIGIS="undef"/>
        <PORT DIR="O" NAME="sck_o" SIGIS="undef" SIGNAME="psf_spi_sck_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="SCLK"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="sck_t" SIGIS="undef"/>
        <PORT DIR="I" LEFT="3" NAME="ss_i" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="3" NAME="ss_o" RIGHT="0" SIGIS="undef" SIGNAME="psf_spi_ss_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="S"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="ss_t" SIGIS="undef"/>
        <PORT DIR="O" NAME="ip2intc_irpt" SENSITIVITY="EDGE_RISING" SIGIS="INTERRUPT"/>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="SPI_0" TYPE="INITIATOR" VLNV="xilinx.com:interface:spi:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="IO0_I" PHYSICAL="io0_i"/>
            <PORTMAP LOGICAL="IO0_O" PHYSICAL="io0_o"/>
            <PORTMAP LOGICAL="IO0_T" PHYSICAL="io0_t"/>
            <PORTMAP LOGICAL="IO1_I" PHYSICAL="io1_i"/>
            <PORTMAP LOGICAL="IO1_O" PHYSICAL="io1_o"/>
            <PORTMAP LOGICAL="IO1_T" PHYSICAL="io1_t"/>
            <PORTMAP LOGICAL="SCK_I" PHYSICAL="sck_i"/>
            <PORTMAP LOGICAL="SCK_O" PHYSICAL="sck_o"/>
            <PORTMAP LOGICAL="SCK_T" PHYSICAL="sck_t"/>
            <PORTMAP LOGICAL="SS_I" PHYSICAL="ss_i"/>
            <PORTMAP LOGICAL="SS_O" PHYSICAL="ss_o"/>
            <PORTMAP LOGICAL="SS_T" PHYSICAL="ss_t"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M30_AXI" DATAWIDTH="32" NAME="AXI_LITE" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="7"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="12" FULLNAME="/qick_processor_0" HWVERSION="2.0" INSTANCE="qick_processor_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="qick_processor" VLNV="Fermi:user:qick_processor:2.0">
      <DOCUMENTS/>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="" INTERFACE="s_axi" NAME="reg0" RANGE="64" USAGE="register"/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="PMEM_AW" VALUE="10"/>
        <PARAMETER NAME="DMEM_AW" VALUE="10"/>
        <PARAMETER NAME="WMEM_AW" VALUE="10"/>
        <PARAMETER NAME="REG_AW" VALUE="4"/>
        <PARAMETER NAME="IN_PORT_QTY" VALUE="2"/>
        <PARAMETER NAME="OUT_DPORT_QTY" VALUE="2"/>
        <PARAMETER NAME="OUT_WPORT_QTY" VALUE="8"/>
        <PARAMETER NAME="LFSR" VALUE="0"/>
        <PARAMETER NAME="DIVIDER" VALUE="0"/>
        <PARAMETER NAME="ARITH" VALUE="1"/>
        <PARAMETER NAME="TIME_READ" VALUE="1"/>
        <PARAMETER NAME="DUAL_CORE" VALUE="0"/>
        <PARAMETER NAME="IO_CTRL" VALUE="1"/>
        <PARAMETER NAME="DEBUG" VALUE="0"/>
        <PARAMETER NAME="TNET" VALUE="0"/>
        <PARAMETER NAME="CUSTOM_PERIPH" VALUE="0"/>
        <PARAMETER NAME="OUT_DPORT_DW" VALUE="8"/>
        <PARAMETER NAME="OUT_TRIG_QTY" VALUE="2"/>
        <PARAMETER NAME="FIFO_DEPTH" VALUE="9"/>
        <PARAMETER NAME="EXT_FLAG" VALUE="0"/>
        <PARAMETER NAME="QCOM" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_qick_processor_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA025D000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA025DFFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="t_clk_i" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="t_resetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="199998000" DIR="I" NAME="c_clk_i" SIGIS="clk" SIGNAME="clk_core_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_core" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="c_resetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_core_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_core" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="ps_clk_i" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="ps_resetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="proc_start_i" SIGIS="undef" SIGNAME="External_Ports_PMOD1_0_LS">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="PMOD1_0_LS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="proc_stop_i" SIGIS="undef" SIGNAME="External_Ports_PMOD1_1_LS">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="PMOD1_1_LS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="255" NAME="s_dma_axis_tdata_i" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axis_mm2s_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axis_mm2s_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_dma_axis_tlast_i" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axis_mm2s_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axis_mm2s_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_dma_axis_tvalid_i" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axis_mm2s_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axis_mm2s_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_dma_axis_tready_o" SIGIS="undef" SIGNAME="axi_dma_tproc_m_axis_mm2s_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axis_mm2s_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="255" NAME="m_dma_axis_tdata_o" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axis_s2mm_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axis_s2mm_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_dma_axis_tlast_o" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axis_s2mm_tlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axis_s2mm_tlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_dma_axis_tvalid_o" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axis_s2mm_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axis_s2mm_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_dma_axis_tready_i" SIGIS="undef" SIGNAME="axi_dma_tproc_s_axis_s2mm_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axis_s2mm_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_awprot" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="s_axi_arprot" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M01_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="63" NAME="s0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_clk_cnvrt_avg_0_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_0" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_tvalid" SIGIS="undef" SIGNAME="axis_clk_cnvrt_avg_0_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_0" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="63" NAME="s1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_clk_cnvrt_avg_1_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_1" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s1_axis_tvalid" SIGIS="undef" SIGNAME="axis_clk_cnvrt_avg_1_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_1" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m0_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="s0_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m0_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="s0_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m0_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="s0_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m1_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="s1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m1_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="s1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m1_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="s1_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m2_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s2_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="s2_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m2_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s2_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="s2_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m2_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s2_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="s2_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m3_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s3_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="s3_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m3_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s3_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="s3_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m3_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_s3_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="s3_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m4_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="s0_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m4_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="s0_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m4_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s0_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="s0_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m5_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="s1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m5_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="s1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m5_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="s1_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m6_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s2_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="s2_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m6_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s2_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="s2_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m6_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s2_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="s2_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="167" NAME="m7_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s3_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="s3_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m7_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s3_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="s3_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m7_axis_tready" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_s3_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="s3_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="trig_0_o" SIGIS="undef"/>
        <PORT DIR="O" NAME="trig_1_o" SIGIS="undef"/>
        <PORT DIR="O" LEFT="7" NAME="port_0_dt_o" RIGHT="0" SIGIS="undef" SIGNAME="qick_processor_0_port_0_dt_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_vec2bit_0" PORT="din"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="port_1_dt_o" RIGHT="0" SIGIS="undef" SIGNAME="qick_processor_0_port_1_dt_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_vec2bit_1" PORT="din"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="qick_processor_0_m0_axis" NAME="m0_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m0_axis_tvalid"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m0_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m0_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m1_axis" NAME="m1_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m1_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m1_axis_tready"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m1_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m2_axis" NAME="m2_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m2_axis_tvalid"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m2_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m2_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m3_axis" NAME="m3_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m3_axis_tvalid"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m3_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m3_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m4_axis" NAME="m4_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m4_axis_tvalid"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m4_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m4_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m5_axis" NAME="m5_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m5_axis_tvalid"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m5_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m5_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m6_axis" NAME="m6_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m6_axis_tvalid"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m6_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m6_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m7_axis" NAME="m7_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m7_axis_tvalid"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m7_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m7_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="qick_processor_0_m_dma_axis_o" NAME="m_dma_axis_o" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_dma_axis_tvalid_o"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="m_dma_axis_tlast_o"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_dma_axis_tdata_o"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_dma_axis_tready_i"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_clk_cnvrt_avg_0_M_AXIS" NAME="s0_axis" TYPE="SLAVE" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="199998000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_1_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s0_axis_tvalid"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s0_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_clk_cnvrt_avg_1_M_AXIS" NAME="s1_axis" TYPE="SLAVE" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="8"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="0"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="199998000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_1_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s1_axis_tvalid"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s1_axis_tdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_dma_tproc_M_AXIS_MM2S" NAME="s_dma_axis_i" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="1"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_dma_axis_tvalid_i"/>
            <PORTMAP LOGICAL="TLAST" PHYSICAL="s_dma_axis_tlast_i"/>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_dma_axis_tdata_i"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_dma_axis_tready_o"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M01_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="8"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="s_axi_awprot"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="s_axi_arprot"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="PROC_CTRL" TYPE="TARGET" VLNV="Fermi:user:qick_qproc_control:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="start" PHYSICAL="proc_start_i"/>
            <PORTMAP LOGICAL="stop" PHYSICAL="proc_stop_i"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="5" FULLNAME="/qick_vec2bit_0" HWVERSION="1.0" INSTANCE="qick_vec2bit_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="qick_vec2bit" VLNV="FERMI:user:qick_vec2bit:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="IN_DW" VALUE="8"/>
        <PARAMETER NAME="OUT_QTY" VALUE="8"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_qick_vec2bit_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="7" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="qick_processor_0_port_0_dt_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="port_0_dt_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="dout0" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="PMOD0_0_LS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="dout1" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="PMOD0_1_LS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="dout2" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout2">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="PMOD0_2_LS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="dout3" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout3">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="PMOD0_3_LS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="dout4" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout4">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="PMOD0_4_LS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="dout5" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout5">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="PMOD0_5_LS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="dout6" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout6">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="PMOD0_6_LS"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="dout7" SIGIS="undef" SIGNAME="qick_vec2bit_0_dout7">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="PMOD0_7_LS"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="5" FULLNAME="/qick_vec2bit_1" HWVERSION="1.0" INSTANCE="qick_vec2bit_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="qick_vec2bit" VLNV="FERMI:user:qick_vec2bit:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="IN_DW" VALUE="8"/>
        <PARAMETER NAME="OUT_QTY" VALUE="4"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_qick_vec2bit_1_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="7" NAME="din" RIGHT="0" SIGIS="undef" SIGNAME="qick_processor_0_port_1_dt_o">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="port_1_dt_o"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="dout0" SIGIS="undef" SIGNAME="qick_vec2bit_1_dout0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="trigger"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="dout1" SIGIS="undef" SIGNAME="qick_vec2bit_1_dout1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="trigger"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="dout2" SIGIS="undef" SIGNAME="qick_vec2bit_1_dout2">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="trigger"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="dout3" SIGIS="undef" SIGNAME="qick_vec2bit_1_dout3">
          <CONNECTIONS>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="trigger"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="13" FULLNAME="/rst_100" HWVERSION="5.0" INSTANCE="rst_100" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_rst_100_0"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="ext_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="zynq_ultra_ps_e_0_pl_resetn0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_resetn0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aux_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="I" NAME="mb_debug_sys_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="I" NAME="dcm_locked" SIGIS="undef"/>
        <PORT DIR="O" NAME="mb_reset" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst" SIGNAME="rst_100_bus_struct_reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="sys_rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="peripheral_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst" SIGNAME="rst_100_peripheral_reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_core" PORT="reset"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="axi_resetn"/>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="axi_resetn"/>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="axi_resetn"/>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="axi_resetn"/>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="axi_resetn"/>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="axi_smc" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="m_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="m_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_0" PORT="s_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_1" PORT="s_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s0_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s0_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s0_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s0_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s0_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s0_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s0_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s0_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_aresetn"/>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_aresetn"/>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_aresetn"/>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_aresetn"/>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_aresetn"/>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="m00_axis_aresetn"/>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_aresetn"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_ARESETN"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_ARESETN"/>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_aresetn"/>
            <CONNECTION INSTANCE="qick_processor_0" PORT="ps_resetn"/>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_aresetn"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="13" FULLNAME="/rst_adc0" HWVERSION="5.0" INSTANCE="rst_adc0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_rst_adc0_0"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="256000000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_adc0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_adc0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="ext_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="zynq_ultra_ps_e_0_pl_resetn0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_resetn0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aux_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="I" NAME="mb_debug_sys_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="I" NAME="dcm_locked" SIGIS="undef"/>
        <PORT DIR="O" NAME="mb_reset" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst" SIGNAME="rst_adc0_peripheral_reset">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="reset"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst"/>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="13" FULLNAME="/rst_adc0_x2" HWVERSION="5.0" INSTANCE="rst_adc0_x2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_rst_adc0_x2_0"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="512000000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="ext_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="zynq_ultra_ps_e_0_pl_resetn0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_resetn0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aux_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="I" NAME="mb_debug_sys_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="I" NAME="dcm_locked" SIGIS="undef" SIGNAME="clk_adc0_x2_locked">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="locked"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="mb_reset" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst" SIGNAME="rst_adc0_x2_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_broadcaster_0" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_broadcaster_1" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_clock_converter_0" PORT="s_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_dwidth_converter_0" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_register_slice_0" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_register_slice_1" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="aresetn"/>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axis_aresetn"/>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="m0_axis_aresetn"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="13" FULLNAME="/rst_core" HWVERSION="5.0" INSTANCE="rst_core" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_rst_adc0_x2_1"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="199998000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="clk_core_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_core" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="ext_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="zynq_ultra_ps_e_0_pl_resetn0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_resetn0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aux_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="I" NAME="mb_debug_sys_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="I" NAME="dcm_locked" SIGIS="undef" SIGNAME="clk_core_locked">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_core" PORT="locked"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="mb_reset" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst" SIGNAME="rst_core_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="qick_processor_0" PORT="c_resetn"/>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_1" PORT="m_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_0" PORT="m_axis_aresetn"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="13" FULLNAME="/rst_dac0" HWVERSION="5.0" INSTANCE="rst_dac0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_rst_dac0_0"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="ext_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="zynq_ultra_ps_e_0_pl_resetn0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_resetn0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aux_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="I" NAME="mb_debug_sys_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="I" NAME="dcm_locked" SIGIS="undef"/>
        <PORT DIR="O" NAME="mb_reset" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst" SIGNAME="rst_dac0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="m_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="s_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="s_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="aresetn"/>
            <CONNECTION INSTANCE="qick_processor_0" PORT="t_resetn"/>
            <CONNECTION INSTANCE="sg_translator_0" PORT="aresetn"/>
            <CONNECTION INSTANCE="sg_translator_1" PORT="aresetn"/>
            <CONNECTION INSTANCE="sg_translator_2" PORT="aresetn"/>
            <CONNECTION INSTANCE="sg_translator_3" PORT="aresetn"/>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s0_axis_aresetn"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="13" FULLNAME="/rst_dac1" HWVERSION="5.0" INSTANCE="rst_dac1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_rst_dac1_0"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="ext_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="zynq_ultra_ps_e_0_pl_resetn0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_resetn0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aux_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="I" NAME="mb_debug_sys_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="I" NAME="dcm_locked" SIGIS="undef"/>
        <PORT DIR="O" NAME="mb_reset" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst" SIGNAME="rst_dac1_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="m_axis_aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="aresetn"/>
            <CONNECTION INSTANCE="sg_translator_4" PORT="aresetn"/>
            <CONNECTION INSTANCE="sg_translator_5" PORT="aresetn"/>
            <CONNECTION INSTANCE="sg_translator_6" PORT="aresetn"/>
            <CONNECTION INSTANCE="sg_translator_7" PORT="aresetn"/>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s1_axis_aresetn"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="13" FULLNAME="/rst_ddr4" HWVERSION="5.0" INSTANCE="rst_ddr4" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="proc_sys_reset" VLNV="xilinx.com:ip:proc_sys_reset:5.0">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=proc_sys_reset;v=v5_0;d=pg164-proc-sys-reset.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_FAMILY" VALUE="zynquplus"/>
        <PARAMETER NAME="C_EXT_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_AUX_RST_WIDTH" VALUE="4"/>
        <PARAMETER NAME="C_EXT_RESET_HIGH" VALUE="1"/>
        <PARAMETER NAME="C_AUX_RESET_HIGH" VALUE="0"/>
        <PARAMETER NAME="C_NUM_BUS_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_RST" VALUE="1"/>
        <PARAMETER NAME="C_NUM_INTERCONNECT_ARESETN" VALUE="1"/>
        <PARAMETER NAME="C_NUM_PERP_ARESETN" VALUE="1"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_rst_ddr4_0"/>
        <PARAMETER NAME="USE_BOARD_FLOW" VALUE="false"/>
        <PARAMETER NAME="RESET_BOARD_INTERFACE" VALUE="Custom"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="333250000" DIR="I" NAME="slowest_sync_clk" SIGIS="clk" SIGNAME="ddr4_0_c0_ddr4_ui_clk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_ui_clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="ext_reset_in" POLARITY="ACTIVE_HIGH" SIGIS="rst" SIGNAME="ddr4_0_c0_ddr4_ui_clk_sync_rst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_ui_clk_sync_rst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="aux_reset_in" POLARITY="ACTIVE_LOW" SIGIS="rst"/>
        <PORT DIR="I" NAME="mb_debug_sys_rst" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="I" NAME="dcm_locked" SIGIS="undef"/>
        <PORT DIR="O" NAME="mb_reset" POLARITY="ACTIVE_HIGH" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="bus_struct_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_reset" POLARITY="ACTIVE_HIGH" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="interconnect_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst"/>
        <PORT DIR="O" LEFT="0" NAME="peripheral_aresetn" POLARITY="ACTIVE_LOW" RIGHT="0" SIGIS="rst" SIGNAME="rst_ddr4_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="aresetn"/>
            <CONNECTION INSTANCE="axis_clock_converter_0" PORT="m_axis_aresetn"/>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_aresetn"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE COREREVISION="9" FULLNAME="/sg_translator_0" HWVERSION="1.0" INSTANCE="sg_translator_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="sg_translator" VLNV="user.org:user:sg_translator:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="OUT_TYPE" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_sg_translator_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="m0_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="m0_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="159" NAME="m_gen_v6_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_gen_v6_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_gen_v6_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s1_axis_tready"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="sg_translator_0_m_gen_v6_axis" NAME="m_gen_v6_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="NUM_READ_OUTSTANDING"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_gen_v6_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_gen_v6_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_gen_v6_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_0_m0_axis" NAME="s_tproc_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="9" FULLNAME="/sg_translator_1" HWVERSION="1.0" INSTANCE="sg_translator_1" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="sg_translator" VLNV="user.org:user:sg_translator:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="OUT_TYPE" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_sg_translator_1_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="m1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="m1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="159" NAME="m_gen_v6_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_gen_v6_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_gen_v6_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s1_axis_tready"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="sg_translator_1_m_gen_v6_axis" NAME="m_gen_v6_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="NUM_READ_OUTSTANDING"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_gen_v6_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_gen_v6_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_gen_v6_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_0_m1_axis" NAME="s_tproc_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="9" FULLNAME="/sg_translator_2" HWVERSION="1.0" INSTANCE="sg_translator_2" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="sg_translator" VLNV="user.org:user:sg_translator:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="OUT_TYPE" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_sg_translator_2_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m2_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="m2_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m2_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="m2_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="159" NAME="m_gen_v6_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_gen_v6_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_gen_v6_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s1_axis_tready"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="sg_translator_2_m_gen_v6_axis" NAME="m_gen_v6_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="NUM_READ_OUTSTANDING"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_gen_v6_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_gen_v6_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_gen_v6_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_0_m2_axis" NAME="s_tproc_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="9" FULLNAME="/sg_translator_3" HWVERSION="1.0" INSTANCE="sg_translator_3" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="sg_translator" VLNV="user.org:user:sg_translator:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="OUT_TYPE" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_sg_translator_3_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m3_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="m3_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_0_m3_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="m3_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="159" NAME="m_gen_v6_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_gen_v6_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_gen_v6_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s1_axis_tready"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="sg_translator_3_m_gen_v6_axis" NAME="m_gen_v6_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="NUM_READ_OUTSTANDING"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_gen_v6_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_gen_v6_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_gen_v6_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_0_m3_axis" NAME="s_tproc_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="9" FULLNAME="/sg_translator_4" HWVERSION="1.0" INSTANCE="sg_translator_4" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="sg_translator" VLNV="user.org:user:sg_translator:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="OUT_TYPE" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_sg_translator_4_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac1_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac1" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m0_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="m0_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m0_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="m0_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="159" NAME="m_gen_v6_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_gen_v6_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_gen_v6_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s1_axis_tready"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="sg_translator_4_m_gen_v6_axis" NAME="m_gen_v6_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="NUM_READ_OUTSTANDING"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_gen_v6_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_gen_v6_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_gen_v6_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_1_m0_axis" NAME="s_tproc_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="9" FULLNAME="/sg_translator_5" HWVERSION="1.0" INSTANCE="sg_translator_5" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="sg_translator" VLNV="user.org:user:sg_translator:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="OUT_TYPE" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_sg_translator_5_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac1_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac1" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="m1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="m1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="159" NAME="m_gen_v6_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_gen_v6_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_gen_v6_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s1_axis_tready"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="sg_translator_5_m_gen_v6_axis" NAME="m_gen_v6_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="NUM_READ_OUTSTANDING"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_gen_v6_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_gen_v6_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_gen_v6_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_1_m1_axis" NAME="s_tproc_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="9" FULLNAME="/sg_translator_6" HWVERSION="1.0" INSTANCE="sg_translator_6" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="sg_translator" VLNV="user.org:user:sg_translator:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="OUT_TYPE" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_sg_translator_6_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac1_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac1" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m2_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="m2_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m2_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="m2_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="159" NAME="m_gen_v6_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_gen_v6_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_gen_v6_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s1_axis_tready"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="sg_translator_6_m_gen_v6_axis" NAME="m_gen_v6_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="NUM_READ_OUTSTANDING"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_gen_v6_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_gen_v6_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_gen_v6_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_1_m2_axis" NAME="s_tproc_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="9" FULLNAME="/sg_translator_7" HWVERSION="1.0" INSTANCE="sg_translator_7" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="sg_translator" VLNV="user.org:user:sg_translator:1.0">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="OUT_TYPE" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_sg_translator_7_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac1_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac1" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="167" NAME="s_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m3_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="m3_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axis_tvalid" SIGIS="undef" SIGNAME="axis_cdcsync_v1_1_m3_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="m3_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axis_tready" SIGIS="undef"/>
        <PORT DIR="O" LEFT="159" NAME="m_gen_v6_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s1_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s1_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m_gen_v6_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s1_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s1_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m_gen_v6_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_s1_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s1_axis_tready"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="sg_translator_7_m_gen_v6_axis" NAME="m_gen_v6_axis" TYPE="INITIATOR" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="NUM_READ_OUTSTANDING"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING"/>
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="20"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m_gen_v6_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m_gen_v6_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m_gen_v6_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_cdcsync_v1_1_m3_axis" NAME="s_tproc_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="21"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s_axis_tdata"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s_axis_tvalid"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s_axis_tready"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="2" FULLNAME="/usp_rf_data_converter_0" HWVERSION="2.6" INSTANCE="usp_rf_data_converter_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="usp_rf_data_converter" VLNV="xilinx.com:ip:usp_rf_data_converter:2.6">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=usp_rf_data_converter;v=v2_6;d=pg269-rf-data-converter.pdf"/>
      </DOCUMENTS>
      <ADDRESSBLOCKS>
        <ADDRESSBLOCK ACCESS="read-write" INTERFACE="s_axi" NAME="Reg" RANGE="262144" USAGE=""/>
      </ADDRESSBLOCKS>
      <PARAMETERS>
        <PARAMETER NAME="C_AMS_Factory_Var" VALUE="0"/>
        <PARAMETER NAME="C_COMPONENT_NAME" VALUE="d_1_usp_rf_data_converter_0_0"/>
        <PARAMETER NAME="C_High_Speed_ADC" VALUE="1"/>
        <PARAMETER NAME="C_IP_Type" VALUE="0"/>
        <PARAMETER NAME="C_Axiclk_Freq" VALUE="100.0"/>
        <PARAMETER NAME="C_Sysref_Source" VALUE="1"/>
        <PARAMETER NAME="C_Converter_Setup" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Debug" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Debug" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Output_Current" VALUE="0"/>
        <PARAMETER NAME="C_DAC_VOP_Mode" VALUE="1"/>
        <PARAMETER NAME="C_DAC_RTS" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RTS" VALUE="false"/>
        <PARAMETER NAME="C_Analog_Detection" VALUE="1"/>
        <PARAMETER NAME="C_Calibration_Freeze" VALUE="false"/>
        <PARAMETER NAME="C_Auto_Calibration_Freeze" VALUE="false"/>
        <PARAMETER NAME="C_Calibration_Time" VALUE="10"/>
        <PARAMETER NAME="C_DAC_NCO_RTS" VALUE="false"/>
        <PARAMETER NAME="C_DAC_VOP_RTS" VALUE="false"/>
        <PARAMETER NAME="C_DAC_MTS_Variable_Fabric_Width" VALUE="false"/>
        <PARAMETER NAME="C_ADC_NCO_RTS" VALUE="false"/>
        <PARAMETER NAME="C_ADC_DSA_RTS" VALUE="false"/>
        <PARAMETER NAME="C_ADC_MTS_Variable_Fabric_Width" VALUE="false"/>
        <PARAMETER NAME="C_RESERVED_2" VALUE="false"/>
        <PARAMETER NAME="C_ADC0_Enable" VALUE="1"/>
        <PARAMETER NAME="C_ADC0_PLL_Enable" VALUE="true"/>
        <PARAMETER NAME="C_ADC0_Sampling_Rate" VALUE="4.096"/>
        <PARAMETER NAME="C_ADC0_Fs_Max" VALUE="4.096"/>
        <PARAMETER NAME="C_ADC0_Refclk_Freq" VALUE="204.800"/>
        <PARAMETER NAME="C_ADC0_Outclk_Freq" VALUE="256.000"/>
        <PARAMETER NAME="C_ADC0_FBDIV" VALUE="60"/>
        <PARAMETER NAME="C_ADC0_OutDiv" VALUE="3"/>
        <PARAMETER NAME="C_ADC0_Vco" VALUE="12288.0"/>
        <PARAMETER NAME="C_ADC0_Fabric_Freq" VALUE="512.000"/>
        <PARAMETER NAME="C_ADC0_OBS_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC0_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="C_ADC0_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="C_ADC0_Band" VALUE="0"/>
        <PARAMETER NAME="C_ADC0_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="C_ADC0_Slices" VALUE="2"/>
        <PARAMETER NAME="C_ADC0_Decimation" VALUE="1"/>
        <PARAMETER NAME="C_ADC0_Clock_Source" VALUE="0"/>
        <PARAMETER NAME="C_ADC0_Clock_Source_MX" VALUE="0"/>
        <PARAMETER NAME="C_ADC0_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Slice00_Enable" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Dither00" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type00" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode00" VALUE="1"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode00" VALUE="1"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode00" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type00" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode00" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width00" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width00" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq00" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq00" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase00" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature00" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist00" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal00" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_00" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS00" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS00" VALUE="false"/>
        <PARAMETER NAME="C_ADC00_Dig_Port" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Slice01_Enable" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Dither01" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type01" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode01" VALUE="1"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode01" VALUE="1"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode01" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type01" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode01" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width01" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width01" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq01" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq01" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase01" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature01" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist01" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal01" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_01" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS01" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS01" VALUE="false"/>
        <PARAMETER NAME="C_ADC01_Dig_Port" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Slice02_Enable" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Dither02" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type02" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode02" VALUE="1"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode02" VALUE="0"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode02" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type02" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode02" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width02" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width02" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq02" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq02" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase02" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature02" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist02" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal02" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_02" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS02" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS02" VALUE="false"/>
        <PARAMETER NAME="C_ADC02_Dig_Port" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Slice03_Enable" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Dither03" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type03" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode03" VALUE="1"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode03" VALUE="0"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode03" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type03" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode03" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width03" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width03" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq03" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq03" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase03" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature03" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist03" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal03" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_03" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS03" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS03" VALUE="false"/>
        <PARAMETER NAME="C_ADC03_Dig_Port" VALUE="0"/>
        <PARAMETER NAME="C_ADC1_Enable" VALUE="0"/>
        <PARAMETER NAME="C_ADC1_PLL_Enable" VALUE="false"/>
        <PARAMETER NAME="C_ADC1_Sampling_Rate" VALUE="2.0"/>
        <PARAMETER NAME="C_ADC1_Fs_Max" VALUE="4.096"/>
        <PARAMETER NAME="C_ADC1_Refclk_Freq" VALUE="2000.000"/>
        <PARAMETER NAME="C_ADC1_Outclk_Freq" VALUE="15.625"/>
        <PARAMETER NAME="C_ADC1_FBDIV" VALUE="10"/>
        <PARAMETER NAME="C_ADC1_OutDiv" VALUE="1"/>
        <PARAMETER NAME="C_ADC1_Vco" VALUE="8500.0"/>
        <PARAMETER NAME="C_ADC1_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC1_OBS_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC1_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="C_ADC1_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="C_ADC1_Band" VALUE="0"/>
        <PARAMETER NAME="C_ADC1_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="C_ADC1_Slices" VALUE="2"/>
        <PARAMETER NAME="C_ADC1_Decimation" VALUE="0"/>
        <PARAMETER NAME="C_ADC1_Clock_Source" VALUE="1"/>
        <PARAMETER NAME="C_ADC1_Clock_Source_MX" VALUE="1"/>
        <PARAMETER NAME="C_ADC1_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Slice10_Enable" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Dither10" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type10" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode10" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode10" VALUE="1"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode10" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type10" VALUE="3"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode10" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width10" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width10" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq10" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq10" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase10" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature10" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist10" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal10" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_10" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS10" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS10" VALUE="false"/>
        <PARAMETER NAME="C_ADC10_Dig_Port" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Slice11_Enable" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Dither11" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type11" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode11" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode11" VALUE="1"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode11" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type11" VALUE="3"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode11" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width11" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width11" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq11" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq11" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase11" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature11" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist11" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal11" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_11" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS11" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS11" VALUE="false"/>
        <PARAMETER NAME="C_ADC11_Dig_Port" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Slice12_Enable" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Dither12" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type12" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode12" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode12" VALUE="1"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode12" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type12" VALUE="3"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode12" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width12" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width12" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq12" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq12" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase12" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature12" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist12" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal12" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_12" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS12" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS12" VALUE="false"/>
        <PARAMETER NAME="C_ADC12_Dig_Port" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Slice13_Enable" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Dither13" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type13" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode13" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode13" VALUE="1"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode13" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type13" VALUE="3"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode13" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width13" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width13" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq13" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq13" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase13" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature13" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist13" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal13" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_13" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS13" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS13" VALUE="false"/>
        <PARAMETER NAME="C_ADC13_Dig_Port" VALUE="0"/>
        <PARAMETER NAME="C_ADC2_Enable" VALUE="0"/>
        <PARAMETER NAME="C_ADC2_PLL_Enable" VALUE="false"/>
        <PARAMETER NAME="C_ADC2_Sampling_Rate" VALUE="2.0"/>
        <PARAMETER NAME="C_ADC2_Fs_Max" VALUE="4.096"/>
        <PARAMETER NAME="C_ADC2_Refclk_Freq" VALUE="2000.000"/>
        <PARAMETER NAME="C_ADC2_Outclk_Freq" VALUE="15.625"/>
        <PARAMETER NAME="C_ADC2_FBDIV" VALUE="10"/>
        <PARAMETER NAME="C_ADC2_OutDiv" VALUE="1"/>
        <PARAMETER NAME="C_ADC2_Vco" VALUE="8500.0"/>
        <PARAMETER NAME="C_ADC2_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC2_OBS_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC2_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="C_ADC2_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="C_ADC2_Band" VALUE="0"/>
        <PARAMETER NAME="C_ADC2_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="C_ADC2_Slices" VALUE="2"/>
        <PARAMETER NAME="C_ADC2_Decimation" VALUE="0"/>
        <PARAMETER NAME="C_ADC2_Clock_Source" VALUE="2"/>
        <PARAMETER NAME="C_ADC2_Clock_Source_MX" VALUE="2"/>
        <PARAMETER NAME="C_ADC2_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Slice20_Enable" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Dither20" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type20" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode20" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode20" VALUE="1"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode20" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type20" VALUE="3"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode20" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width20" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width20" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq20" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq20" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase20" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature20" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist20" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal20" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_20" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS20" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS20" VALUE="false"/>
        <PARAMETER NAME="C_ADC20_Dig_Port" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Slice21_Enable" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Dither21" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type21" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode21" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode21" VALUE="1"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode21" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type21" VALUE="3"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode21" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width21" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width21" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq21" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq21" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase21" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature21" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist21" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal21" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_21" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS21" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS21" VALUE="false"/>
        <PARAMETER NAME="C_ADC21_Dig_Port" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Slice22_Enable" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Dither22" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type22" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode22" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode22" VALUE="1"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode22" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type22" VALUE="3"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode22" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width22" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width22" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq22" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq22" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase22" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature22" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist22" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal22" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_22" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS22" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS22" VALUE="false"/>
        <PARAMETER NAME="C_ADC22_Dig_Port" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Slice23_Enable" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Dither23" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type23" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode23" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode23" VALUE="1"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode23" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type23" VALUE="3"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode23" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width23" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width23" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq23" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq23" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase23" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature23" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist23" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal23" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_23" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS23" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS23" VALUE="false"/>
        <PARAMETER NAME="C_ADC23_Dig_Port" VALUE="0"/>
        <PARAMETER NAME="C_ADC3_Enable" VALUE="0"/>
        <PARAMETER NAME="C_ADC3_PLL_Enable" VALUE="false"/>
        <PARAMETER NAME="C_ADC3_Sampling_Rate" VALUE="2.0"/>
        <PARAMETER NAME="C_ADC3_Fs_Max" VALUE="4.096"/>
        <PARAMETER NAME="C_ADC3_Refclk_Freq" VALUE="2000.000"/>
        <PARAMETER NAME="C_ADC3_Outclk_Freq" VALUE="15.625"/>
        <PARAMETER NAME="C_ADC3_FBDIV" VALUE="10"/>
        <PARAMETER NAME="C_ADC3_OutDiv" VALUE="1"/>
        <PARAMETER NAME="C_ADC3_Vco" VALUE="8500.0"/>
        <PARAMETER NAME="C_ADC3_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC3_OBS_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC3_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="C_ADC3_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="C_ADC3_Band" VALUE="0"/>
        <PARAMETER NAME="C_ADC3_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="C_ADC3_Slices" VALUE="2"/>
        <PARAMETER NAME="C_ADC3_Decimation" VALUE="0"/>
        <PARAMETER NAME="C_ADC3_Clock_Source" VALUE="3"/>
        <PARAMETER NAME="C_ADC3_Clock_Source_MX" VALUE="3"/>
        <PARAMETER NAME="C_ADC3_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Slice30_Enable" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Dither30" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type30" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode30" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode30" VALUE="1"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode30" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type30" VALUE="3"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode30" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width30" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width30" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq30" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq30" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase30" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature30" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist30" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal30" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_30" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS30" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS30" VALUE="false"/>
        <PARAMETER NAME="C_ADC30_Dig_Port" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Slice31_Enable" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Dither31" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type31" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode31" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode31" VALUE="1"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode31" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type31" VALUE="3"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode31" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width31" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width31" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq31" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq31" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase31" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature31" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist31" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal31" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_31" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS31" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS31" VALUE="false"/>
        <PARAMETER NAME="C_ADC31_Dig_Port" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Slice32_Enable" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Dither32" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type32" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode32" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode32" VALUE="1"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode32" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type32" VALUE="3"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode32" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width32" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width32" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq32" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq32" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase32" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature32" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist32" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal32" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_32" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS32" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS32" VALUE="false"/>
        <PARAMETER NAME="C_ADC32_Dig_Port" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Slice33_Enable" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Dither33" VALUE="true"/>
        <PARAMETER NAME="C_ADC_Data_Type33" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Decimation_Mode33" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS_Decimation_Mode33" VALUE="1"/>
        <PARAMETER NAME="C_ADC_CalOpt_Mode33" VALUE="1"/>
        <PARAMETER NAME="C_ADC_Mixer_Type33" VALUE="3"/>
        <PARAMETER NAME="C_ADC_Mixer_Mode33" VALUE="2"/>
        <PARAMETER NAME="C_ADC_Data_Width33" VALUE="8"/>
        <PARAMETER NAME="C_ADC_OBS_Data_Width33" VALUE="8"/>
        <PARAMETER NAME="C_ADC_Coarse_Mixer_Freq33" VALUE="0"/>
        <PARAMETER NAME="C_ADC_NCO_Freq33" VALUE="0.0"/>
        <PARAMETER NAME="C_ADC_NCO_Phase33" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Neg_Quadrature33" VALUE="false"/>
        <PARAMETER NAME="C_ADC_Nyquist33" VALUE="0"/>
        <PARAMETER NAME="C_ADC_Bypass_BG_Cal33" VALUE="false"/>
        <PARAMETER NAME="C_ADC_RESERVED_1_33" VALUE="false"/>
        <PARAMETER NAME="C_ADC_TDD_RTS33" VALUE="0"/>
        <PARAMETER NAME="C_ADC_OBS33" VALUE="false"/>
        <PARAMETER NAME="C_ADC33_Dig_Port" VALUE="0"/>
        <PARAMETER NAME="C_DAC0_Enable" VALUE="1"/>
        <PARAMETER NAME="C_DAC0_PLL_Enable" VALUE="true"/>
        <PARAMETER NAME="C_DAC0_Sampling_Rate" VALUE="6.144"/>
        <PARAMETER NAME="C_DAC0_Fs_Max" VALUE="6.554"/>
        <PARAMETER NAME="C_DAC0_Refclk_Freq" VALUE="204.800"/>
        <PARAMETER NAME="C_DAC0_Outclk_Freq" VALUE="384.000"/>
        <PARAMETER NAME="C_DAC0_FBDIV" VALUE="60"/>
        <PARAMETER NAME="C_DAC0_OutDiv" VALUE="2"/>
        <PARAMETER NAME="C_DAC0_Vco" VALUE="12288.0"/>
        <PARAMETER NAME="C_DAC0_Fabric_Freq" VALUE="384.000"/>
        <PARAMETER NAME="C_DAC0_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="C_DAC0_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="C_DAC0_Band" VALUE="0"/>
        <PARAMETER NAME="C_DAC0_VOP" VALUE="20.0"/>
        <PARAMETER NAME="C_DAC0_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="C_DAC0_Slices" VALUE="4"/>
        <PARAMETER NAME="C_DAC0_Interpolation" VALUE="1"/>
        <PARAMETER NAME="C_DAC0_Clock_Source" VALUE="4"/>
        <PARAMETER NAME="C_DAC0_Clock_Source_MX" VALUE="4"/>
        <PARAMETER NAME="C_DAC0_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice00_Enable" VALUE="true"/>
        <PARAMETER NAME="C_DAC_Data_Type00" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width00" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode00" VALUE="1"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode00" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type00" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode00" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl00" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq00" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq00" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase00" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature00" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist00" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode00" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_00" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS00" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice01_Enable" VALUE="true"/>
        <PARAMETER NAME="C_DAC_Data_Type01" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width01" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode01" VALUE="1"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode01" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type01" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode01" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl01" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq01" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq01" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase01" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature01" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist01" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode01" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_01" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS01" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice02_Enable" VALUE="true"/>
        <PARAMETER NAME="C_DAC_Data_Type02" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width02" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode02" VALUE="1"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode02" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type02" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode02" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl02" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq02" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq02" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase02" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature02" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist02" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode02" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_02" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS02" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice03_Enable" VALUE="true"/>
        <PARAMETER NAME="C_DAC_Data_Type03" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width03" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode03" VALUE="1"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode03" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type03" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode03" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl03" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq03" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq03" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase03" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature03" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist03" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode03" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_03" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS03" VALUE="0"/>
        <PARAMETER NAME="C_DAC1_Enable" VALUE="1"/>
        <PARAMETER NAME="C_DAC1_PLL_Enable" VALUE="true"/>
        <PARAMETER NAME="C_DAC1_Sampling_Rate" VALUE="6.144"/>
        <PARAMETER NAME="C_DAC1_Fs_Max" VALUE="6.554"/>
        <PARAMETER NAME="C_DAC1_Refclk_Freq" VALUE="204.800"/>
        <PARAMETER NAME="C_DAC1_Outclk_Freq" VALUE="384.000"/>
        <PARAMETER NAME="C_DAC1_FBDIV" VALUE="60"/>
        <PARAMETER NAME="C_DAC1_OutDiv" VALUE="2"/>
        <PARAMETER NAME="C_DAC1_Vco" VALUE="12288.0"/>
        <PARAMETER NAME="C_DAC1_Fabric_Freq" VALUE="384.000"/>
        <PARAMETER NAME="C_DAC1_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="C_DAC1_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="C_DAC1_Band" VALUE="0"/>
        <PARAMETER NAME="C_DAC1_VOP" VALUE="20.0"/>
        <PARAMETER NAME="C_DAC1_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="C_DAC1_Slices" VALUE="4"/>
        <PARAMETER NAME="C_DAC1_Interpolation" VALUE="1"/>
        <PARAMETER NAME="C_DAC1_Clock_Source" VALUE="5"/>
        <PARAMETER NAME="C_DAC1_Clock_Source_MX" VALUE="5"/>
        <PARAMETER NAME="C_DAC1_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice10_Enable" VALUE="true"/>
        <PARAMETER NAME="C_DAC_Data_Type10" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width10" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode10" VALUE="1"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode10" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type10" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode10" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl10" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq10" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq10" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase10" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature10" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist10" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode10" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_10" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS10" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice11_Enable" VALUE="true"/>
        <PARAMETER NAME="C_DAC_Data_Type11" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width11" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode11" VALUE="1"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode11" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type11" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode11" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl11" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq11" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq11" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase11" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature11" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist11" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode11" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_11" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS11" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice12_Enable" VALUE="true"/>
        <PARAMETER NAME="C_DAC_Data_Type12" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width12" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode12" VALUE="1"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode12" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type12" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode12" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl12" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq12" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq12" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase12" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature12" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist12" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode12" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_12" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS12" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice13_Enable" VALUE="true"/>
        <PARAMETER NAME="C_DAC_Data_Type13" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width13" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode13" VALUE="1"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode13" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type13" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode13" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl13" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq13" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq13" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase13" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature13" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist13" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode13" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_13" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS13" VALUE="0"/>
        <PARAMETER NAME="C_DAC2_Enable" VALUE="0"/>
        <PARAMETER NAME="C_DAC2_PLL_Enable" VALUE="false"/>
        <PARAMETER NAME="C_DAC2_Sampling_Rate" VALUE="6.4"/>
        <PARAMETER NAME="C_DAC2_Fs_Max" VALUE="6.554"/>
        <PARAMETER NAME="C_DAC2_Refclk_Freq" VALUE="6400.000"/>
        <PARAMETER NAME="C_DAC2_Outclk_Freq" VALUE="50.000"/>
        <PARAMETER NAME="C_DAC2_FBDIV" VALUE="10"/>
        <PARAMETER NAME="C_DAC2_OutDiv" VALUE="2"/>
        <PARAMETER NAME="C_DAC2_Vco" VALUE="12800.0"/>
        <PARAMETER NAME="C_DAC2_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC2_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="C_DAC2_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="C_DAC2_Band" VALUE="0"/>
        <PARAMETER NAME="C_DAC2_VOP" VALUE="20.0"/>
        <PARAMETER NAME="C_DAC2_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="C_DAC2_Slices" VALUE="0"/>
        <PARAMETER NAME="C_DAC2_Interpolation" VALUE="0"/>
        <PARAMETER NAME="C_DAC2_Clock_Source" VALUE="6"/>
        <PARAMETER NAME="C_DAC2_Clock_Source_MX" VALUE="6"/>
        <PARAMETER NAME="C_DAC2_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice20_Enable" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Data_Type20" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width20" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode20" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode20" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type20" VALUE="3"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode20" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl20" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq20" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq20" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase20" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature20" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist20" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode20" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_20" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS20" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice21_Enable" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Data_Type21" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width21" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode21" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode21" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type21" VALUE="3"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode21" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl21" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq21" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq21" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase21" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature21" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist21" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode21" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_21" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS21" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice22_Enable" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Data_Type22" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width22" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode22" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode22" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type22" VALUE="3"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode22" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl22" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq22" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq22" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase22" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature22" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist22" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode22" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_22" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS22" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice23_Enable" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Data_Type23" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width23" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode23" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode23" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type23" VALUE="3"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode23" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl23" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq23" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq23" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase23" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature23" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist23" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode23" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_23" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS23" VALUE="0"/>
        <PARAMETER NAME="C_DAC3_Enable" VALUE="0"/>
        <PARAMETER NAME="C_DAC3_PLL_Enable" VALUE="false"/>
        <PARAMETER NAME="C_DAC3_Sampling_Rate" VALUE="6.4"/>
        <PARAMETER NAME="C_DAC3_Fs_Max" VALUE="6.554"/>
        <PARAMETER NAME="C_DAC3_Refclk_Freq" VALUE="6400.000"/>
        <PARAMETER NAME="C_DAC3_Outclk_Freq" VALUE="50.000"/>
        <PARAMETER NAME="C_DAC3_FBDIV" VALUE="10"/>
        <PARAMETER NAME="C_DAC3_OutDiv" VALUE="2"/>
        <PARAMETER NAME="C_DAC3_Vco" VALUE="12800.0"/>
        <PARAMETER NAME="C_DAC3_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC3_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="C_DAC3_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="C_DAC3_Band" VALUE="0"/>
        <PARAMETER NAME="C_DAC3_VOP" VALUE="20.0"/>
        <PARAMETER NAME="C_DAC3_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="C_DAC3_Slices" VALUE="0"/>
        <PARAMETER NAME="C_DAC3_Interpolation" VALUE="0"/>
        <PARAMETER NAME="C_DAC3_Clock_Source" VALUE="7"/>
        <PARAMETER NAME="C_DAC3_Clock_Source_MX" VALUE="7"/>
        <PARAMETER NAME="C_DAC3_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice30_Enable" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Data_Type30" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width30" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode30" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode30" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type30" VALUE="3"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode30" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl30" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq30" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq30" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase30" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature30" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist30" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode30" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_30" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS30" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice31_Enable" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Data_Type31" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width31" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode31" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode31" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type31" VALUE="3"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode31" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl31" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq31" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq31" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase31" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature31" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist31" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode31" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_31" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS31" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice32_Enable" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Data_Type32" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width32" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode32" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode32" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type32" VALUE="3"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode32" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl32" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq32" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq32" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase32" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature32" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist32" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode32" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_32" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS32" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Slice33_Enable" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Data_Type33" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Data_Width33" VALUE="16"/>
        <PARAMETER NAME="C_DAC_Interpolation_Mode33" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Decoder_Mode33" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mixer_Type33" VALUE="3"/>
        <PARAMETER NAME="C_DAC_Mixer_Mode33" VALUE="2"/>
        <PARAMETER NAME="C_DAC_Invsinc_Ctrl33" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Coarse_Mixer_Freq33" VALUE="0"/>
        <PARAMETER NAME="C_DAC_NCO_Freq33" VALUE="0.0"/>
        <PARAMETER NAME="C_DAC_NCO_Phase33" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Neg_Quadrature33" VALUE="false"/>
        <PARAMETER NAME="C_DAC_Nyquist33" VALUE="0"/>
        <PARAMETER NAME="C_DAC_Mode33" VALUE="0"/>
        <PARAMETER NAME="C_DAC_RESERVED_1_33" VALUE="false"/>
        <PARAMETER NAME="C_DAC_TDD_RTS33" VALUE="0"/>
        <PARAMETER NAME="C_Clock_Forwarding" VALUE="false"/>
        <PARAMETER NAME="production_simulation" VALUE="0"/>
        <PARAMETER NAME="disable_bg_cal_en" VALUE="1"/>
        <PARAMETER NAME="C_VNC_Testing" VALUE="false"/>
        <PARAMETER NAME="C_RESERVED_3" VALUE="110000"/>
        <PARAMETER NAME="C_VNC_Include_OIS_Change" VALUE="false"/>
        <PARAMETER NAME="C_VNC_Include_Fs2_Change" VALUE="false"/>
        <PARAMETER NAME="C_RF_Analyzer" VALUE="0"/>
        <PARAMETER NAME="C_PL_Clock_Freq" VALUE="100.0"/>
        <PARAMETER NAME="tb_dac_fft" VALUE="true"/>
        <PARAMETER NAME="tb_adc_fft" VALUE="true"/>
        <PARAMETER NAME="use_bram" VALUE="1"/>
        <PARAMETER NAME="C_Silicon_Revision" VALUE="1"/>
        <PARAMETER NAME="AMS_Factory_Var" VALUE="0"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_usp_rf_data_converter_0_0"/>
        <PARAMETER NAME="Axiclk_Freq" VALUE="100.0"/>
        <PARAMETER NAME="Sysref_Source" VALUE="1"/>
        <PARAMETER NAME="PRESET" VALUE="None"/>
        <PARAMETER NAME="Converter_Setup" VALUE="1"/>
        <PARAMETER NAME="ADC224_En" VALUE="false"/>
        <PARAMETER NAME="ADC225_En" VALUE="false"/>
        <PARAMETER NAME="ADC226_En" VALUE="false"/>
        <PARAMETER NAME="ADC227_En" VALUE="false"/>
        <PARAMETER NAME="DAC228_En" VALUE="false"/>
        <PARAMETER NAME="DAC229_En" VALUE="false"/>
        <PARAMETER NAME="DAC230_En" VALUE="false"/>
        <PARAMETER NAME="DAC231_En" VALUE="false"/>
        <PARAMETER NAME="ADC_Debug" VALUE="false"/>
        <PARAMETER NAME="DAC_Debug" VALUE="false"/>
        <PARAMETER NAME="DAC_Output_Current" VALUE="0"/>
        <PARAMETER NAME="DAC_VOP_Mode" VALUE="1"/>
        <PARAMETER NAME="ADC_RTS" VALUE="false"/>
        <PARAMETER NAME="DAC_RTS" VALUE="false"/>
        <PARAMETER NAME="Analog_Detection" VALUE="1"/>
        <PARAMETER NAME="Calibration_Freeze" VALUE="false"/>
        <PARAMETER NAME="Auto_Calibration_Freeze" VALUE="false"/>
        <PARAMETER NAME="Calibration_Time" VALUE="10"/>
        <PARAMETER NAME="DAC_NCO_RTS" VALUE="false"/>
        <PARAMETER NAME="DAC_VOP_RTS" VALUE="false"/>
        <PARAMETER NAME="DAC_MTS_Variable_Fabric_Width" VALUE="false"/>
        <PARAMETER NAME="ADC_NCO_RTS" VALUE="false"/>
        <PARAMETER NAME="ADC_DSA_RTS" VALUE="false"/>
        <PARAMETER NAME="ADC_MTS_Variable_Fabric_Width" VALUE="false"/>
        <PARAMETER NAME="ADC0_Enable" VALUE="1"/>
        <PARAMETER NAME="ADC0_PLL_Enable" VALUE="true"/>
        <PARAMETER NAME="ADC0_Sampling_Rate" VALUE="4.096"/>
        <PARAMETER NAME="ADC0_Refclk_Freq" VALUE="204.800"/>
        <PARAMETER NAME="ADC0_Outclk_Freq" VALUE="256.000"/>
        <PARAMETER NAME="ADC0_Fabric_Freq" VALUE="512.000"/>
        <PARAMETER NAME="ADC0_OBS_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="ADC0_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="ADC0_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="ADC0_Band" VALUE="0"/>
        <PARAMETER NAME="ADC0_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="ADC0_Clock_Source" VALUE="0"/>
        <PARAMETER NAME="ADC0_Clock_Source_MX" VALUE="0"/>
        <PARAMETER NAME="ADC0_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="ADC_Slice00_Enable" VALUE="true"/>
        <PARAMETER NAME="ADC_Dither00" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type00" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode00" VALUE="1"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode00" VALUE="1"/>
        <PARAMETER NAME="ADC_CalOpt_Mode00" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type00" VALUE="0"/>
        <PARAMETER NAME="ADC_Mixer_Mode00" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width00" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width00" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq00" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq00" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase00" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature00" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist00" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal00" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_00" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS00" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS00" VALUE="false"/>
        <PARAMETER NAME="ADC_Slice01_Enable" VALUE="true"/>
        <PARAMETER NAME="ADC_Dither01" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type01" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode01" VALUE="1"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode01" VALUE="1"/>
        <PARAMETER NAME="ADC_CalOpt_Mode01" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type01" VALUE="0"/>
        <PARAMETER NAME="ADC_Mixer_Mode01" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width01" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width01" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq01" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq01" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase01" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature01" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist01" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal01" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_01" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS01" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS01" VALUE="false"/>
        <PARAMETER NAME="ADC_Slice02_Enable" VALUE="true"/>
        <PARAMETER NAME="ADC_Dither02" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type02" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode02" VALUE="1"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode02" VALUE="0"/>
        <PARAMETER NAME="ADC_CalOpt_Mode02" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type02" VALUE="0"/>
        <PARAMETER NAME="ADC_Mixer_Mode02" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width02" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width02" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq02" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq02" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase02" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature02" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist02" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal02" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_02" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS02" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS02" VALUE="false"/>
        <PARAMETER NAME="ADC_Slice03_Enable" VALUE="true"/>
        <PARAMETER NAME="ADC_Dither03" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type03" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode03" VALUE="1"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode03" VALUE="0"/>
        <PARAMETER NAME="ADC_CalOpt_Mode03" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type03" VALUE="0"/>
        <PARAMETER NAME="ADC_Mixer_Mode03" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width03" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width03" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq03" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq03" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase03" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature03" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist03" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal03" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_03" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS03" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS03" VALUE="false"/>
        <PARAMETER NAME="ADC1_Enable" VALUE="0"/>
        <PARAMETER NAME="ADC1_PLL_Enable" VALUE="false"/>
        <PARAMETER NAME="ADC1_Sampling_Rate" VALUE="2.0"/>
        <PARAMETER NAME="ADC1_Refclk_Freq" VALUE="2000.000"/>
        <PARAMETER NAME="ADC1_Outclk_Freq" VALUE="15.625"/>
        <PARAMETER NAME="ADC1_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="ADC1_OBS_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="ADC1_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="ADC1_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="ADC1_Band" VALUE="0"/>
        <PARAMETER NAME="ADC1_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="ADC1_Clock_Source" VALUE="1"/>
        <PARAMETER NAME="ADC1_Clock_Source_MX" VALUE="1"/>
        <PARAMETER NAME="ADC1_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="ADC_Slice10_Enable" VALUE="false"/>
        <PARAMETER NAME="ADC_Dither10" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type10" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode10" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode10" VALUE="1"/>
        <PARAMETER NAME="ADC_CalOpt_Mode10" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type10" VALUE="3"/>
        <PARAMETER NAME="ADC_Mixer_Mode10" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width10" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width10" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq10" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq10" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase10" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature10" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist10" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal10" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_10" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS10" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS10" VALUE="false"/>
        <PARAMETER NAME="ADC_Slice11_Enable" VALUE="false"/>
        <PARAMETER NAME="ADC_Dither11" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type11" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode11" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode11" VALUE="1"/>
        <PARAMETER NAME="ADC_CalOpt_Mode11" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type11" VALUE="3"/>
        <PARAMETER NAME="ADC_Mixer_Mode11" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width11" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width11" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq11" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq11" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase11" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature11" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist11" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal11" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_11" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS11" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS11" VALUE="false"/>
        <PARAMETER NAME="ADC_Slice12_Enable" VALUE="false"/>
        <PARAMETER NAME="ADC_Dither12" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type12" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode12" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode12" VALUE="1"/>
        <PARAMETER NAME="ADC_CalOpt_Mode12" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type12" VALUE="3"/>
        <PARAMETER NAME="ADC_Mixer_Mode12" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width12" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width12" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq12" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq12" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase12" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature12" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist12" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal12" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_12" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS12" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS12" VALUE="false"/>
        <PARAMETER NAME="ADC_Slice13_Enable" VALUE="false"/>
        <PARAMETER NAME="ADC_Dither13" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type13" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode13" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode13" VALUE="1"/>
        <PARAMETER NAME="ADC_CalOpt_Mode13" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type13" VALUE="3"/>
        <PARAMETER NAME="ADC_Mixer_Mode13" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width13" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width13" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq13" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq13" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase13" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature13" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist13" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal13" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_13" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS13" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS13" VALUE="false"/>
        <PARAMETER NAME="ADC2_Enable" VALUE="0"/>
        <PARAMETER NAME="ADC2_PLL_Enable" VALUE="false"/>
        <PARAMETER NAME="ADC2_Sampling_Rate" VALUE="2.0"/>
        <PARAMETER NAME="ADC2_Refclk_Freq" VALUE="2000.000"/>
        <PARAMETER NAME="ADC2_Outclk_Freq" VALUE="15.625"/>
        <PARAMETER NAME="ADC2_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="ADC2_OBS_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="ADC2_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="ADC2_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="ADC2_Band" VALUE="0"/>
        <PARAMETER NAME="ADC2_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="ADC2_Clock_Source" VALUE="2"/>
        <PARAMETER NAME="ADC2_Clock_Source_MX" VALUE="2"/>
        <PARAMETER NAME="ADC2_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="ADC_Slice20_Enable" VALUE="false"/>
        <PARAMETER NAME="ADC_Dither20" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type20" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode20" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode20" VALUE="1"/>
        <PARAMETER NAME="ADC_CalOpt_Mode20" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type20" VALUE="3"/>
        <PARAMETER NAME="ADC_Mixer_Mode20" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width20" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width20" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq20" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq20" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase20" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature20" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist20" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal20" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_20" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS20" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS20" VALUE="false"/>
        <PARAMETER NAME="ADC_Slice21_Enable" VALUE="false"/>
        <PARAMETER NAME="ADC_Dither21" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type21" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode21" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode21" VALUE="1"/>
        <PARAMETER NAME="ADC_CalOpt_Mode21" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type21" VALUE="3"/>
        <PARAMETER NAME="ADC_Mixer_Mode21" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width21" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width21" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq21" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq21" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase21" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature21" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist21" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal21" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_21" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS21" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS21" VALUE="false"/>
        <PARAMETER NAME="ADC_Slice22_Enable" VALUE="false"/>
        <PARAMETER NAME="ADC_Dither22" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type22" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode22" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode22" VALUE="1"/>
        <PARAMETER NAME="ADC_CalOpt_Mode22" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type22" VALUE="3"/>
        <PARAMETER NAME="ADC_Mixer_Mode22" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width22" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width22" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq22" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq22" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase22" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature22" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist22" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal22" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_22" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS22" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS22" VALUE="false"/>
        <PARAMETER NAME="ADC_Slice23_Enable" VALUE="false"/>
        <PARAMETER NAME="ADC_Dither23" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type23" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode23" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode23" VALUE="1"/>
        <PARAMETER NAME="ADC_CalOpt_Mode23" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type23" VALUE="3"/>
        <PARAMETER NAME="ADC_Mixer_Mode23" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width23" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width23" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq23" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq23" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase23" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature23" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist23" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal23" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_23" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS23" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS23" VALUE="false"/>
        <PARAMETER NAME="ADC3_Enable" VALUE="0"/>
        <PARAMETER NAME="ADC3_PLL_Enable" VALUE="false"/>
        <PARAMETER NAME="ADC3_Sampling_Rate" VALUE="2.0"/>
        <PARAMETER NAME="ADC3_Refclk_Freq" VALUE="2000.000"/>
        <PARAMETER NAME="ADC3_Outclk_Freq" VALUE="15.625"/>
        <PARAMETER NAME="ADC3_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="ADC3_OBS_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="ADC3_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="ADC3_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="ADC3_Band" VALUE="0"/>
        <PARAMETER NAME="ADC3_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="ADC3_Clock_Source" VALUE="3"/>
        <PARAMETER NAME="ADC3_Clock_Source_MX" VALUE="3"/>
        <PARAMETER NAME="ADC3_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="ADC_Slice30_Enable" VALUE="false"/>
        <PARAMETER NAME="ADC_Dither30" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type30" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode30" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode30" VALUE="1"/>
        <PARAMETER NAME="ADC_CalOpt_Mode30" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type30" VALUE="3"/>
        <PARAMETER NAME="ADC_Mixer_Mode30" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width30" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width30" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq30" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq30" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase30" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature30" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist30" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal30" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_30" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS30" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS30" VALUE="false"/>
        <PARAMETER NAME="ADC_Slice31_Enable" VALUE="false"/>
        <PARAMETER NAME="ADC_Dither31" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type31" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode31" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode31" VALUE="1"/>
        <PARAMETER NAME="ADC_CalOpt_Mode31" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type31" VALUE="3"/>
        <PARAMETER NAME="ADC_Mixer_Mode31" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width31" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width31" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq31" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq31" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase31" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature31" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist31" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal31" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_31" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS31" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS31" VALUE="false"/>
        <PARAMETER NAME="ADC_Slice32_Enable" VALUE="false"/>
        <PARAMETER NAME="ADC_Dither32" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type32" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode32" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode32" VALUE="1"/>
        <PARAMETER NAME="ADC_CalOpt_Mode32" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type32" VALUE="3"/>
        <PARAMETER NAME="ADC_Mixer_Mode32" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width32" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width32" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq32" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq32" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase32" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature32" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist32" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal32" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_32" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS32" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS32" VALUE="false"/>
        <PARAMETER NAME="ADC_Slice33_Enable" VALUE="false"/>
        <PARAMETER NAME="ADC_Dither33" VALUE="true"/>
        <PARAMETER NAME="ADC_Data_Type33" VALUE="0"/>
        <PARAMETER NAME="ADC_Decimation_Mode33" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS_Decimation_Mode33" VALUE="1"/>
        <PARAMETER NAME="ADC_CalOpt_Mode33" VALUE="1"/>
        <PARAMETER NAME="ADC_Mixer_Type33" VALUE="3"/>
        <PARAMETER NAME="ADC_Mixer_Mode33" VALUE="2"/>
        <PARAMETER NAME="ADC_Data_Width33" VALUE="8"/>
        <PARAMETER NAME="ADC_OBS_Data_Width33" VALUE="8"/>
        <PARAMETER NAME="ADC_Coarse_Mixer_Freq33" VALUE="0"/>
        <PARAMETER NAME="ADC_NCO_Freq33" VALUE="0.0"/>
        <PARAMETER NAME="ADC_NCO_Phase33" VALUE="0"/>
        <PARAMETER NAME="ADC_Neg_Quadrature33" VALUE="false"/>
        <PARAMETER NAME="ADC_Nyquist33" VALUE="0"/>
        <PARAMETER NAME="ADC_Bypass_BG_Cal33" VALUE="false"/>
        <PARAMETER NAME="ADC_RESERVED_1_33" VALUE="false"/>
        <PARAMETER NAME="ADC_TDD_RTS33" VALUE="0"/>
        <PARAMETER NAME="ADC_OBS33" VALUE="false"/>
        <PARAMETER NAME="mADC_Enable" VALUE="0"/>
        <PARAMETER NAME="mADC_PLL_Enable" VALUE="false"/>
        <PARAMETER NAME="mADC_Sampling_Rate" VALUE="2.0"/>
        <PARAMETER NAME="mADC_Refclk_Freq" VALUE="2000.000"/>
        <PARAMETER NAME="mADC_Outclk_Freq" VALUE="15.625"/>
        <PARAMETER NAME="mADC_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="mADC_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="mADC_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="mADC_Band" VALUE="0"/>
        <PARAMETER NAME="mADC_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="mADC_Slice00_Enable" VALUE="false"/>
        <PARAMETER NAME="mADC_Dither00" VALUE="true"/>
        <PARAMETER NAME="mADC_Data_Type00" VALUE="0"/>
        <PARAMETER NAME="mADC_Decimation_Mode00" VALUE="0"/>
        <PARAMETER NAME="mADC_CalOpt_Mode00" VALUE="1"/>
        <PARAMETER NAME="mADC_Mixer_Type00" VALUE="3"/>
        <PARAMETER NAME="mADC_Mixer_Mode00" VALUE="2"/>
        <PARAMETER NAME="mADC_Data_Width00" VALUE="8"/>
        <PARAMETER NAME="mADC_Coarse_Mixer_Freq00" VALUE="0"/>
        <PARAMETER NAME="mADC_NCO_Freq00" VALUE="0.0"/>
        <PARAMETER NAME="mADC_NCO_Phase00" VALUE="0"/>
        <PARAMETER NAME="mADC_Neg_Quadrature00" VALUE="false"/>
        <PARAMETER NAME="mADC_Nyquist00" VALUE="0"/>
        <PARAMETER NAME="mADC_Bypass_BG_Cal00" VALUE="false"/>
        <PARAMETER NAME="mADC_RESERVED_1_00" VALUE="false"/>
        <PARAMETER NAME="mADC_TDD_RTS00" VALUE="0"/>
        <PARAMETER NAME="mADC_OBS00" VALUE="false"/>
        <PARAMETER NAME="mADC_Slice01_Enable" VALUE="false"/>
        <PARAMETER NAME="mADC_Dither01" VALUE="true"/>
        <PARAMETER NAME="mADC_Data_Type01" VALUE="0"/>
        <PARAMETER NAME="mADC_Decimation_Mode01" VALUE="0"/>
        <PARAMETER NAME="mADC_CalOpt_Mode01" VALUE="1"/>
        <PARAMETER NAME="mADC_Mixer_Type01" VALUE="3"/>
        <PARAMETER NAME="mADC_Mixer_Mode01" VALUE="2"/>
        <PARAMETER NAME="mADC_Data_Width01" VALUE="8"/>
        <PARAMETER NAME="mADC_Coarse_Mixer_Freq01" VALUE="0"/>
        <PARAMETER NAME="mADC_NCO_Freq01" VALUE="0.0"/>
        <PARAMETER NAME="mADC_NCO_Phase01" VALUE="0"/>
        <PARAMETER NAME="mADC_Neg_Quadrature01" VALUE="false"/>
        <PARAMETER NAME="mADC_Nyquist01" VALUE="0"/>
        <PARAMETER NAME="mADC_Bypass_BG_Cal01" VALUE="false"/>
        <PARAMETER NAME="mADC_RESERVED_1_01" VALUE="false"/>
        <PARAMETER NAME="mADC_TDD_RTS01" VALUE="0"/>
        <PARAMETER NAME="mADC_OBS01" VALUE="false"/>
        <PARAMETER NAME="mADC_Slice02_Enable" VALUE="false"/>
        <PARAMETER NAME="mADC_Dither02" VALUE="true"/>
        <PARAMETER NAME="mADC_Data_Type02" VALUE="0"/>
        <PARAMETER NAME="mADC_Decimation_Mode02" VALUE="0"/>
        <PARAMETER NAME="mADC_CalOpt_Mode02" VALUE="1"/>
        <PARAMETER NAME="mADC_Mixer_Type02" VALUE="3"/>
        <PARAMETER NAME="mADC_Mixer_Mode02" VALUE="2"/>
        <PARAMETER NAME="mADC_Data_Width02" VALUE="8"/>
        <PARAMETER NAME="mADC_Coarse_Mixer_Freq02" VALUE="0"/>
        <PARAMETER NAME="mADC_NCO_Freq02" VALUE="0.0"/>
        <PARAMETER NAME="mADC_NCO_Phase02" VALUE="0"/>
        <PARAMETER NAME="mADC_Neg_Quadrature02" VALUE="false"/>
        <PARAMETER NAME="mADC_Nyquist02" VALUE="0"/>
        <PARAMETER NAME="mADC_Bypass_BG_Cal02" VALUE="false"/>
        <PARAMETER NAME="mADC_RESERVED_1_02" VALUE="false"/>
        <PARAMETER NAME="mADC_TDD_RTS02" VALUE="0"/>
        <PARAMETER NAME="mADC_OBS02" VALUE="false"/>
        <PARAMETER NAME="mADC_Slice03_Enable" VALUE="false"/>
        <PARAMETER NAME="mADC_Dither03" VALUE="true"/>
        <PARAMETER NAME="mADC_Data_Type03" VALUE="0"/>
        <PARAMETER NAME="mADC_Decimation_Mode03" VALUE="0"/>
        <PARAMETER NAME="mADC_CalOpt_Mode03" VALUE="1"/>
        <PARAMETER NAME="mADC_Mixer_Type03" VALUE="3"/>
        <PARAMETER NAME="mADC_Mixer_Mode03" VALUE="2"/>
        <PARAMETER NAME="mADC_Data_Width03" VALUE="8"/>
        <PARAMETER NAME="mADC_Coarse_Mixer_Freq03" VALUE="0"/>
        <PARAMETER NAME="mADC_NCO_Freq03" VALUE="0.0"/>
        <PARAMETER NAME="mADC_NCO_Phase03" VALUE="0"/>
        <PARAMETER NAME="mADC_Neg_Quadrature03" VALUE="false"/>
        <PARAMETER NAME="mADC_Nyquist03" VALUE="0"/>
        <PARAMETER NAME="mADC_Bypass_BG_Cal03" VALUE="false"/>
        <PARAMETER NAME="mADC_RESERVED_1_03" VALUE="false"/>
        <PARAMETER NAME="mADC_TDD_RTS03" VALUE="0"/>
        <PARAMETER NAME="mADC_OBS03" VALUE="false"/>
        <PARAMETER NAME="DAC0_Enable" VALUE="1"/>
        <PARAMETER NAME="DAC0_PLL_Enable" VALUE="true"/>
        <PARAMETER NAME="DAC0_Sampling_Rate" VALUE="6.144"/>
        <PARAMETER NAME="DAC0_Refclk_Freq" VALUE="204.800"/>
        <PARAMETER NAME="DAC0_Outclk_Freq" VALUE="384.000"/>
        <PARAMETER NAME="DAC0_Fabric_Freq" VALUE="384.000"/>
        <PARAMETER NAME="DAC0_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="DAC0_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="DAC0_Band" VALUE="0"/>
        <PARAMETER NAME="DAC0_VOP" VALUE="20.0"/>
        <PARAMETER NAME="DAC0_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="DAC0_Clock_Source" VALUE="4"/>
        <PARAMETER NAME="DAC0_Clock_Source_MX" VALUE="4"/>
        <PARAMETER NAME="DAC0_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice00_Enable" VALUE="true"/>
        <PARAMETER NAME="DAC_Data_Type00" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width00" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode00" VALUE="1"/>
        <PARAMETER NAME="DAC_Decoder_Mode00" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type00" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Mode00" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl00" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq00" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq00" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase00" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature00" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist00" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode00" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_00" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS00" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice01_Enable" VALUE="true"/>
        <PARAMETER NAME="DAC_Data_Type01" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width01" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode01" VALUE="1"/>
        <PARAMETER NAME="DAC_Decoder_Mode01" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type01" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Mode01" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl01" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq01" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq01" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase01" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature01" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist01" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode01" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_01" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS01" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice02_Enable" VALUE="true"/>
        <PARAMETER NAME="DAC_Data_Type02" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width02" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode02" VALUE="1"/>
        <PARAMETER NAME="DAC_Decoder_Mode02" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type02" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Mode02" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl02" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq02" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq02" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase02" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature02" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist02" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode02" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_02" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS02" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice03_Enable" VALUE="true"/>
        <PARAMETER NAME="DAC_Data_Type03" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width03" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode03" VALUE="1"/>
        <PARAMETER NAME="DAC_Decoder_Mode03" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type03" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Mode03" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl03" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq03" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq03" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase03" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature03" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist03" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode03" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_03" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS03" VALUE="0"/>
        <PARAMETER NAME="DAC1_Enable" VALUE="1"/>
        <PARAMETER NAME="DAC1_PLL_Enable" VALUE="true"/>
        <PARAMETER NAME="DAC1_Sampling_Rate" VALUE="6.144"/>
        <PARAMETER NAME="DAC1_Refclk_Freq" VALUE="204.800"/>
        <PARAMETER NAME="DAC1_Outclk_Freq" VALUE="384.000"/>
        <PARAMETER NAME="DAC1_Fabric_Freq" VALUE="384.000"/>
        <PARAMETER NAME="DAC1_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="DAC1_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="DAC1_Band" VALUE="0"/>
        <PARAMETER NAME="DAC1_VOP" VALUE="20.0"/>
        <PARAMETER NAME="DAC1_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="DAC1_Clock_Source" VALUE="5"/>
        <PARAMETER NAME="DAC1_Clock_Source_MX" VALUE="5"/>
        <PARAMETER NAME="DAC1_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice10_Enable" VALUE="true"/>
        <PARAMETER NAME="DAC_Data_Type10" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width10" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode10" VALUE="1"/>
        <PARAMETER NAME="DAC_Decoder_Mode10" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type10" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Mode10" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl10" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq10" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq10" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase10" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature10" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist10" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode10" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_10" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS10" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice11_Enable" VALUE="true"/>
        <PARAMETER NAME="DAC_Data_Type11" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width11" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode11" VALUE="1"/>
        <PARAMETER NAME="DAC_Decoder_Mode11" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type11" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Mode11" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl11" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq11" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq11" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase11" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature11" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist11" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode11" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_11" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS11" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice12_Enable" VALUE="true"/>
        <PARAMETER NAME="DAC_Data_Type12" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width12" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode12" VALUE="1"/>
        <PARAMETER NAME="DAC_Decoder_Mode12" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type12" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Mode12" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl12" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq12" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq12" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase12" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature12" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist12" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode12" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_12" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS12" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice13_Enable" VALUE="true"/>
        <PARAMETER NAME="DAC_Data_Type13" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width13" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode13" VALUE="1"/>
        <PARAMETER NAME="DAC_Decoder_Mode13" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type13" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Mode13" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl13" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq13" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq13" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase13" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature13" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist13" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode13" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_13" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS13" VALUE="0"/>
        <PARAMETER NAME="DAC2_Enable" VALUE="0"/>
        <PARAMETER NAME="DAC2_PLL_Enable" VALUE="false"/>
        <PARAMETER NAME="DAC2_Sampling_Rate" VALUE="6.4"/>
        <PARAMETER NAME="DAC2_Refclk_Freq" VALUE="6400.000"/>
        <PARAMETER NAME="DAC2_Outclk_Freq" VALUE="50.000"/>
        <PARAMETER NAME="DAC2_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="DAC2_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="DAC2_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="DAC2_Band" VALUE="0"/>
        <PARAMETER NAME="DAC2_VOP" VALUE="20.0"/>
        <PARAMETER NAME="DAC2_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="DAC2_Clock_Source" VALUE="6"/>
        <PARAMETER NAME="DAC2_Clock_Source_MX" VALUE="6"/>
        <PARAMETER NAME="DAC2_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice20_Enable" VALUE="false"/>
        <PARAMETER NAME="DAC_Data_Type20" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width20" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode20" VALUE="0"/>
        <PARAMETER NAME="DAC_Decoder_Mode20" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type20" VALUE="3"/>
        <PARAMETER NAME="DAC_Mixer_Mode20" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl20" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq20" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq20" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase20" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature20" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist20" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode20" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_20" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS20" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice21_Enable" VALUE="false"/>
        <PARAMETER NAME="DAC_Data_Type21" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width21" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode21" VALUE="0"/>
        <PARAMETER NAME="DAC_Decoder_Mode21" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type21" VALUE="3"/>
        <PARAMETER NAME="DAC_Mixer_Mode21" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl21" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq21" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq21" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase21" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature21" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist21" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode21" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_21" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS21" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice22_Enable" VALUE="false"/>
        <PARAMETER NAME="DAC_Data_Type22" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width22" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode22" VALUE="0"/>
        <PARAMETER NAME="DAC_Decoder_Mode22" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type22" VALUE="3"/>
        <PARAMETER NAME="DAC_Mixer_Mode22" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl22" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq22" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq22" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase22" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature22" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist22" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode22" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_22" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS22" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice23_Enable" VALUE="false"/>
        <PARAMETER NAME="DAC_Data_Type23" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width23" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode23" VALUE="0"/>
        <PARAMETER NAME="DAC_Decoder_Mode23" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type23" VALUE="3"/>
        <PARAMETER NAME="DAC_Mixer_Mode23" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl23" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq23" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq23" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase23" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature23" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist23" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode23" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_23" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS23" VALUE="0"/>
        <PARAMETER NAME="DAC3_Enable" VALUE="0"/>
        <PARAMETER NAME="DAC3_PLL_Enable" VALUE="false"/>
        <PARAMETER NAME="DAC3_Sampling_Rate" VALUE="6.4"/>
        <PARAMETER NAME="DAC3_Refclk_Freq" VALUE="6400.000"/>
        <PARAMETER NAME="DAC3_Outclk_Freq" VALUE="50.000"/>
        <PARAMETER NAME="DAC3_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="DAC3_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="DAC3_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="DAC3_Band" VALUE="0"/>
        <PARAMETER NAME="DAC3_VOP" VALUE="20.0"/>
        <PARAMETER NAME="DAC3_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="DAC3_Clock_Source" VALUE="7"/>
        <PARAMETER NAME="DAC3_Clock_Source_MX" VALUE="7"/>
        <PARAMETER NAME="DAC3_Clock_Dist" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice30_Enable" VALUE="false"/>
        <PARAMETER NAME="DAC_Data_Type30" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width30" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode30" VALUE="0"/>
        <PARAMETER NAME="DAC_Decoder_Mode30" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type30" VALUE="3"/>
        <PARAMETER NAME="DAC_Mixer_Mode30" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl30" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq30" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq30" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase30" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature30" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist30" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode30" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_30" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS30" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice31_Enable" VALUE="false"/>
        <PARAMETER NAME="DAC_Data_Type31" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width31" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode31" VALUE="0"/>
        <PARAMETER NAME="DAC_Decoder_Mode31" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type31" VALUE="3"/>
        <PARAMETER NAME="DAC_Mixer_Mode31" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl31" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq31" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq31" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase31" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature31" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist31" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode31" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_31" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS31" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice32_Enable" VALUE="false"/>
        <PARAMETER NAME="DAC_Data_Type32" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width32" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode32" VALUE="0"/>
        <PARAMETER NAME="DAC_Decoder_Mode32" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type32" VALUE="3"/>
        <PARAMETER NAME="DAC_Mixer_Mode32" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl32" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq32" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq32" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase32" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature32" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist32" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode32" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_32" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS32" VALUE="0"/>
        <PARAMETER NAME="DAC_Slice33_Enable" VALUE="false"/>
        <PARAMETER NAME="DAC_Data_Type33" VALUE="0"/>
        <PARAMETER NAME="DAC_Data_Width33" VALUE="16"/>
        <PARAMETER NAME="DAC_Interpolation_Mode33" VALUE="0"/>
        <PARAMETER NAME="DAC_Decoder_Mode33" VALUE="0"/>
        <PARAMETER NAME="DAC_Mixer_Type33" VALUE="3"/>
        <PARAMETER NAME="DAC_Mixer_Mode33" VALUE="2"/>
        <PARAMETER NAME="DAC_Invsinc_Ctrl33" VALUE="false"/>
        <PARAMETER NAME="DAC_Coarse_Mixer_Freq33" VALUE="0"/>
        <PARAMETER NAME="DAC_NCO_Freq33" VALUE="0.0"/>
        <PARAMETER NAME="DAC_NCO_Phase33" VALUE="0"/>
        <PARAMETER NAME="DAC_Neg_Quadrature33" VALUE="false"/>
        <PARAMETER NAME="DAC_Nyquist33" VALUE="0"/>
        <PARAMETER NAME="DAC_Mode33" VALUE="0"/>
        <PARAMETER NAME="DAC_RESERVED_1_33" VALUE="false"/>
        <PARAMETER NAME="DAC_TDD_RTS33" VALUE="0"/>
        <PARAMETER NAME="mDAC_Enable" VALUE="0"/>
        <PARAMETER NAME="mDAC_PLL_Enable" VALUE="false"/>
        <PARAMETER NAME="mDAC_Sampling_Rate" VALUE="6.4"/>
        <PARAMETER NAME="mDAC_Refclk_Freq" VALUE="6400.000"/>
        <PARAMETER NAME="mDAC_Outclk_Freq" VALUE="50.000"/>
        <PARAMETER NAME="mDAC_Fabric_Freq" VALUE="0.0"/>
        <PARAMETER NAME="mDAC_Link_Coupling" VALUE="0"/>
        <PARAMETER NAME="mDAC_Multi_Tile_Sync" VALUE="false"/>
        <PARAMETER NAME="mDAC_Band" VALUE="0"/>
        <PARAMETER NAME="mDAC_VOP" VALUE="20.0"/>
        <PARAMETER NAME="mDAC_Refclk_Div" VALUE="1"/>
        <PARAMETER NAME="mDAC_Slice00_Enable" VALUE="false"/>
        <PARAMETER NAME="mDAC_Data_Type00" VALUE="0"/>
        <PARAMETER NAME="mDAC_Data_Width00" VALUE="16"/>
        <PARAMETER NAME="mDAC_Interpolation_Mode00" VALUE="0"/>
        <PARAMETER NAME="mDAC_Decoder_Mode00" VALUE="0"/>
        <PARAMETER NAME="mDAC_Mixer_Type00" VALUE="3"/>
        <PARAMETER NAME="mDAC_Mixer_Mode00" VALUE="2"/>
        <PARAMETER NAME="mDAC_Invsinc_Ctrl00" VALUE="false"/>
        <PARAMETER NAME="mDAC_Coarse_Mixer_Freq00" VALUE="0"/>
        <PARAMETER NAME="mDAC_NCO_Freq00" VALUE="0.0"/>
        <PARAMETER NAME="mDAC_NCO_Phase00" VALUE="0"/>
        <PARAMETER NAME="mDAC_Neg_Quadrature00" VALUE="false"/>
        <PARAMETER NAME="mDAC_Nyquist00" VALUE="0"/>
        <PARAMETER NAME="mDAC_Mode00" VALUE="0"/>
        <PARAMETER NAME="mDAC_RESERVED_1_00" VALUE="false"/>
        <PARAMETER NAME="mDAC_TDD_RTS00" VALUE="0"/>
        <PARAMETER NAME="mDAC_Slice01_Enable" VALUE="false"/>
        <PARAMETER NAME="mDAC_Data_Type01" VALUE="0"/>
        <PARAMETER NAME="mDAC_Data_Width01" VALUE="16"/>
        <PARAMETER NAME="mDAC_Interpolation_Mode01" VALUE="0"/>
        <PARAMETER NAME="mDAC_Decoder_Mode01" VALUE="0"/>
        <PARAMETER NAME="mDAC_Mixer_Type01" VALUE="3"/>
        <PARAMETER NAME="mDAC_Mixer_Mode01" VALUE="2"/>
        <PARAMETER NAME="mDAC_Invsinc_Ctrl01" VALUE="false"/>
        <PARAMETER NAME="mDAC_Coarse_Mixer_Freq01" VALUE="0"/>
        <PARAMETER NAME="mDAC_NCO_Freq01" VALUE="0.0"/>
        <PARAMETER NAME="mDAC_NCO_Phase01" VALUE="0"/>
        <PARAMETER NAME="mDAC_Neg_Quadrature01" VALUE="false"/>
        <PARAMETER NAME="mDAC_Nyquist01" VALUE="0"/>
        <PARAMETER NAME="mDAC_Mode01" VALUE="0"/>
        <PARAMETER NAME="mDAC_RESERVED_1_01" VALUE="false"/>
        <PARAMETER NAME="mDAC_TDD_RTS01" VALUE="0"/>
        <PARAMETER NAME="mDAC_Slice02_Enable" VALUE="false"/>
        <PARAMETER NAME="mDAC_Data_Type02" VALUE="0"/>
        <PARAMETER NAME="mDAC_Data_Width02" VALUE="16"/>
        <PARAMETER NAME="mDAC_Interpolation_Mode02" VALUE="0"/>
        <PARAMETER NAME="mDAC_Decoder_Mode02" VALUE="0"/>
        <PARAMETER NAME="mDAC_Mixer_Type02" VALUE="3"/>
        <PARAMETER NAME="mDAC_Mixer_Mode02" VALUE="2"/>
        <PARAMETER NAME="mDAC_Invsinc_Ctrl02" VALUE="false"/>
        <PARAMETER NAME="mDAC_Coarse_Mixer_Freq02" VALUE="0"/>
        <PARAMETER NAME="mDAC_NCO_Freq02" VALUE="0.0"/>
        <PARAMETER NAME="mDAC_NCO_Phase02" VALUE="0"/>
        <PARAMETER NAME="mDAC_Neg_Quadrature02" VALUE="false"/>
        <PARAMETER NAME="mDAC_Nyquist02" VALUE="0"/>
        <PARAMETER NAME="mDAC_Mode02" VALUE="0"/>
        <PARAMETER NAME="mDAC_RESERVED_1_02" VALUE="false"/>
        <PARAMETER NAME="mDAC_TDD_RTS02" VALUE="0"/>
        <PARAMETER NAME="mDAC_Slice03_Enable" VALUE="false"/>
        <PARAMETER NAME="mDAC_Data_Type03" VALUE="0"/>
        <PARAMETER NAME="mDAC_Data_Width03" VALUE="16"/>
        <PARAMETER NAME="mDAC_Interpolation_Mode03" VALUE="0"/>
        <PARAMETER NAME="mDAC_Decoder_Mode03" VALUE="0"/>
        <PARAMETER NAME="mDAC_Mixer_Type03" VALUE="3"/>
        <PARAMETER NAME="mDAC_Mixer_Mode03" VALUE="2"/>
        <PARAMETER NAME="mDAC_Invsinc_Ctrl03" VALUE="false"/>
        <PARAMETER NAME="mDAC_Coarse_Mixer_Freq03" VALUE="0"/>
        <PARAMETER NAME="mDAC_NCO_Freq03" VALUE="0.0"/>
        <PARAMETER NAME="mDAC_NCO_Phase03" VALUE="0"/>
        <PARAMETER NAME="mDAC_Neg_Quadrature03" VALUE="false"/>
        <PARAMETER NAME="mDAC_Nyquist03" VALUE="0"/>
        <PARAMETER NAME="mDAC_Mode03" VALUE="0"/>
        <PARAMETER NAME="mDAC_RESERVED_1_03" VALUE="false"/>
        <PARAMETER NAME="mDAC_TDD_RTS03" VALUE="0"/>
        <PARAMETER NAME="Clock_Forwarding" VALUE="false"/>
        <PARAMETER NAME="VNC_Testing" VALUE="false"/>
        <PARAMETER NAME="RESERVED_3" VALUE="110000"/>
        <PARAMETER NAME="VNC_Include_OIS_Change" VALUE="true"/>
        <PARAMETER NAME="VNC_Include_Fs2_Change" VALUE="true"/>
        <PARAMETER NAME="RF_Analyzer" VALUE="0"/>
        <PARAMETER NAME="PL_Clock_Freq" VALUE="100.0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xA0280000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xA02BFFFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" NAME="adc0_clk_p" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_adc0_clk_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="adc0_clk_clk_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="adc0_clk_n" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_adc0_clk_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="adc0_clk_clk_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="256000000" DIR="O" NAME="clk_adc0" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_adc0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_in1"/>
            <CONNECTION INSTANCE="rst_adc0" PORT="slowest_sync_clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="dac0_clk_p" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_dac0_clk_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="dac0_clk_clk_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="dac0_clk_n" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_dac0_clk_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="dac0_clk_clk_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="O" NAME="clk_dac0" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="m_axis_aclk"/>
            <CONNECTION INSTANCE="axis_cdcsync_v1_0" PORT="s_axis_aclk"/>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="s_axis_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="aclk"/>
            <CONNECTION INSTANCE="qick_processor_0" PORT="t_clk_i"/>
            <CONNECTION INSTANCE="rst_dac0" PORT="slowest_sync_clk"/>
            <CONNECTION INSTANCE="sg_translator_0" PORT="aclk"/>
            <CONNECTION INSTANCE="sg_translator_1" PORT="aclk"/>
            <CONNECTION INSTANCE="sg_translator_2" PORT="aclk"/>
            <CONNECTION INSTANCE="sg_translator_3" PORT="aclk"/>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s0_axis_aclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="dac1_clk_p" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_dac1_clk_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="dac1_clk_clk_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="dac1_clk_n" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_dac1_clk_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="dac1_clk_clk_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="O" NAME="clk_dac1" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_cdcsync_v1_1" PORT="m_axis_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="aclk"/>
            <CONNECTION INSTANCE="rst_dac1" PORT="slowest_sync_clk"/>
            <CONNECTION INSTANCE="sg_translator_4" PORT="aclk"/>
            <CONNECTION INSTANCE="sg_translator_5" PORT="aclk"/>
            <CONNECTION INSTANCE="sg_translator_6" PORT="aclk"/>
            <CONNECTION INSTANCE="sg_translator_7" PORT="aclk"/>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s1_axis_aclk"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="s_axi_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_100_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="17" NAME="s_axi_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_awvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_awready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="31" NAME="s_axi_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="s_axi_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_wvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_wready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_bvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_bready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="17" NAME="s_axi_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_arvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_arready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="31" NAME="s_axi_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="s_axi_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s_axi_rvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s_axi_rready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_M08_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="irq" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT"/>
        <PORT DIR="I" NAME="sysref_in_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_sysref_in_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="sysref_in_diff_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="sysref_in_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_sysref_in_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="sysref_in_diff_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="vin0_01_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vin0_01_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vin0_v_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="vin0_01_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vin0_01_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vin0_v_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="vin0_23_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vin0_23_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vin1_v_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="vin0_23_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vin0_23_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vin1_v_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout00_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout00_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout0_v_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout00_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout00_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout0_v_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout01_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout01_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout1_v_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout01_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout01_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout1_v_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout02_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout02_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout2_v_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout02_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout02_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout2_v_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout03_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout03_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout3_v_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout03_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout03_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout3_v_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout10_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout10_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout4_v_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout10_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout10_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout4_v_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout11_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout11_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout5_v_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout11_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout11_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout5_v_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout12_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout12_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout6_v_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout12_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout12_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout6_v_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout13_p" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout13_p">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout7_v_p"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="vout13_n" SIGIS="undef" SIGNAME="usp_rf_data_converter_0_vout13_n">
          <CONNECTIONS>
            <CONNECTION INSTANCE="d_1_imp" PORT="vout7_v_n"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m0_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_adc0_x2_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="512000000" DIR="I" NAME="m0_axis_aclk" SIGIS="clk" SIGNAME="clk_adc0_x2_clk_out1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="clk_adc0_x2" PORT="clk_out1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="m00_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_register_slice_0_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_register_slice_0" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m00_axis_tvalid" SIGIS="undef" SIGNAME="axis_register_slice_0_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_register_slice_0" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m00_axis_tready" SIGIS="undef" SIGNAME="axis_register_slice_0_s_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_register_slice_0" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="m02_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_register_slice_1_s_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_register_slice_1" PORT="s_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="m02_axis_tvalid" SIGIS="undef" SIGNAME="axis_register_slice_1_s_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_register_slice_1" PORT="s_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="m02_axis_tready" SIGIS="undef" SIGNAME="axis_register_slice_1_s_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_register_slice_1" PORT="s_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s0_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac0_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac0" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="s0_axis_aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="255" NAME="s00_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s00_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s00_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_0_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="255" NAME="s01_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s01_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s01_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_1_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="255" NAME="s02_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s02_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s02_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_2_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="255" NAME="s03_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s03_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s03_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_3_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s1_axis_aresetn" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="rst_dac1_peripheral_aresetn">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_dac1" PORT="peripheral_aresetn"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="384000000" DIR="I" NAME="s1_axis_aclk" SIGIS="clk" SIGNAME="usp_rf_data_converter_0_clk_dac1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="clk_dac1"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="255" NAME="s10_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s10_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s10_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_4_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="255" NAME="s11_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s11_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s11_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_5_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="255" NAME="s12_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s12_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s12_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_6_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="255" NAME="s13_axis_tdata" RIGHT="0" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_m_axis_tdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="m_axis_tdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="s13_axis_tvalid" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_m_axis_tvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="m_axis_tvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="s13_axis_tready" SIGIS="undef" SIGNAME="axis_signal_gen_v6_7_m_axis_tready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="m_axis_tready"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="ps8_0_axi_periph_M08_AXI" DATAWIDTH="32" NAME="s_axi" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="DATA_WIDTH" VALUE="32"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4LITE"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="18"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="0"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="0"/>
          <PARAMETER NAME="HAS_PROT" VALUE="0"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="0"/>
          <PARAMETER NAME="HAS_QOS" VALUE="0"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="2"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="1"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="s_axi_araddr"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="s_axi_arready"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="s_axi_arvalid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="s_axi_awaddr"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="s_axi_awready"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="s_axi_awvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="s_axi_bready"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="s_axi_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="s_axi_bvalid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="s_axi_rdata"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="s_axi_rready"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="s_axi_rresp"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="s_axi_rvalid"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="s_axi_wdata"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="s_axi_wready"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="s_axi_wstrb"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="s_axi_wvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_m00_axis" NAME="m00_axis" TYPE="MASTER" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="16"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m00_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m00_axis_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m00_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_m02_axis" NAME="m02_axis" TYPE="MASTER" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="16"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="512000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_clk_adc0_x2_0_clk_out1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="m02_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="m02_axis_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="m02_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_0_m_axis" NAME="s00_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s00_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s00_axis_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s00_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_1_m_axis" NAME="s01_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s01_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s01_axis_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s01_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_2_m_axis" NAME="s02_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s02_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s02_axis_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s02_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_3_m_axis" NAME="s03_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac0"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s03_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s03_axis_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s03_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_4_m_axis" NAME="s10_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s10_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s10_axis_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s10_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_5_m_axis" NAME="s11_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s11_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s11_axis_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s11_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_6_m_axis" NAME="s12_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s12_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s12_axis_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s12_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axis_signal_gen_v6_7_m_axis" NAME="s13_axis" TYPE="TARGET" VLNV="xilinx.com:interface:axis:1.0">
          <PARAMETER NAME="TDATA_NUM_BYTES" VALUE="32"/>
          <PARAMETER NAME="TDEST_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TID_WIDTH" VALUE="0"/>
          <PARAMETER NAME="TUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="HAS_TREADY" VALUE="1"/>
          <PARAMETER NAME="HAS_TSTRB" VALUE="0"/>
          <PARAMETER NAME="HAS_TKEEP" VALUE="0"/>
          <PARAMETER NAME="HAS_TLAST" VALUE="0"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="384000000"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_usp_rf_data_converter_0_0_clk_dac1"/>
          <PARAMETER NAME="LAYERED_METADATA" VALUE="undef"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="TDATA" PHYSICAL="s13_axis_tdata"/>
            <PORTMAP LOGICAL="TREADY" PHYSICAL="s13_axis_tready"/>
            <PORTMAP LOGICAL="TVALID" PHYSICAL="s13_axis_tvalid"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="External_Interface_adc0_clk" NAME="adc0_clk" TYPE="TARGET" VLNV="xilinx.com:interface:diff_clock:1.0">
          <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="CLK_N" PHYSICAL="adc0_clk_n"/>
            <PORTMAP LOGICAL="CLK_P" PHYSICAL="adc0_clk_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="External_Interface_dac0_clk" NAME="dac0_clk" TYPE="TARGET" VLNV="xilinx.com:interface:diff_clock:1.0">
          <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="CLK_N" PHYSICAL="dac0_clk_n"/>
            <PORTMAP LOGICAL="CLK_P" PHYSICAL="dac0_clk_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="External_Interface_dac1_clk" NAME="dac1_clk" TYPE="TARGET" VLNV="xilinx.com:interface:diff_clock:1.0">
          <PARAMETER NAME="CAN_DEBUG" VALUE="false"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="100000000"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="CLK_N" PHYSICAL="dac1_clk_n"/>
            <PORTMAP LOGICAL="CLK_P" PHYSICAL="dac1_clk_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="External_Interface_vin0" NAME="vin0_01" TYPE="TARGET" VLNV="xilinx.com:interface:diff_analog_io:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="V_N" PHYSICAL="vin0_01_n"/>
            <PORTMAP LOGICAL="V_P" PHYSICAL="vin0_01_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="External_Interface_vin1" NAME="vin0_23" TYPE="TARGET" VLNV="xilinx.com:interface:diff_analog_io:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="V_N" PHYSICAL="vin0_23_n"/>
            <PORTMAP LOGICAL="V_P" PHYSICAL="vin0_23_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout00" NAME="vout00" TYPE="INITIATOR" VLNV="xilinx.com:interface:diff_analog_io:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="V_N" PHYSICAL="vout00_n"/>
            <PORTMAP LOGICAL="V_P" PHYSICAL="vout00_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout01" NAME="vout01" TYPE="INITIATOR" VLNV="xilinx.com:interface:diff_analog_io:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="V_N" PHYSICAL="vout01_n"/>
            <PORTMAP LOGICAL="V_P" PHYSICAL="vout01_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout02" NAME="vout02" TYPE="INITIATOR" VLNV="xilinx.com:interface:diff_analog_io:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="V_N" PHYSICAL="vout02_n"/>
            <PORTMAP LOGICAL="V_P" PHYSICAL="vout02_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout03" NAME="vout03" TYPE="INITIATOR" VLNV="xilinx.com:interface:diff_analog_io:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="V_N" PHYSICAL="vout03_n"/>
            <PORTMAP LOGICAL="V_P" PHYSICAL="vout03_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout10" NAME="vout10" TYPE="INITIATOR" VLNV="xilinx.com:interface:diff_analog_io:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="V_N" PHYSICAL="vout10_n"/>
            <PORTMAP LOGICAL="V_P" PHYSICAL="vout10_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout11" NAME="vout11" TYPE="INITIATOR" VLNV="xilinx.com:interface:diff_analog_io:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="V_N" PHYSICAL="vout11_n"/>
            <PORTMAP LOGICAL="V_P" PHYSICAL="vout11_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout12" NAME="vout12" TYPE="INITIATOR" VLNV="xilinx.com:interface:diff_analog_io:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="V_N" PHYSICAL="vout12_n"/>
            <PORTMAP LOGICAL="V_P" PHYSICAL="vout12_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="usp_rf_data_converter_0_vout13" NAME="vout13" TYPE="INITIATOR" VLNV="xilinx.com:interface:diff_analog_io:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="V_N" PHYSICAL="vout13_n"/>
            <PORTMAP LOGICAL="V_P" PHYSICAL="vout13_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="External_Interface_sysref_in" NAME="sysref_in" TYPE="TARGET" VLNV="xilinx.com:display_usp_rf_data_converter:diff_pins:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="diff_n" PHYSICAL="sysref_in_n"/>
            <PORTMAP LOGICAL="diff_p" PHYSICAL="sysref_in_p"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
    </MODULE>
    <MODULE COREREVISION="4" FULLNAME="/xlconcat_0" HWVERSION="2.1" INSTANCE="xlconcat_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" MODCLASS="PERIPHERAL" MODTYPE="xlconcat" VLNV="xilinx.com:ip:xlconcat:2.1">
      <DOCUMENTS/>
      <PARAMETERS>
        <PARAMETER NAME="IN0_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN1_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN2_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN3_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN4_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN5_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN6_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN7_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN8_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN9_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN10_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN11_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN12_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN13_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN14_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN15_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN16_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN17_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN18_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN19_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN20_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN21_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN22_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN23_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN24_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN25_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN26_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN27_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN28_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN29_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN30_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN31_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN32_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN33_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN34_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN35_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN36_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN37_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN38_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN39_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN40_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN41_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN42_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN43_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN44_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN45_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN46_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN47_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN48_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN49_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN50_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN51_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN52_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN53_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN54_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN55_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN56_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN57_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN58_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN59_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN60_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN61_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN62_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN63_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN64_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN65_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN66_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN67_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN68_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN69_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN70_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN71_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN72_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN73_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN74_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN75_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN76_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN77_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN78_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN79_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN80_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN81_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN82_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN83_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN84_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN85_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN86_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN87_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN88_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN89_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN90_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN91_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN92_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN93_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN94_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN95_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN96_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN97_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN98_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN99_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN100_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN101_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN102_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN103_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN104_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN105_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN106_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN107_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN108_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN109_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN110_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN111_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN112_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN113_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN114_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN115_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN116_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN117_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN118_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN119_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN120_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN121_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN122_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN123_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN124_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN125_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN126_WIDTH" VALUE="1"/>
        <PARAMETER NAME="IN127_WIDTH" VALUE="1"/>
        <PARAMETER NAME="dout_width" VALUE="6"/>
        <PARAMETER NAME="NUM_PORTS" VALUE="6"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_xlconcat_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
      </PARAMETERS>
      <PORTS>
        <PORT DIR="I" LEFT="0" NAME="In0" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_mm2s_introut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="mm2s_introut"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="In1" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_tproc_s2mm_introut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s2mm_introut"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="In2" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_gen_mm2s_introut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="mm2s_introut"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="In3" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_avg_s2mm_introut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s2mm_introut"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="In4" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_buf_s2mm_introut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s2mm_introut"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="0" NAME="In5" RIGHT="0" SIGIS="undef" SIGNAME="axi_dma_mr_s2mm_introut">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s2mm_introut"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="5" NAME="dout" RIGHT="0" SIGIS="undef" SIGNAME="xlconcat_0_dout">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="intr"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES/>
    </MODULE>
    <MODULE CONFIGURABLE="TRUE" COREREVISION="0" FULLNAME="/zynq_ultra_ps_e_0" HWVERSION="3.4" INSTANCE="zynq_ultra_ps_e_0" IPTYPE="PERIPHERAL" IS_ENABLE="1" IS_PL="FALSE" MODTYPE="zynq_ultra_ps_e" VLNV="xilinx.com:ip:zynq_ultra_ps_e:3.4">
      <DOCUMENTS>
        <DOCUMENT SOURCE="http://www.xilinx.com/cgi-bin/docs/ipdoc?c=zynq_ultra_ps_e;v=v3_4;d=pg201-zynq-ultrascale-plus-processing-system.pdf"/>
      </DOCUMENTS>
      <PARAMETERS>
        <PARAMETER NAME="C_DP_USE_AUDIO" VALUE="0"/>
        <PARAMETER NAME="C_DP_USE_VIDEO" VALUE="0"/>
        <PARAMETER NAME="C_MAXIGP0_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_MAXIGP1_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_MAXIGP2_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_SAXIGP0_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_SAXIGP1_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_SAXIGP2_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_SAXIGP3_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_SAXIGP4_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_SAXIGP5_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_SAXIGP6_DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP0" VALUE="0"/>
        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP1" VALUE="0"/>
        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP2" VALUE="0"/>
        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP3" VALUE="0"/>
        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP4" VALUE="0"/>
        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP5" VALUE="0"/>
        <PARAMETER NAME="C_USE_DIFF_RW_CLK_GP6" VALUE="0"/>
        <PARAMETER NAME="C_EN_FIFO_ENET0" VALUE="0"/>
        <PARAMETER NAME="C_EN_FIFO_ENET1" VALUE="0"/>
        <PARAMETER NAME="C_EN_FIFO_ENET2" VALUE="0"/>
        <PARAMETER NAME="C_EN_FIFO_ENET3" VALUE="0"/>
        <PARAMETER NAME="C_PL_CLK0_BUF" VALUE="TRUE"/>
        <PARAMETER NAME="C_PL_CLK1_BUF" VALUE="FALSE"/>
        <PARAMETER NAME="C_PL_CLK2_BUF" VALUE="FALSE"/>
        <PARAMETER NAME="C_PL_CLK3_BUF" VALUE="FALSE"/>
        <PARAMETER NAME="C_TRACE_PIPELINE_WIDTH" VALUE="8"/>
        <PARAMETER NAME="C_EN_EMIO_TRACE" VALUE="0"/>
        <PARAMETER NAME="C_TRACE_DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="C_USE_DEBUG_TEST" VALUE="0"/>
        <PARAMETER NAME="C_SD0_INTERNAL_BUS_WIDTH" VALUE="5"/>
        <PARAMETER NAME="C_SD1_INTERNAL_BUS_WIDTH" VALUE="8"/>
        <PARAMETER NAME="C_NUM_F2P_0_INTR_INPUTS" VALUE="1"/>
        <PARAMETER NAME="C_NUM_F2P_1_INTR_INPUTS" VALUE="1"/>
        <PARAMETER NAME="C_EMIO_GPIO_WIDTH" VALUE="1"/>
        <PARAMETER NAME="C_NUM_FABRIC_RESETS" VALUE="1"/>
        <PARAMETER NAME="PSU_VALUE_SILVERSION" VALUE="3"/>
        <PARAMETER NAME="PSU__USE__DDR_INTF_REQUESTED" VALUE="0"/>
        <PARAMETER NAME="PSU__EN_AXI_STATUS_PORTS" VALUE="0"/>
        <PARAMETER NAME="PSU__PSS_REF_CLK__FREQMHZ" VALUE="33.333"/>
        <PARAMETER NAME="PSU__PSS_ALT_REF_CLK__FREQMHZ" VALUE="33.333"/>
        <PARAMETER NAME="PSU__VIDEO_REF_CLK__FREQMHZ" VALUE="33.333"/>
        <PARAMETER NAME="PSU__AUX_REF_CLK__FREQMHZ" VALUE="33.333"/>
        <PARAMETER NAME="PSU__GT_REF_CLK__FREQMHZ" VALUE="33.333"/>
        <PARAMETER NAME="PSU__VIDEO_REF_CLK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__VIDEO_REF_CLK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PSS_ALT_REF_CLK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PSS_ALT_REF_CLK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CAN0__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CAN0__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CAN0__GRP_CLK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CAN0__GRP_CLK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CAN1__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CAN1__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CAN1__GRP_CLK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CAN1__GRP_CLK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CAN0_LOOP_CAN1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__DPAUX__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__DPAUX__PERIPHERAL__IO" VALUE="MIO 27 .. 30"/>
        <PARAMETER NAME="PSU__ENET0__GRP_MDIO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ACT_DDR_FREQ_MHZ" VALUE="1066.656006"/>
        <PARAMETER NAME="PSU__ENET0__GRP_MDIO__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM__TSU__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM__TSU__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__ENET0__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET0__FIFO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET0__PTP__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET0__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__ENET1__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET1__FIFO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET1__PTP__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET1__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__ENET1__GRP_MDIO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__FPGA_PL0_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__FPGA_PL1_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__FPGA_PL2_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__FPGA_PL3_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET1__GRP_MDIO__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__ENET2__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET2__FIFO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET2__PTP__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET2__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__ENET2__GRP_MDIO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET2__GRP_MDIO__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__ENET3__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__ENET3__FIFO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET3__PTP__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET3__PERIPHERAL__IO" VALUE="MIO 64 .. 75"/>
        <PARAMETER NAME="PSU__ENET3__GRP_MDIO__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__ENET3__GRP_MDIO__IO" VALUE="MIO 76 .. 77"/>
        <PARAMETER NAME="PSU__GPIO_EMIO__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__GPIO_EMIO__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GPIO0_MIO__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__GPIO0_MIO__IO" VALUE="MIO 0 .. 25"/>
        <PARAMETER NAME="PSU__GPIO1_MIO__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__GPIO1_MIO__IO" VALUE="MIO 26 .. 51"/>
        <PARAMETER NAME="PSU__GPIO2_MIO__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__GPIO2_MIO__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__I2C0__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__I2C0__PERIPHERAL__IO" VALUE="MIO 14 .. 15"/>
        <PARAMETER NAME="PSU__I2C0__GRP_INT__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__I2C0__GRP_INT__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__I2C1__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__I2C1__PERIPHERAL__IO" VALUE="MIO 16 .. 17"/>
        <PARAMETER NAME="PSU__I2C1__GRP_INT__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__I2C1__GRP_INT__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__I2C0_LOOP_I2C1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TESTSCAN__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__PERIPHERAL__ENDPOINT_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__PERIPHERAL__ROOTPORT_IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__LANE0__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__LANE0__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__LANE1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__LANE1__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__LANE2__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__LANE2__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__LANE3__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__LANE3__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__RESET__POLARITY" VALUE="Active Low"/>
        <PARAMETER NAME="PSU__GT__LINK_SPEED" VALUE="HBR"/>
        <PARAMETER NAME="PSU__GT__VLT_SWNG_LVL_4" VALUE="0"/>
        <PARAMETER NAME="PSU__GT__PRE_EMPH_LVL_4" VALUE="0"/>
        <PARAMETER NAME="PSU__USB0__REF_CLK_SEL" VALUE="Ref Clk2"/>
        <PARAMETER NAME="PSU__USB0__REF_CLK_FREQ" VALUE="26"/>
        <PARAMETER NAME="PSU__USB1__REF_CLK_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__USB1__REF_CLK_FREQ" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM0__REF_CLK_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM0__REF_CLK_FREQ" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM1__REF_CLK_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM1__REF_CLK_FREQ" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM2__REF_CLK_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM2__REF_CLK_FREQ" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM3__REF_CLK_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEM3__REF_CLK_FREQ" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DP__REF_CLK_SEL" VALUE="Ref Clk1"/>
        <PARAMETER NAME="PSU__DP__REF_CLK_FREQ" VALUE="27"/>
        <PARAMETER NAME="PSU__SATA__REF_CLK_SEL" VALUE="Ref Clk3"/>
        <PARAMETER NAME="PSU__SATA__REF_CLK_FREQ" VALUE="125"/>
        <PARAMETER NAME="PSU__PCIE__REF_CLK_SEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__REF_CLK_FREQ" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DP__LANE_SEL" VALUE="Dual Lower"/>
        <PARAMETER NAME="PSU__PCIE__DEVICE_PORT_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__MAXIMUM_LINK_WIDTH" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__LINK_SPEED" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__INTERFACE_WIDTH" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR0_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR0_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR0_SCALE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR0_64BIT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR0_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR0_VAL"/>
        <PARAMETER NAME="PSU__PCIE__BAR0_PREFETCHABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR1_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR1_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR1_SCALE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR1_64BIT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR1_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR1_VAL"/>
        <PARAMETER NAME="PSU__PCIE__BAR1_PREFETCHABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR2_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR2_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR2_SCALE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR2_64BIT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR2_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR2_VAL"/>
        <PARAMETER NAME="PSU__PCIE__BAR2_PREFETCHABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR3_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR3_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR3_SCALE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR3_64BIT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR3_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR3_VAL"/>
        <PARAMETER NAME="PSU__PCIE__BAR3_PREFETCHABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR4_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR4_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR4_SCALE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR4_64BIT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR4_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR4_VAL"/>
        <PARAMETER NAME="PSU__PCIE__BAR4_PREFETCHABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR5_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR5_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR5_SCALE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR5_64BIT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__BAR5_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__BAR5_VAL"/>
        <PARAMETER NAME="PSU__PCIE__BAR5_PREFETCHABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__EROM_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__EROM_SCALE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__EROM_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__EROM_VAL"/>
        <PARAMETER NAME="PSU__PCIE__CAP_SLOT_IMPLEMENTED" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__MAX_PAYLOAD_SIZE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__LEGACY_INTERRUPT" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__VENDOR_ID"/>
        <PARAMETER NAME="PSU__PCIE__DEVICE_ID"/>
        <PARAMETER NAME="PSU__PCIE__REVISION_ID"/>
        <PARAMETER NAME="PSU__PCIE__SUBSYSTEM_VENDOR_ID"/>
        <PARAMETER NAME="PSU__PCIE__SUBSYSTEM_ID"/>
        <PARAMETER NAME="PSU__PCIE__BASE_CLASS_MENU" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__USE_CLASS_CODE_LOOKUP_ASSISTANT" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__SUB_CLASS_INTERFACE_MENU" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__CLASS_CODE_BASE"/>
        <PARAMETER NAME="PSU__PCIE__CLASS_CODE_SUB"/>
        <PARAMETER NAME="PSU__PCIE__CLASS_CODE_INTERFACE"/>
        <PARAMETER NAME="PSU__PCIE__CLASS_CODE_VALUE"/>
        <PARAMETER NAME="PSU__PCIE__AER_CAPABILITY" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__CORRECTABLE_INT_ERR" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__HEADER_LOG_OVERFLOW" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__RECEIVER_ERR" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__SURPRISE_DOWN" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__FLOW_CONTROL_ERR" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__COMPLTION_TIMEOUT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__COMPLETER_ABORT" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__RECEIVER_OVERFLOW" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__ECRC_ERR" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__ACS_VIOLAION" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__UNCORRECTABL_INT_ERR" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__MC_BLOCKED_TLP" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__ATOMICOP_EGRESS_BLOCKED" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__TLP_PREFIX_BLOCKED" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__ACS_VIOLATION" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__MULTIHEADER" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__ECRC_CHECK" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__ECRC_GEN" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__PERM_ROOT_ERR_UPDATE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__CRS_SW_VISIBILITY" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__INTX_GENERATION" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__INTX_PIN" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__MSI_CAPABILITY" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__MSI_64BIT_ADDR_CAPABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__MSI_MULTIPLE_MSG_CAPABLE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PCIE__MSIX_CAPABILITY" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__MSIX_TABLE_SIZE" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__MSIX_TABLE_OFFSET" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__MSIX_BAR_INDICATOR"/>
        <PARAMETER NAME="PSU__PCIE__MSIX_PBA_OFFSET" VALUE="0"/>
        <PARAMETER NAME="PSU__PCIE__MSIX_PBA_BAR_INDICATOR"/>
        <PARAMETER NAME="PSU__PCIE__BRIDGE_BAR_INDICATOR" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU_IMPORT_BOARD_PRESET"/>
        <PARAMETER NAME="PSU__PROTECTION__SUBSYSTEMS" VALUE="PMU Firmware:PMU|Secure Subsystem:"/>
        <PARAMETER NAME="PSU__PROTECTION__MASTERS_TZ" VALUE="GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure"/>
        <PARAMETER NAME="PSU__PROTECTION__MASTERS" VALUE="USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;1|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1"/>
        <PARAMETER NAME="PSU__PROTECTION__DDR_SEGMENTS" VALUE="NONE"/>
        <PARAMETER NAME="PSU__PROTECTION__OCM_SEGMENTS" VALUE="NONE"/>
        <PARAMETER NAME="PSU__PROTECTION__LPD_SEGMENTS" VALUE="SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem"/>
        <PARAMETER NAME="PSU__PROTECTION__FPD_SEGMENTS" VALUE="SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware  |   SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware  |   SA:0xFD010000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware  |   SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware  |   SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware  |   SA:0xFD040000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware  |   SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware  |   SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware  |   SA:0xFD5D0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware  |  SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem"/>
        <PARAMETER NAME="PSU__PROTECTION__DEBUG" VALUE="0"/>
        <PARAMETER NAME="PSU__PROTECTION__SLAVES" VALUE="LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;1|FPD;GPU;FD4B0000;FD4BFFFF;0|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;87FFFFFFF;1|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;0|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1"/>
        <PARAMETER NAME="PSU__PROTECTION__PRESUBSYSTEMS" VALUE="NONE"/>
        <PARAMETER NAME="PSU__PROTECTION__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__DDR_SW_REFRESH_ENABLED" VALUE="1"/>
        <PARAMETER NAME="PSU__PROTECTION__LOCK_UNUSED_SEGMENTS" VALUE="0"/>
        <PARAMETER NAME="PSU__EP__IP" VALUE="0"/>
        <PARAMETER NAME="PSU__ACTUAL__IP" VALUE="1"/>
        <PARAMETER NAME="SUBPRESET1" VALUE="Custom"/>
        <PARAMETER NAME="SUBPRESET2" VALUE="Custom"/>
        <PARAMETER NAME="PSU_UIPARAM_GENERATE_SUMMARY" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU_MIO_TREE_PERIPHERALS" VALUE="Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Feedback Clk#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO0 MIO#I2C 0#I2C 0#I2C 1#I2C 1#UART 0#UART 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO1 MIO#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#PMU GPO 3#PMU GPO 4#PMU GPO 5#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO 3"/>
        <PARAMETER NAME="PSU_MIO_TREE_SIGNALS" VALUE="sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk#n_ss_out_upper#mo_upper[0]#mo_upper[1]#mo_upper[2]#mo_upper[3]#sclk_out_upper#gpio0[13]#scl_out#sda_out#scl_out#sda_out#rxd#txd#gpio0[20]#gpio0[21]#gpio0[22]#gpio0[23]#gpio0[24]#gpio0[25]#gpio1[26]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpo[3]#gpo[4]#gpo[5]#gpio1[38]#sdio1_data_out[4]#sdio1_data_out[5]#sdio1_data_out[6]#sdio1_data_out[7]#gpio1[43]#gpio1[44]#sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out"/>
        <PARAMETER NAME="PSU_PERIPHERAL_BOARD_PRESET"/>
        <PARAMETER NAME="PSU__NAND__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__NAND__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND__READY_BUSY__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND__READY0_BUSY__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND__READY1_BUSY__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND__READY_BUSY__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__NAND__READY0_BUSY__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__NAND__READY1_BUSY__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__NAND__CHIP_ENABLE__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND__CHIP_ENABLE__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__NAND__DATA_STROBE__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND__DATA_STROBE__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PJTAG__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PJTAG__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__AIBACK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__PLERROR__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__PMU__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__EMIO_GPI__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__EMIO_GPO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPI0__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPI1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPI2__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPI3__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPI4__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPI5__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU__GPO0__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__PMU__GPO1__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__PMU__GPO2__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__PMU__GPO3__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__PMU__GPO4__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__PMU__GPO5__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__PMU__GPI0__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPI1__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPI2__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPI3__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPI4__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPI5__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__PMU__GPO0__IO" VALUE="MIO 32"/>
        <PARAMETER NAME="PSU__PMU__GPO1__IO" VALUE="MIO 33"/>
        <PARAMETER NAME="PSU__PMU__GPO2__IO" VALUE="MIO 34"/>
        <PARAMETER NAME="PSU__PMU__GPO3__IO" VALUE="MIO 35"/>
        <PARAMETER NAME="PSU__PMU__GPO4__IO" VALUE="MIO 36"/>
        <PARAMETER NAME="PSU__PMU__GPO5__IO" VALUE="MIO 37"/>
        <PARAMETER NAME="PSU__PMU__GPO2__POLARITY" VALUE="low"/>
        <PARAMETER NAME="PSU__PMU__GPO3__POLARITY" VALUE="low"/>
        <PARAMETER NAME="PSU__PMU__GPO4__POLARITY" VALUE="low"/>
        <PARAMETER NAME="PSU__PMU__GPO5__POLARITY" VALUE="low"/>
        <PARAMETER NAME="PSU__CSU__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__QSPI__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__QSPI__PERIPHERAL__IO" VALUE="MIO 0 .. 12"/>
        <PARAMETER NAME="PSU__QSPI__PERIPHERAL__MODE" VALUE="Dual Parallel"/>
        <PARAMETER NAME="PSU__QSPI__PERIPHERAL__DATA_MODE" VALUE="x4"/>
        <PARAMETER NAME="PSU__QSPI__GRP_FBCLK__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__QSPI__GRP_FBCLK__IO" VALUE="MIO 6"/>
        <PARAMETER NAME="PSU__SD0__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD0__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD0__GRP_CD__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD0__GRP_CD__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD0__GRP_POW__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD0__GRP_POW__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD0__GRP_WP__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD0__GRP_WP__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD0__SLOT_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD0__RESET__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD0__DATA_TRANSFER_MODE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD0__CLK_50_SDR_ITAP_DLY" VALUE="0x15"/>
        <PARAMETER NAME="PSU__SD0__CLK_50_SDR_OTAP_DLY" VALUE="0x5"/>
        <PARAMETER NAME="PSU__SD0__CLK_50_DDR_ITAP_DLY" VALUE="0x3D"/>
        <PARAMETER NAME="PSU__SD0__CLK_50_DDR_OTAP_DLY" VALUE="0x4"/>
        <PARAMETER NAME="PSU__SD0__CLK_100_SDR_OTAP_DLY" VALUE="0x3"/>
        <PARAMETER NAME="PSU__SD0__CLK_200_SDR_OTAP_DLY" VALUE="0x3"/>
        <PARAMETER NAME="PSU__SD1__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__SD1__PERIPHERAL__IO" VALUE="MIO 39 .. 51"/>
        <PARAMETER NAME="PSU__SD1__GRP_CD__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__SD1__GRP_CD__IO" VALUE="MIO 45"/>
        <PARAMETER NAME="PSU__SD1__GRP_POW__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD1__GRP_POW__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD1__GRP_WP__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD1__GRP_WP__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SD1__SLOT_TYPE" VALUE="SD 3.0"/>
        <PARAMETER NAME="PSU__SD1__RESET__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SD1__DATA_TRANSFER_MODE" VALUE="8Bit"/>
        <PARAMETER NAME="PSU__SD1__CLK_50_SDR_ITAP_DLY" VALUE="0x15"/>
        <PARAMETER NAME="PSU__SD1__CLK_50_SDR_OTAP_DLY" VALUE="0x5"/>
        <PARAMETER NAME="PSU__SD1__CLK_50_DDR_ITAP_DLY" VALUE="0x3D"/>
        <PARAMETER NAME="PSU__SD1__CLK_50_DDR_OTAP_DLY" VALUE="0x4"/>
        <PARAMETER NAME="PSU__SD1__CLK_100_SDR_OTAP_DLY" VALUE="0x3"/>
        <PARAMETER NAME="PSU__SD1__CLK_200_SDR_OTAP_DLY" VALUE="0x3"/>
        <PARAMETER NAME="PSU__DEVICE_TYPE" VALUE="RFSOC"/>
        <PARAMETER NAME="PSU_SMC_CYCLE_T0" VALUE="NA"/>
        <PARAMETER NAME="PSU_SMC_CYCLE_T1" VALUE="NA"/>
        <PARAMETER NAME="PSU_SMC_CYCLE_T2" VALUE="NA"/>
        <PARAMETER NAME="PSU_SMC_CYCLE_T3" VALUE="NA"/>
        <PARAMETER NAME="PSU_SMC_CYCLE_T4" VALUE="NA"/>
        <PARAMETER NAME="PSU_SMC_CYCLE_T5" VALUE="NA"/>
        <PARAMETER NAME="PSU_SMC_CYCLE_T6" VALUE="NA"/>
        <PARAMETER NAME="PSU__SPI0__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SPI0__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SPI0__GRP_SS0__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SPI0__GRP_SS0__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SPI0__GRP_SS1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SPI0__GRP_SS1__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SPI0__GRP_SS2__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SPI0__GRP_SS2__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SPI1__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SPI1__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SPI1__GRP_SS0__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SPI1__GRP_SS0__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SPI1__GRP_SS1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SPI1__GRP_SS1__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SPI1__GRP_SS2__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SPI1__GRP_SS2__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SPI0_LOOP_SPI1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT" VALUE="APB"/>
        <PARAMETER NAME="PSU__SWDT0__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__SWDT0__CLOCK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SWDT0__RESET__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SWDT0__PERIPHERAL__IO" VALUE="NA"/>
        <PARAMETER NAME="PSU__SWDT0__CLOCK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SWDT0__RESET__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SWDT1__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__SWDT1__CLOCK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SWDT1__RESET__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SWDT1__PERIPHERAL__IO" VALUE="NA"/>
        <PARAMETER NAME="PSU__SWDT1__CLOCK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SWDT1__RESET__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__UART0__BAUD_RATE" VALUE="115200"/>
        <PARAMETER NAME="PSU__TRACE__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TRACE__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TRACE__WIDTH" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TRACE__INTERNAL_WIDTH" VALUE="32"/>
        <PARAMETER NAME="PSU_SD0_INTERNAL_BUS_WIDTH" VALUE="8"/>
        <PARAMETER NAME="PSU__TTC0__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__TTC0__CLOCK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC0__WAVEOUT__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC0__CLOCK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TTC0__WAVEOUT__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TTC0__PERIPHERAL__IO" VALUE="NA"/>
        <PARAMETER NAME="PSU__TTC1__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__TTC1__PERIPHERAL__IO" VALUE="NA"/>
        <PARAMETER NAME="PSU__UART1__BAUD_RATE" VALUE="115200"/>
        <PARAMETER NAME="PSU__TTC1__CLOCK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC1__WAVEOUT__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC1__CLOCK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TTC1__WAVEOUT__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TTC2__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__TTC2__PERIPHERAL__IO" VALUE="NA"/>
        <PARAMETER NAME="PSU__TTC2__CLOCK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC2__WAVEOUT__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC2__CLOCK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TTC2__WAVEOUT__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TTC3__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__TTC3__PERIPHERAL__IO" VALUE="NA"/>
        <PARAMETER NAME="PSU__TTC3__CLOCK__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC3__WAVEOUT__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TTC3__CLOCK__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__TTC3__WAVEOUT__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSUPMU__PERIPHERAL__VALID" VALUE="1"/>
        <PARAMETER NAME="PSU__DDRC__AL" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__BANK_ADDR_COUNT" VALUE="2"/>
        <PARAMETER NAME="PSU__DDRC__BUS_WIDTH" VALUE="64 Bit"/>
        <PARAMETER NAME="PSU__DDRC__CL" VALUE="15"/>
        <PARAMETER NAME="PSU__DDRC__CLOCK_STOP_EN" VALUE="0"/>
        <PARAMETER NAME="PSU_DYNAMIC_DDR_CONFIG_EN" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__COL_ADDR_COUNT" VALUE="10"/>
        <PARAMETER NAME="PSU__DDRC__RANK_ADDR_COUNT" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__CWL" VALUE="14"/>
        <PARAMETER NAME="PSU__DDRC__BG_ADDR_COUNT" VALUE="1"/>
        <PARAMETER NAME="PSU__DDRC__DEVICE_CAPACITY" VALUE="8192 MBits"/>
        <PARAMETER NAME="PSU__DDRC__DRAM_WIDTH" VALUE="16 Bits"/>
        <PARAMETER NAME="PSU__DDRC__ECC" VALUE="Disabled"/>
        <PARAMETER NAME="PSU__DDRC__ECC_SCRUB" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__DDRC__FREQ_MHZ" VALUE="1"/>
        <PARAMETER NAME="PSU__DDRC__HIGH_TEMP" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDRC__MEMORY_TYPE" VALUE="DDR 4"/>
        <PARAMETER NAME="PSU__DDRC__PARTNO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDRC__ROW_ADDR_COUNT" VALUE="16"/>
        <PARAMETER NAME="PSU__DDRC__SPEED_BIN" VALUE="DDR4_2133P"/>
        <PARAMETER NAME="PSU__DDRC__T_FAW" VALUE="30.0"/>
        <PARAMETER NAME="PSU__DDRC__T_RAS_MIN" VALUE="33"/>
        <PARAMETER NAME="PSU__DDRC__T_RC" VALUE="47.06"/>
        <PARAMETER NAME="PSU__DDRC__T_RCD" VALUE="15"/>
        <PARAMETER NAME="PSU__DDRC__T_RP" VALUE="15"/>
        <PARAMETER NAME="PSU__DDRC__TRAIN_DATA_EYE" VALUE="1"/>
        <PARAMETER NAME="PSU__DDRC__TRAIN_READ_GATE" VALUE="1"/>
        <PARAMETER NAME="PSU__DDRC__TRAIN_WRITE_LEVEL" VALUE="1"/>
        <PARAMETER NAME="PSU__DDRC__VREF" VALUE="1"/>
        <PARAMETER NAME="PSU__DDRC__VIDEO_BUFFER_SIZE" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__BRC_MAPPING" VALUE="ROW_BANK_COL"/>
        <PARAMETER NAME="PSU__DDRC__DIMM_ADDR_MIRROR" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__STATIC_RD_MODE" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DDR4_MAXPWR_SAVING_EN" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__PWR_DOWN_EN" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DEEP_PWR_DOWN_EN" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__PLL_BYPASS" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DDR4_T_REF_MODE" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DDR4_T_REF_RANGE" VALUE="Normal (0-85)"/>
        <PARAMETER NAME="PSU__DDRC__DDR3_T_REF_RANGE" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__DDR3L_T_REF_RANGE" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__LPDDR3_T_REF_RANGE" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__LPDDR4_T_REF_RANGE" VALUE="NA"/>
        <PARAMETER NAME="PSU__DDRC__PHY_DBI_MODE" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DM_DBI" VALUE="DM_NO_DBI"/>
        <PARAMETER NAME="PSU__DDRC__COMPONENTS" VALUE="UDIMM"/>
        <PARAMETER NAME="PSU__DDRC__PARITY_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DDR4_CAL_MODE_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DDR4_CRC_CONTROL" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__FGRM" VALUE="1X"/>
        <PARAMETER NAME="PSU__DDRC__VENDOR_PART" VALUE="OTHERS"/>
        <PARAMETER NAME="PSU__DDRC__SB_TARGET" VALUE="15-15-15"/>
        <PARAMETER NAME="PSU__DDRC__LP_ASR" VALUE="manual normal"/>
        <PARAMETER NAME="PSU__DDRC__DDR4_ADDR_MAPPING" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__SELF_REF_ABORT" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DERATE_INT_D" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDRC__ADDR_MIRROR" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__EN_2ND_CLK" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__LPDDR3_DUALRANK_SDP" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__PER_BANK_REFRESH" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__ENABLE_DP_SWITCH" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__ENABLE_LP4_SLOWBOOT" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__ENABLE_2T_TIMING" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__RD_DQS_CENTER" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_0_3" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_4_7" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_8_11" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_12_15" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_16_19" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_20_23" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_24_27" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_28_31" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_32_35" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_36_39" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_40_43" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_44_47" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_48_51" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_52_55" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_56_59" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_60_63" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_64_67" VALUE="0"/>
        <PARAMETER NAME="PSU__DDRC__DQMAP_68_71" VALUE="0"/>
        <PARAMETER NAME="PSU_DDR_RAM_HIGHADDR" VALUE="0xFFFFFFFF"/>
        <PARAMETER NAME="PSU_DDR_RAM_HIGHADDR_OFFSET" VALUE="0x800000000"/>
        <PARAMETER NAME="PSU_DDR_RAM_LOWADDR_OFFSET" VALUE="0x80000000"/>
        <PARAMETER NAME="PSU__DDR_QOS_ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT0_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT1_VN1_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT1_VN2_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT2_VN1_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT2_VN2_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT3_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT4_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_PORT5_TYPE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__DDR_QOS_RD_LPR_THRSHLD"/>
        <PARAMETER NAME="PSU__DDR_QOS_RD_HPR_THRSHLD"/>
        <PARAMETER NAME="PSU__DDR_QOS_WR_THRSHLD"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP0_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP0_WRQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP1_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP1_WRQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP2_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP2_WRQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP3_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_HP3_WRQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP0_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP0_WRQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP1_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP1_WRQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP2_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP2_WRQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP3_RDQOS"/>
        <PARAMETER NAME="PSU__DDR_QOS_FIX_HP3_WRQOS"/>
        <PARAMETER NAME="PSU__OVERRIDE_HPX_QOS" VALUE="0"/>
        <PARAMETER NAME="PSU__FP__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__PL__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__OCM_BANK0__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__OCM_BANK1__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__OCM_BANK2__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__OCM_BANK3__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__TCM0A__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__TCM0B__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__TCM1A__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__TCM1B__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__RPU__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__L2_BANK0__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__GPU_PP0__POWER__ON" VALUE="0"/>
        <PARAMETER NAME="PSU__GPU_PP1__POWER__ON" VALUE="0"/>
        <PARAMETER NAME="PSU__ACPU0__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__ACPU1__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__ACPU2__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__ACPU3__POWER__ON" VALUE="1"/>
        <PARAMETER NAME="PSU__UART0__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__UART0__PERIPHERAL__IO" VALUE="MIO 18 .. 19"/>
        <PARAMETER NAME="PSU__UART0__MODEM__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__UART1__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__UART1__PERIPHERAL__IO" VALUE="EMIO"/>
        <PARAMETER NAME="PSU__UART1__MODEM__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__UART0_LOOP_UART1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB0__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__USB0__PERIPHERAL__IO" VALUE="MIO 52 .. 63"/>
        <PARAMETER NAME="PSU__USB0__RESET__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB0__RESET__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__USB__RESET__MODE" VALUE="Boot Pin"/>
        <PARAMETER NAME="PSU__USB__RESET__POLARITY" VALUE="Active Low"/>
        <PARAMETER NAME="PSU__USB1__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB1__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__USB1__RESET__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB1__RESET__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__USB3_0__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__USB3_0__PERIPHERAL__IO" VALUE="GT Lane2"/>
        <PARAMETER NAME="PSU__USB3_1__PERIPHERAL__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB3_1__PERIPHERAL__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__USB3_0__EMIO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB2_0__EMIO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB3_1__EMIO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USB2_1__EMIO__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__USB3_0_HUB" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__USB3_1_HUB" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__ADMA" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__M_AXI_GP0" VALUE="1"/>
        <PARAMETER NAME="PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST" VALUE="1"/>
        <PARAMETER NAME="PSU__MAXIGP0__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__USE__M_AXI_GP1" VALUE="1"/>
        <PARAMETER NAME="PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST" VALUE="1"/>
        <PARAMETER NAME="PSU__MAXIGP1__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__USE__M_AXI_GP2" VALUE="0"/>
        <PARAMETER NAME="PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST" VALUE="1"/>
        <PARAMETER NAME="PSU__MAXIGP2__DATA_WIDTH" VALUE="32"/>
        <PARAMETER NAME="PSU__USE__S_AXI_ACP" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__S_AXI_GP0" VALUE="1"/>
        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP0" VALUE="0"/>
        <PARAMETER NAME="PSU__SAXIGP0__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__USE__S_AXI_GP1" VALUE="0"/>
        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP1" VALUE="0"/>
        <PARAMETER NAME="PSU__SAXIGP1__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__USE__S_AXI_GP2" VALUE="0"/>
        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP2" VALUE="0"/>
        <PARAMETER NAME="PSU__SAXIGP2__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__USE__S_AXI_GP3" VALUE="0"/>
        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP3" VALUE="0"/>
        <PARAMETER NAME="PSU__SAXIGP3__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__USE__S_AXI_GP4" VALUE="0"/>
        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP4" VALUE="0"/>
        <PARAMETER NAME="PSU__SAXIGP4__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__USE__S_AXI_GP5" VALUE="0"/>
        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP5" VALUE="0"/>
        <PARAMETER NAME="PSU__SAXIGP5__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__USE__S_AXI_GP6" VALUE="0"/>
        <PARAMETER NAME="PSU__USE_DIFF_RW_CLK_GP6" VALUE="0"/>
        <PARAMETER NAME="PSU__SAXIGP6__DATA_WIDTH" VALUE="128"/>
        <PARAMETER NAME="PSU__USE__S_AXI_ACE" VALUE="0"/>
        <PARAMETER NAME="PSU__TRACE_PIPELINE_WIDTH" VALUE="8"/>
        <PARAMETER NAME="PSU__EN_EMIO_TRACE" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__AUDIO" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__VIDEO" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__PROC_EVENT_BUS" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__FTM" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__CROSS_TRIGGER" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__CTI_IN_0" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__CTI_IN_1" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__CTI_IN_2" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__CTI_IN_3" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__CTI_OUT_0" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__CTI_OUT_1" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__CTI_OUT_2" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__CTI_OUT_3" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__GPO" VALUE="0"/>
        <PARAMETER NAME="PSU__FTM__GPI" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__GDMA" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__IRQ" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__IRQ0" VALUE="1"/>
        <PARAMETER NAME="PSU__USE__IRQ1" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__CLK0" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__CLK1" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__CLK2" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__CLK3" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__RST0" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__RST1" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__RST2" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__RST3" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__FABRIC__RST" VALUE="1"/>
        <PARAMETER NAME="PSU__USE__RTC" VALUE="0"/>
        <PARAMETER NAME="PSU__PRESET_APPLIED" VALUE="1"/>
        <PARAMETER NAME="PSU__USE__EVENT_RPU" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__APU_LEGACY_INTERRUPT" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__RPU_LEGACY_INTERRUPT" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__STM" VALUE="0"/>
        <PARAMETER NAME="PSU__USE__DEBUG__TEST" VALUE="0"/>
        <PARAMETER NAME="PSU__HIGH_ADDRESS__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__DDR_HIGH_ADDRESS_GUI_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__EXPAND__LOWER_LPS_SLAVES" VALUE="0"/>
        <PARAMETER NAME="PSU__EXPAND__CORESIGHT" VALUE="0"/>
        <PARAMETER NAME="PSU__EXPAND__GIC" VALUE="0"/>
        <PARAMETER NAME="PSU__EXPAND__FPD_SLAVES" VALUE="0"/>
        <PARAMETER NAME="PSU__EXPAND__UPPER_LPS_SLAVES" VALUE="0"/>
        <PARAMETER NAME="PSU_MIO_0_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_0_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_0_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_0_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_0_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_0_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_1_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_1_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_1_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_1_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_1_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_1_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_2_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_2_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_2_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_2_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_2_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_2_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_3_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_3_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_3_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_3_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_3_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_3_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_4_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_4_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_4_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_4_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_4_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_4_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_5_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_5_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_5_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_5_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_5_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_5_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_6_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_6_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_6_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_6_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_6_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_6_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_7_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_7_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_7_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_7_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_7_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_7_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_8_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_8_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_8_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_8_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_8_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_8_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_9_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_9_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_9_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_9_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_9_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_9_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_10_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_10_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_10_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_10_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_10_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_10_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_11_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_11_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_11_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_11_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_11_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_11_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_12_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_12_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_12_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_12_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_12_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_12_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_13_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_13_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_13_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_13_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_13_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_13_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_14_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_14_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_14_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_14_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_14_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_14_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_15_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_15_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_15_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_15_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_15_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_15_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_16_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_16_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_16_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_16_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_16_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_16_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_17_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_17_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_17_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_17_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_17_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_17_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_18_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_18_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_18_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_18_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_18_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_18_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_19_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_19_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_19_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_19_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_19_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_19_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_20_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_20_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_20_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_20_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_20_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_20_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_21_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_21_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_21_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_21_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_21_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_21_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_22_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_22_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_22_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_22_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_22_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_22_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_23_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_23_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_23_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_23_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_23_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_23_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_24_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_24_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_24_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_24_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_24_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_24_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_25_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_25_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_25_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_25_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_25_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_25_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_26_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_26_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_26_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_26_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_26_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_26_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_27_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_27_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_27_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_27_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_27_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_27_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_28_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_28_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_28_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_28_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_28_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_28_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_29_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_29_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_29_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_29_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_29_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_29_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_30_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_30_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_30_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_30_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_30_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_30_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_31_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_31_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_31_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_31_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_31_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_31_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_32_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_32_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_32_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_32_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_32_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_32_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_33_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_33_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_33_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_33_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_33_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_33_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_34_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_34_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_34_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_34_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_34_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_34_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_35_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_35_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_35_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_35_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_35_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_35_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_36_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_36_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_36_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_36_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_36_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_36_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_37_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_37_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_37_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_37_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_37_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_37_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_38_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_38_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_38_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_38_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_38_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_38_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_39_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_39_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_39_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_39_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_39_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_39_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_40_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_40_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_40_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_40_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_40_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_40_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_41_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_41_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_41_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_41_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_41_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_41_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_42_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_42_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_42_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_42_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_42_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_42_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_43_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_43_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_43_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_43_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_43_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_43_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_44_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_44_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_44_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_44_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_44_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_44_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_45_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_45_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_45_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_45_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_45_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_45_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_46_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_46_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_46_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_46_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_46_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_46_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_47_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_47_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_47_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_47_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_47_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_47_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_48_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_48_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_48_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_48_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_48_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_48_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_49_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_49_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_49_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_49_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_49_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_49_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_50_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_50_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_50_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_50_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_50_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_50_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_51_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_51_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_51_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_51_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_51_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_51_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_52_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_52_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_52_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_52_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_52_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_52_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_53_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_53_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_53_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_53_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_53_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_53_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_54_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_54_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_54_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_54_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_54_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_54_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_55_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_55_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_55_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_55_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_55_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_55_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_56_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_56_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_56_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_56_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_56_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_56_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_57_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_57_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_57_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_57_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_57_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_57_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_58_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_58_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_58_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_58_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_58_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_58_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_59_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_59_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_59_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_59_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_59_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_59_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_60_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_60_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_60_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_60_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_60_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_60_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_61_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_61_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_61_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_61_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_61_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_61_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_62_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_62_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_62_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_62_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_62_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_62_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_63_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_63_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_63_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_63_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_63_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_63_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_MIO_64_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_64_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_64_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_64_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_64_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_64_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_65_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_65_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_65_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_65_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_65_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_65_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_66_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_66_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_66_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_66_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_66_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_66_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_67_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_67_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_67_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_67_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_67_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_67_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_68_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_68_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_68_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_68_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_68_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_68_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_69_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_69_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_69_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_69_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_69_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_69_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_70_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_70_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_70_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_70_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_70_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_70_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_71_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_71_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_71_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_71_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_71_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_71_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_72_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_72_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_72_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_72_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_72_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_72_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_73_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_73_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_73_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_73_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_73_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_73_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_74_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_74_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_74_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_74_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_74_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_74_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_75_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_75_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_75_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_75_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_75_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_75_DIRECTION" VALUE="in"/>
        <PARAMETER NAME="PSU_MIO_76_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_76_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_76_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_76_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_76_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_76_DIRECTION" VALUE="out"/>
        <PARAMETER NAME="PSU_MIO_77_PULLUPDOWN" VALUE="pullup"/>
        <PARAMETER NAME="PSU_MIO_77_DRIVE_STRENGTH" VALUE="12"/>
        <PARAMETER NAME="PSU_MIO_77_POLARITY" VALUE="Default"/>
        <PARAMETER NAME="PSU_MIO_77_INPUT_TYPE" VALUE="cmos"/>
        <PARAMETER NAME="PSU_MIO_77_SLEW" VALUE="fast"/>
        <PARAMETER NAME="PSU_MIO_77_DIRECTION" VALUE="inout"/>
        <PARAMETER NAME="PSU_BANK_0_IO_STANDARD" VALUE="LVCMOS18"/>
        <PARAMETER NAME="PSU_BANK_1_IO_STANDARD" VALUE="LVCMOS18"/>
        <PARAMETER NAME="PSU_BANK_2_IO_STANDARD" VALUE="LVCMOS18"/>
        <PARAMETER NAME="PSU_BANK_3_IO_STANDARD" VALUE="LVCMOS33"/>
        <PARAMETER NAME="PSU__CRF_APB__APLL_CTRL__FRACDATA" VALUE="0.000000"/>
        <PARAMETER NAME="PSU__CRF_APB__VPLL_CTRL__FRACDATA" VALUE="0.000000"/>
        <PARAMETER NAME="PSU__CRF_APB__DPLL_CTRL__FRACDATA" VALUE="0.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__IOPLL_CTRL__FRACDATA" VALUE="0.000000"/>
        <PARAMETER NAME="PSU__CRL_APB__RPLL_CTRL__FRACDATA" VALUE="0.000000"/>
        <PARAMETER NAME="PSU__CRF_APB__DPLL_CTRL__DIV2" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__APLL_CTRL__DIV2" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__VPLL_CTRL__DIV2" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__IOPLL_CTRL__DIV2" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__RPLL_CTRL__DIV2" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__APLL_CTRL__FBDIV" VALUE="72"/>
        <PARAMETER NAME="PSU__CRF_APB__DPLL_CTRL__FBDIV" VALUE="64"/>
        <PARAMETER NAME="PSU__CRF_APB__VPLL_CTRL__FBDIV" VALUE="90"/>
        <PARAMETER NAME="PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRF_APB__ACPU_CTRL__DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0" VALUE="5"/>
        <PARAMETER NAME="PSU__DISPLAYPORT__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__DISPLAYPORT__LANE0__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__DISPLAYPORT__LANE0__IO" VALUE="GT Lane1"/>
        <PARAMETER NAME="PSU__DISPLAYPORT__LANE1__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__DISPLAYPORT__LANE1__IO" VALUE="GT Lane0"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__APM_CTRL__DIVISOR0" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0" VALUE="5"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0" VALUE="14"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__DDR_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI3_REF__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI4_REF__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI5_REF__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__SATA__PERIPHERAL__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__SATA__LANE0__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__SATA__LANE0__IO" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__SATA__LANE1__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__SATA__LANE1__IO" VALUE="GT Lane3"/>
        <PARAMETER NAME="PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0" VALUE="50"/>
        <PARAMETER NAME="PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0" VALUE="4"/>
        <PARAMETER NAME="PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0" VALUE="4"/>
        <PARAMETER NAME="PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0" VALUE="30"/>
        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__AFI6__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0" VALUE="25"/>
        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1" VALUE="3"/>
        <PARAMETER NAME="PSU_USB3__DUAL_CLOCK_ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__USB3__ENABLE" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__USE__CLK" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0" VALUE="5"/>
        <PARAMETER NAME="PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0" VALUE="-1"/>
        <PARAMETER NAME="PSU__CRF_APB__GTGREF0__ENABLE" VALUE="NA"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRL_APB__IOPLL_CTRL__FBDIV" VALUE="90"/>
        <PARAMETER NAME="PSU__CRL_APB__RPLL_CTRL__FBDIV" VALUE="45"/>
        <PARAMETER NAME="PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0" VALUE="2"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0" VALUE="12"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0" VALUE="12"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0" VALUE="12"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0" VALUE="12"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0" VALUE="12"/>
        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0" VALUE="7"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0" VALUE="8"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0" VALUE="7"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0" VALUE="7"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__PCAP_CTRL__DIVISOR0" VALUE="8"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0" VALUE="6"/>
        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0" VALUE="15"/>
        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1" VALUE="1"/>
        <PARAMETER NAME="PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0" VALUE="3"/>
        <PARAMETER NAME="PSU__CRF_APB__APLL_CTRL__SRCSEL" VALUE="PSS_REF_CLK"/>
        <PARAMETER NAME="PSU__CRF_APB__DPLL_CTRL__SRCSEL" VALUE="PSS_REF_CLK"/>
        <PARAMETER NAME="PSU__CRF_APB__VPLL_CTRL__SRCSEL" VALUE="PSS_REF_CLK"/>
        <PARAMETER NAME="PSU__CRF_APB__ACPU_CTRL__SRCSEL" VALUE="APLL"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__APM_CTRL__SRCSEL" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL" VALUE="VPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__DDR_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__GPU_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__SATA_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__PL0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__PL1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__PL2_REF_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__PL3_REF_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL" VALUE="APLL"/>
        <PARAMETER NAME="PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL" VALUE="APLL"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL" VALUE="DPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL" VALUE="NA"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__IOPLL_CTRL__SRCSEL" VALUE="PSS_REF_CLK"/>
        <PARAMETER NAME="PSU__CRL_APB__RPLL_CTRL__SRCSEL" VALUE="PSS_REF_CLK"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__UART1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL" VALUE="RPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__CPU_R5_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL" VALUE="SysOsc"/>
        <PARAMETER NAME="PSU__CRL_APB__PCAP_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__DLL_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL" VALUE="IOPLL"/>
        <PARAMETER NAME="PSU__IOU_SLCR__WDT_CLK_SEL__SELECT" VALUE="APB"/>
        <PARAMETER NAME="PSU__FPD_SLCR__WDT_CLK_SEL__SELECT" VALUE="APB"/>
        <PARAMETER NAME="PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL" VALUE="APB"/>
        <PARAMETER NAME="PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL" VALUE="APB"/>
        <PARAMETER NAME="PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL" VALUE="APB"/>
        <PARAMETER NAME="PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL" VALUE="APB"/>
        <PARAMETER NAME="PSU__CRF_APB__APLL_FRAC_CFG__ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__ACPU__FRAC_ENABLED" VALUE="0"/>
        <PARAMETER NAME="PSU__OVERRIDE__BASIC_CLOCK" VALUE="0"/>
        <PARAMETER NAME="PSU__DLL__ISUSED" VALUE="1"/>
        <PARAMETER NAME="PSU__PL_CLK0_BUF" VALUE="TRUE"/>
        <PARAMETER NAME="PSU__PL_CLK1_BUF" VALUE="FALSE"/>
        <PARAMETER NAME="PSU__PL_CLK2_BUF" VALUE="FALSE"/>
        <PARAMETER NAME="PSU__PL_CLK3_BUF" VALUE="FALSE"/>
        <PARAMETER NAME="PSU__CRF_APB__APLL_CTRL__FRACFREQ" VALUE="27.138"/>
        <PARAMETER NAME="PSU__CRF_APB__VPLL_CTRL__FRACFREQ" VALUE="27.138"/>
        <PARAMETER NAME="PSU__CRF_APB__DPLL_CTRL__FRACFREQ" VALUE="27.138"/>
        <PARAMETER NAME="PSU__CRL_APB__IOPLL_CTRL__FRACFREQ" VALUE="27.138"/>
        <PARAMETER NAME="PSU__CRL_APB__RPLL_CTRL__FRACFREQ" VALUE="27.138"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC0__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC1__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC2__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC3__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__WDT0__ACT_FREQMHZ" VALUE="99.999001"/>
        <PARAMETER NAME="PSU__FPD_SLCR__WDT1__ACT_FREQMHZ" VALUE="99.999001"/>
        <PARAMETER NAME="PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ" VALUE="1199.988037"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
        <PARAMETER NAME="PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ" VALUE="299.997009"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ" VALUE="24.999750"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ" VALUE="26.785446"/>
        <PARAMETER NAME="PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ" VALUE="533.328003"/>
        <PARAMETER NAME="PSU__DDR__INTERFACE__FREQMHZ" VALUE="533.500"/>
        <PARAMETER NAME="PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ" VALUE="0"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
        <PARAMETER NAME="PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
        <PARAMETER NAME="PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ" VALUE="1.999980"/>
        <PARAMETER NAME="PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ" VALUE="599.994019"/>
        <PARAMETER NAME="PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ" VALUE="599.994019"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ" VALUE="533.328003"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
        <PARAMETER NAME="PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ" VALUE="-1"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ" VALUE="125"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ" VALUE="125"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ" VALUE="125"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ" VALUE="124.998749"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ" VALUE="124.998749"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ" VALUE="187.498123"/>
        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
        <PARAMETER NAME="PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ" VALUE="214"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ" VALUE="214"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ" VALUE="1000"/>
        <PARAMETER NAME="PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ" VALUE="499.994995"/>
        <PARAMETER NAME="PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
        <PARAMETER NAME="PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ" VALUE="180"/>
        <PARAMETER NAME="PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ" VALUE="187.498123"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ" VALUE="499.994995"/>
        <PARAMETER NAME="PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ" VALUE="249.997498"/>
        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ" VALUE="499.994995"/>
        <PARAMETER NAME="PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ" VALUE="1499.984985"/>
        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ" VALUE="49.999500"/>
        <PARAMETER NAME="PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ" VALUE="99.999001"/>
        <PARAMETER NAME="PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ" VALUE="19.999800"/>
        <PARAMETER NAME="PSU__CRF_APB__ACPU_CTRL__FREQMHZ" VALUE="1200"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRF_APB__APM_CTRL__FREQMHZ" VALUE="1"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ" VALUE="300"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ" VALUE="25"/>
        <PARAMETER NAME="PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ" VALUE="27"/>
        <PARAMETER NAME="PSU__CRF_APB__DDR_CTRL__FREQMHZ" VALUE="1067"/>
        <PARAMETER NAME="PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ" VALUE="667"/>
        <PARAMETER NAME="PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ" VALUE="2"/>
        <PARAMETER NAME="PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ" VALUE="600"/>
        <PARAMETER NAME="PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ" VALUE="600"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ" VALUE="533.33"/>
        <PARAMETER NAME="PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ" VALUE="-1"/>
        <PARAMETER NAME="PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ" VALUE="125"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ" VALUE="125"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ" VALUE="125"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ" VALUE="125"/>
        <PARAMETER NAME="PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ" VALUE="125"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ" VALUE="1000"/>
        <PARAMETER NAME="PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ" VALUE="180"/>
        <PARAMETER NAME="PSU__CRL_APB__PCAP_CTRL__FREQMHZ" VALUE="200"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ" VALUE="250"/>
        <PARAMETER NAME="PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ" VALUE="1500"/>
        <PARAMETER NAME="PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ" VALUE="50"/>
        <PARAMETER NAME="PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ" VALUE="100"/>
        <PARAMETER NAME="PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ" VALUE="500"/>
        <PARAMETER NAME="PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ" VALUE="20"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC0__FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC1__FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC2__FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__TTC3__FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__IOU_SLCR__WDT0__FREQMHZ" VALUE="99.999001"/>
        <PARAMETER NAME="PSU__FPD_SLCR__WDT1__FREQMHZ" VALUE="99.999001"/>
        <PARAMETER NAME="PSU__LPD_SLCR__CSUPMU__FREQMHZ" VALUE="100.000000"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_0__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_1__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_2__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_3__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_4__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_5__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_6__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_7__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_8__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_9__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_10__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_11__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_12__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_0__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_1__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_2__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_3__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_4__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_5__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_6__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_7__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_8__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_9__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_10__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_11__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__CSU__CSU_TAMPER_12__RESPONSE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__GEN_IPI_0__MASTER" VALUE="APU"/>
        <PARAMETER NAME="PSU__GEN_IPI_1__MASTER" VALUE="RPU0"/>
        <PARAMETER NAME="PSU__GEN_IPI_2__MASTER" VALUE="RPU1"/>
        <PARAMETER NAME="PSU__GEN_IPI_3__MASTER" VALUE="PMU"/>
        <PARAMETER NAME="PSU__GEN_IPI_4__MASTER" VALUE="PMU"/>
        <PARAMETER NAME="PSU__GEN_IPI_5__MASTER" VALUE="PMU"/>
        <PARAMETER NAME="PSU__GEN_IPI_6__MASTER" VALUE="PMU"/>
        <PARAMETER NAME="PSU__GEN_IPI_7__MASTER" VALUE="NONE"/>
        <PARAMETER NAME="PSU__GEN_IPI_8__MASTER" VALUE="NONE"/>
        <PARAMETER NAME="PSU__GEN_IPI_9__MASTER" VALUE="NONE"/>
        <PARAMETER NAME="PSU__GEN_IPI_10__MASTER" VALUE="NONE"/>
        <PARAMETER NAME="PSU__GEN_IPI__TRUSTZONE" VALUE="&lt;Select>"/>
        <PARAMETER NAME="PSU__IRQ_P2F_RPU_PERMON__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_OCM_ERR__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_LPD_APB__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_NAND__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_QSPI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_GPIO__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_I2C0__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_I2C1__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_SPI0__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_SPI1__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_UART0__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_UART1__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_CAN0__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_CAN1__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_LPD_APM__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_RTC_ALARM__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_RTC_SECONDS__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_CLKMON__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_PL_IPI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_RPU_IPI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_IPI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC0__INT0" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC0__INT1" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC0__INT2" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC1__INT0" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC1__INT1" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC1__INT2" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC2__INT0" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC2__INT1" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC2__INT2" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC3__INT0" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC3__INT1" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_TTC3__INT2" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_SDIO0__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_SDIO1__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_SDIO0_WAKE__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_SDIO1_WAKE__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_LP_WDT__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_CSUPMU_WDT__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ATB_LPD__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_AIB_AXI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_AMS__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT0__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT0_WAKEUP__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT1__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT1_WAKEUP__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT2__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT2_WAKEUP__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT3__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ENT3_WAKEUP__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_USB3_ENDPOINT__INT0" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_USB3_OTG__INT0" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_USB3_ENDPOINT__INT1" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_USB3_OTG__INT1" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_ADMA_CHAN__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_CSU__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_CSU_DMA__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_EFUSE__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_XMPU_LPD__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_DDR_SS__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_FP_WDT__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_PCIE_MSI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_PCIE_LEGACY__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_PCIE_DMA__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_PCIE_MSC__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_DPORT__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_FPD_APB__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_FPD_ATB_ERR__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_DPDMA__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APM_FPD__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_GDMA_CHAN__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_GPU__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_SATA__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_XMPU_FPD__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_CPUMNT__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_CTI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_PMU__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_COMM__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_L2ERR__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_EXTERR__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F_APU_REGS__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F__INTF_PPD_CCI__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__IRQ_P2F__INTF_FPD_SMMU__INT" VALUE="0"/>
        <PARAMETER NAME="PSU__NUM_F2P0__INTR__INPUTS" VALUE="1"/>
        <PARAMETER NAME="PSU__NUM_F2P1__INTR__INPUTS" VALUE="1"/>
        <PARAMETER NAME="PSU__NUM_FABRIC_RESETS" VALUE="1"/>
        <PARAMETER NAME="PSU__GPIO_EMIO_WIDTH" VALUE="1"/>
        <PARAMETER NAME="PSU__HPM0_FPD__NUM_WRITE_THREADS" VALUE="4"/>
        <PARAMETER NAME="PSU__HPM0_FPD__NUM_READ_THREADS" VALUE="4"/>
        <PARAMETER NAME="PSU__HPM1_FPD__NUM_WRITE_THREADS" VALUE="4"/>
        <PARAMETER NAME="PSU__HPM1_FPD__NUM_READ_THREADS" VALUE="4"/>
        <PARAMETER NAME="PSU__HPM0_LPD__NUM_WRITE_THREADS" VALUE="4"/>
        <PARAMETER NAME="PSU__HPM0_LPD__NUM_READ_THREADS" VALUE="4"/>
        <PARAMETER NAME="PSU__TRISTATE__INVERTED" VALUE="1"/>
        <PARAMETER NAME="PSU__GPIO_EMIO__WIDTH" VALUE="[94:0]"/>
        <PARAMETER NAME="PSU__REPORT__DBGLOG" VALUE="0"/>
        <PARAMETER NAME="IIC0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="IIC1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="QSPI_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="NAND_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="SD0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="SD1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="CAN0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="CAN1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="PJTAG_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="PMU_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="CSU_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="SPI0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="SPI1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="UART0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="UART1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="GPIO_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="SWDT0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="SWDT1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="TRACE_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="TTC0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="TTC1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="TTC2_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="TTC3_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="GEM0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="GEM1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="GEM2_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="GEM3_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="USB0_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="USB1_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="PCIE_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="DP_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="SATA_BOARD_INTERFACE" VALUE="custom"/>
        <PARAMETER NAME="preset" VALUE="None"/>
        <PARAMETER NAME="PSU__SD0_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__SD1_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__QSPI_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM0_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM1_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM2_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM3_ROUTE_THROUGH_FPD" VALUE="0"/>
        <PARAMETER NAME="PSU__RPU_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__PMU_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__CSU_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__USB0_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__USB1_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPDMA0_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPDMA1_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPDMA2_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPDMA3_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPDMA4_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPDMA5_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPDMA6_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__LPDMA7_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__SD0_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__SD1_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__NAND_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__QSPI_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET0__TSU__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET1__TSU__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET2__TSU__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__ENET3__TSU__ENABLE" VALUE="0"/>
        <PARAMETER NAME="PSU__TSU__BUFG_PORT_PAIR" VALUE="0"/>
        <PARAMETER NAME="PSU__TSU__BUFG_PORT_LOOPBACK" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM0_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM1_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM2_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__GEM3_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__AFI0_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__AFI1_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__FPDMASTERS_COHERENCY" VALUE="0"/>
        <PARAMETER NAME="PSU__ENABLE__DDR__REFRESH__SIGNALS" VALUE="0"/>
        <PARAMETER NAME="PSU__M_AXI_GP0__FREQMHZ" VALUE="99.999001"/>
        <PARAMETER NAME="PSU__M_AXI_GP1__FREQMHZ" VALUE="333.25"/>
        <PARAMETER NAME="PSU__M_AXI_GP2__FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PSU__S_AXI_GP0__FREQMHZ" VALUE="99.999001"/>
        <PARAMETER NAME="PSU__S_AXI_GP1__FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PSU__S_AXI_GP2__FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PSU__S_AXI_GP3__FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PSU__S_AXI_GP4__FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PSU__S_AXI_GP5__FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PSU__S_AXI_GP6__FREQMHZ" VALUE="10"/>
        <PARAMETER NAME="PSU_SD1_INTERNAL_BUS_WIDTH" VALUE="8"/>
        <PARAMETER NAME="Component_Name" VALUE="d_1_zynq_ultra_ps_e_0_0"/>
        <PARAMETER NAME="EDK_IPTYPE" VALUE="PERIPHERAL"/>
        <PARAMETER NAME="C_BASEADDR" VALUE="0xC0000000"/>
        <PARAMETER NAME="C_HIGHADDR" VALUE="0xDFFFFFFF"/>
      </PARAMETERS>
      <PORTS>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="maxihpm0_fpd_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="maxigp0_awid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="maxigp0_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="maxigp0_awlen" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="maxigp0_awsize" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="maxigp0_awburst" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_awlock" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="maxigp0_awcache" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="maxigp0_awprot" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_awvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="maxigp0_awuser" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="maxigp0_awready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="maxigp0_wdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="maxigp0_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_wlast" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_wvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp0_wready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="maxigp0_bid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_bid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="maxigp0_bresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp0_bvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_bready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="maxigp0_arid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="maxigp0_araddr" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="maxigp0_arlen" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="maxigp0_arsize" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="maxigp0_arburst" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_arlock" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="maxigp0_arcache" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="maxigp0_arprot" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_arvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="maxigp0_aruser" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" NAME="maxigp0_arready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="maxigp0_rid" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_rid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="maxigp0_rdata" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="maxigp0_rresp" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp0_rlast" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp0_rvalid" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp0_rready" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="maxigp0_awqos" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="maxigp0_arqos" RIGHT="0" SIGIS="undef" SIGNAME="ps8_0_axi_periph_S00_AXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_AXI_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="333250000" DIR="I" NAME="maxihpm1_fpd_aclk" SIGIS="clk" SIGNAME="ddr4_0_c0_ddr4_ui_clk">
          <CONNECTIONS>
            <CONNECTION INSTANCE="ddr4_0" PORT="c0_ddr4_ui_clk"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="maxigp1_awid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_awid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="maxigp1_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="maxigp1_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="maxigp1_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="maxigp1_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp1_awlock" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="maxigp1_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="maxigp1_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp1_awvalid" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="maxigp1_awuser" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awuser">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_awuser"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp1_awready" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="127" NAME="maxigp1_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="maxigp1_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp1_wlast" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp1_wvalid" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp1_wready" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="maxigp1_bid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_bid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_bid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="maxigp1_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp1_bvalid" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp1_bready" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="maxigp1_arid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_arid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="39" NAME="maxigp1_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="7" NAME="maxigp1_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="maxigp1_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="maxigp1_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp1_arlock" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="maxigp1_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="2" NAME="maxigp1_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp1_arvalid" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="15" NAME="maxigp1_aruser" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_aruser">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_aruser"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp1_arready" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="maxigp1_rid" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_rid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_rid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="maxigp1_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="maxigp1_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp1_rlast" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="maxigp1_rvalid" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="maxigp1_rready" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="maxigp1_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="3" NAME="maxigp1_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_1_S00_AXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc_1" PORT="S00_AXI_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="I" NAME="saxihpc0_fpd_aclk" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="pl_clk0"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp0_aruser" SIGIS="undef"/>
        <PORT DIR="I" NAME="saxigp0_awuser" SIGIS="undef"/>
        <PORT DIR="I" LEFT="5" NAME="saxigp0_awid" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="48" NAME="saxigp0_awaddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awaddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awaddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="saxigp0_awlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp0_awsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="saxigp0_awburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp0_awlock" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp0_awcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp0_awprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp0_awvalid" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp0_awready" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="127" NAME="saxigp0_wdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_wdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="15" NAME="saxigp0_wstrb" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wstrb">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_wstrb"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp0_wlast" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_wlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp0_wvalid" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_wvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp0_wready" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_wready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_wready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="5" NAME="saxigp0_bid" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="1" NAME="saxigp0_bresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_bresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_bresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp0_bvalid" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_bvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_bvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp0_bready" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_bready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_bready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="5" NAME="saxigp0_arid" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="I" LEFT="48" NAME="saxigp0_araddr" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_araddr">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_araddr"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="7" NAME="saxigp0_arlen" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arlen">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arlen"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp0_arsize" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arsize">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arsize"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="1" NAME="saxigp0_arburst" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arburst">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arburst"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp0_arlock" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arlock">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arlock"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp0_arcache" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arcache">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arcache"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="2" NAME="saxigp0_arprot" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arprot">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arprot"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp0_arvalid" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp0_arready" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="5" NAME="saxigp0_rid" RIGHT="0" SIGIS="undef"/>
        <PORT DIR="O" LEFT="127" NAME="saxigp0_rdata" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rdata">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_rdata"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" LEFT="1" NAME="saxigp0_rresp" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rresp">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_rresp"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp0_rlast" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rlast">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_rlast"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="saxigp0_rvalid" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rvalid">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_rvalid"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" NAME="saxigp0_rready" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_rready">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_rready"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp0_awqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_awqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_awqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="I" LEFT="3" NAME="saxigp0_arqos" RIGHT="0" SIGIS="undef" SIGNAME="axi_smc_M00_AXI_arqos">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_smc" PORT="M00_AXI_arqos"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="emio_uart1_txd" SIGIS="undef"/>
        <PORT DIR="I" NAME="emio_uart1_rxd" SIGIS="undef"/>
        <PORT DIR="I" LEFT="0" NAME="pl_ps_irq0" RIGHT="0" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="axi_intc_0_irq">
          <CONNECTIONS>
            <CONNECTION INSTANCE="axi_intc_0" PORT="irq"/>
          </CONNECTIONS>
        </PORT>
        <PORT DIR="O" NAME="pl_resetn0" POLARITY="ACTIVE_LOW" SIGIS="rst" SIGNAME="zynq_ultra_ps_e_0_pl_resetn0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="rst_100" PORT="ext_reset_in"/>
            <CONNECTION INSTANCE="rst_adc0" PORT="ext_reset_in"/>
            <CONNECTION INSTANCE="rst_adc0_x2" PORT="ext_reset_in"/>
            <CONNECTION INSTANCE="rst_dac0" PORT="ext_reset_in"/>
            <CONNECTION INSTANCE="rst_dac1" PORT="ext_reset_in"/>
            <CONNECTION INSTANCE="rst_core" PORT="ext_reset_in"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="99999001" DIR="O" NAME="pl_clk0" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk0">
          <CONNECTIONS>
            <CONNECTION INSTANCE="attn_spi" PORT="ext_spi_clk"/>
            <CONNECTION INSTANCE="attn_spi" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="m_axi_s2mm_aclk"/>
            <CONNECTION INSTANCE="axi_dma_avg" PORT="s_axi_lite_aclk"/>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="m_axi_s2mm_aclk"/>
            <CONNECTION INSTANCE="axi_dma_buf" PORT="s_axi_lite_aclk"/>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="m_axi_mm2s_aclk"/>
            <CONNECTION INSTANCE="axi_dma_gen" PORT="s_axi_lite_aclk"/>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="m_axi_s2mm_aclk"/>
            <CONNECTION INSTANCE="axi_dma_mr" PORT="s_axi_lite_aclk"/>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_mm2s_aclk"/>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="m_axi_s2mm_aclk"/>
            <CONNECTION INSTANCE="axi_dma_tproc" PORT="s_axi_lite_aclk"/>
            <CONNECTION INSTANCE="axi_intc_0" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="axi_smc" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="m_axis_aclk"/>
            <CONNECTION INSTANCE="axis_avg_buffer_0" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="m_axis_aclk"/>
            <CONNECTION INSTANCE="axis_avg_buffer_1" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="axis_buffer_ddr_v1_0" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_0" PORT="s_axis_aclk"/>
            <CONNECTION INSTANCE="axis_clk_cnvrt_avg_1" PORT="s_axis_aclk"/>
            <CONNECTION INSTANCE="axis_readout_v2_0" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="axis_readout_v2_1" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s0_axis_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_0" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s0_axis_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_1" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s0_axis_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_2" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s0_axis_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_3" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s0_axis_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_4" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s0_axis_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_5" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s0_axis_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_6" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s0_axis_aclk"/>
            <CONNECTION INSTANCE="axis_signal_gen_v6_7" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_switch_avg" PORT="s_axi_ctrl_aclk"/>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_switch_buf" PORT="s_axi_ctrl_aclk"/>
            <CONNECTION INSTANCE="axis_switch_ddr" PORT="s_axi_ctrl_aclk"/>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="aclk"/>
            <CONNECTION INSTANCE="axis_switch_gen" PORT="s_axi_ctrl_aclk"/>
            <CONNECTION INSTANCE="axis_switch_mr" PORT="s_axi_ctrl_aclk"/>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="ext_spi_clk"/>
            <CONNECTION INSTANCE="dac_bias_spi" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="lo_spi" PORT="ext_spi_clk"/>
            <CONNECTION INSTANCE="lo_spi" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="m00_axis_aclk"/>
            <CONNECTION INSTANCE="mr_buffer_et_0" PORT="s00_axi_aclk"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M00_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M01_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M02_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M03_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M04_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M05_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M06_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M07_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M08_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M09_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M10_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M11_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M12_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M13_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M14_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M15_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M16_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M17_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M18_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M19_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M20_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M21_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M22_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M23_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M24_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M25_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M26_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M27_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M28_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M29_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="M30_ACLK"/>
            <CONNECTION INSTANCE="ps8_0_axi_periph" PORT="S00_ACLK"/>
            <CONNECTION INSTANCE="psf_spi" PORT="ext_spi_clk"/>
            <CONNECTION INSTANCE="psf_spi" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="qick_processor_0" PORT="ps_clk_i"/>
            <CONNECTION INSTANCE="rst_100" PORT="slowest_sync_clk"/>
            <CONNECTION INSTANCE="usp_rf_data_converter_0" PORT="s_axi_aclk"/>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="maxihpm0_fpd_aclk"/>
            <CONNECTION INSTANCE="zynq_ultra_ps_e_0" PORT="saxihpc0_fpd_aclk"/>
            <CONNECTION INSTANCE="clk_core" PORT="clk_in1"/>
          </CONNECTIONS>
        </PORT>
        <PORT CLKFREQUENCY="1999980" DIR="O" NAME="pl_clk1" SIGIS="clk" SIGNAME="zynq_ultra_ps_e_0_pl_clk1">
          <CONNECTIONS>
            <CONNECTION INSTANCE="External_Ports" PORT="PWR_SYNC"/>
          </CONNECTIONS>
        </PORT>
      </PORTS>
      <BUSINTERFACES>
        <BUSINTERFACE BUSNAME="zynq_ultra_ps_e_0_M_AXI_HPM0_FPD" DATAWIDTH="128" NAME="M_AXI_HPM0_FPD" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="16"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="40"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="16"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="16"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="4"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="4"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWID" PHYSICAL="maxigp0_awid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="maxigp0_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="maxigp0_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="maxigp0_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="maxigp0_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="maxigp0_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="maxigp0_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="maxigp0_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="maxigp0_awvalid"/>
            <PORTMAP LOGICAL="AWUSER" PHYSICAL="maxigp0_awuser"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="maxigp0_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="maxigp0_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="maxigp0_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="maxigp0_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="maxigp0_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="maxigp0_wready"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="maxigp0_bid"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="maxigp0_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="maxigp0_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="maxigp0_bready"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="maxigp0_arid"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="maxigp0_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="maxigp0_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="maxigp0_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="maxigp0_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="maxigp0_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="maxigp0_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="maxigp0_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="maxigp0_arvalid"/>
            <PORTMAP LOGICAL="ARUSER" PHYSICAL="maxigp0_aruser"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="maxigp0_arready"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="maxigp0_rid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="maxigp0_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="maxigp0_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="maxigp0_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="maxigp0_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="maxigp0_rready"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="maxigp0_awqos"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="maxigp0_arqos"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="zynq_ultra_ps_e_0_M_AXI_HPM1_FPD" DATAWIDTH="128" NAME="M_AXI_HPM1_FPD" TYPE="MASTER" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="8"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="333250000"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="16"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="40"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="16"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="16"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="1"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="256"/>
          <PARAMETER NAME="PHASE" VALUE="0.00"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_ddr4_0_0_c0_ddr4_ui_clk"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="4"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="4"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="AWID" PHYSICAL="maxigp1_awid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="maxigp1_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="maxigp1_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="maxigp1_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="maxigp1_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="maxigp1_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="maxigp1_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="maxigp1_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="maxigp1_awvalid"/>
            <PORTMAP LOGICAL="AWUSER" PHYSICAL="maxigp1_awuser"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="maxigp1_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="maxigp1_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="maxigp1_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="maxigp1_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="maxigp1_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="maxigp1_wready"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="maxigp1_bid"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="maxigp1_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="maxigp1_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="maxigp1_bready"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="maxigp1_arid"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="maxigp1_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="maxigp1_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="maxigp1_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="maxigp1_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="maxigp1_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="maxigp1_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="maxigp1_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="maxigp1_arvalid"/>
            <PORTMAP LOGICAL="ARUSER" PHYSICAL="maxigp1_aruser"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="maxigp1_arready"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="maxigp1_rid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="maxigp1_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="maxigp1_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="maxigp1_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="maxigp1_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="maxigp1_rready"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="maxigp1_awqos"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="maxigp1_arqos"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="axi_smc_M00_AXI" DATAWIDTH="128" NAME="S_AXI_HPC0_FPD" TYPE="SLAVE" VLNV="xilinx.com:interface:aximm:1.0">
          <PARAMETER NAME="NUM_WRITE_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="NUM_READ_OUTSTANDING" VALUE="16"/>
          <PARAMETER NAME="DATA_WIDTH" VALUE="128"/>
          <PARAMETER NAME="PROTOCOL" VALUE="AXI4"/>
          <PARAMETER NAME="FREQ_HZ" VALUE="99999001"/>
          <PARAMETER NAME="ID_WIDTH" VALUE="6"/>
          <PARAMETER NAME="ADDR_WIDTH" VALUE="49"/>
          <PARAMETER NAME="AWUSER_WIDTH" VALUE="1"/>
          <PARAMETER NAME="ARUSER_WIDTH" VALUE="1"/>
          <PARAMETER NAME="WUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="RUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="BUSER_WIDTH" VALUE="0"/>
          <PARAMETER NAME="READ_WRITE_MODE" VALUE="READ_WRITE"/>
          <PARAMETER NAME="HAS_BURST" VALUE="1"/>
          <PARAMETER NAME="HAS_LOCK" VALUE="1"/>
          <PARAMETER NAME="HAS_PROT" VALUE="1"/>
          <PARAMETER NAME="HAS_CACHE" VALUE="1"/>
          <PARAMETER NAME="HAS_QOS" VALUE="1"/>
          <PARAMETER NAME="HAS_REGION" VALUE="0"/>
          <PARAMETER NAME="HAS_WSTRB" VALUE="1"/>
          <PARAMETER NAME="HAS_BRESP" VALUE="1"/>
          <PARAMETER NAME="HAS_RRESP" VALUE="1"/>
          <PARAMETER NAME="SUPPORTS_NARROW_BURST" VALUE="0"/>
          <PARAMETER NAME="MAX_BURST_LENGTH" VALUE="32"/>
          <PARAMETER NAME="PHASE" VALUE="0.0"/>
          <PARAMETER NAME="CLK_DOMAIN" VALUE="d_1_zynq_ultra_ps_e_0_0_pl_clk0"/>
          <PARAMETER NAME="NUM_READ_THREADS" VALUE="1"/>
          <PARAMETER NAME="NUM_WRITE_THREADS" VALUE="1"/>
          <PARAMETER NAME="RUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="WUSER_BITS_PER_BYTE" VALUE="0"/>
          <PARAMETER NAME="INSERT_VIP" VALUE="0"/>
          <PORTMAPS>
            <PORTMAP LOGICAL="ARUSER" PHYSICAL="saxigp0_aruser"/>
            <PORTMAP LOGICAL="AWUSER" PHYSICAL="saxigp0_awuser"/>
            <PORTMAP LOGICAL="AWID" PHYSICAL="saxigp0_awid"/>
            <PORTMAP LOGICAL="AWADDR" PHYSICAL="saxigp0_awaddr"/>
            <PORTMAP LOGICAL="AWLEN" PHYSICAL="saxigp0_awlen"/>
            <PORTMAP LOGICAL="AWSIZE" PHYSICAL="saxigp0_awsize"/>
            <PORTMAP LOGICAL="AWBURST" PHYSICAL="saxigp0_awburst"/>
            <PORTMAP LOGICAL="AWLOCK" PHYSICAL="saxigp0_awlock"/>
            <PORTMAP LOGICAL="AWCACHE" PHYSICAL="saxigp0_awcache"/>
            <PORTMAP LOGICAL="AWPROT" PHYSICAL="saxigp0_awprot"/>
            <PORTMAP LOGICAL="AWVALID" PHYSICAL="saxigp0_awvalid"/>
            <PORTMAP LOGICAL="AWREADY" PHYSICAL="saxigp0_awready"/>
            <PORTMAP LOGICAL="WDATA" PHYSICAL="saxigp0_wdata"/>
            <PORTMAP LOGICAL="WSTRB" PHYSICAL="saxigp0_wstrb"/>
            <PORTMAP LOGICAL="WLAST" PHYSICAL="saxigp0_wlast"/>
            <PORTMAP LOGICAL="WVALID" PHYSICAL="saxigp0_wvalid"/>
            <PORTMAP LOGICAL="WREADY" PHYSICAL="saxigp0_wready"/>
            <PORTMAP LOGICAL="BID" PHYSICAL="saxigp0_bid"/>
            <PORTMAP LOGICAL="BRESP" PHYSICAL="saxigp0_bresp"/>
            <PORTMAP LOGICAL="BVALID" PHYSICAL="saxigp0_bvalid"/>
            <PORTMAP LOGICAL="BREADY" PHYSICAL="saxigp0_bready"/>
            <PORTMAP LOGICAL="ARID" PHYSICAL="saxigp0_arid"/>
            <PORTMAP LOGICAL="ARADDR" PHYSICAL="saxigp0_araddr"/>
            <PORTMAP LOGICAL="ARLEN" PHYSICAL="saxigp0_arlen"/>
            <PORTMAP LOGICAL="ARSIZE" PHYSICAL="saxigp0_arsize"/>
            <PORTMAP LOGICAL="ARBURST" PHYSICAL="saxigp0_arburst"/>
            <PORTMAP LOGICAL="ARLOCK" PHYSICAL="saxigp0_arlock"/>
            <PORTMAP LOGICAL="ARCACHE" PHYSICAL="saxigp0_arcache"/>
            <PORTMAP LOGICAL="ARPROT" PHYSICAL="saxigp0_arprot"/>
            <PORTMAP LOGICAL="ARVALID" PHYSICAL="saxigp0_arvalid"/>
            <PORTMAP LOGICAL="ARREADY" PHYSICAL="saxigp0_arready"/>
            <PORTMAP LOGICAL="RID" PHYSICAL="saxigp0_rid"/>
            <PORTMAP LOGICAL="RDATA" PHYSICAL="saxigp0_rdata"/>
            <PORTMAP LOGICAL="RRESP" PHYSICAL="saxigp0_rresp"/>
            <PORTMAP LOGICAL="RLAST" PHYSICAL="saxigp0_rlast"/>
            <PORTMAP LOGICAL="RVALID" PHYSICAL="saxigp0_rvalid"/>
            <PORTMAP LOGICAL="RREADY" PHYSICAL="saxigp0_rready"/>
            <PORTMAP LOGICAL="AWQOS" PHYSICAL="saxigp0_awqos"/>
            <PORTMAP LOGICAL="ARQOS" PHYSICAL="saxigp0_arqos"/>
          </PORTMAPS>
        </BUSINTERFACE>
        <BUSINTERFACE BUSNAME="__NOC__" NAME="UART_1" TYPE="INITIATOR" VLNV="xilinx.com:interface:uart:1.0">
          <PORTMAPS>
            <PORTMAP LOGICAL="TxD" PHYSICAL="emio_uart1_txd"/>
            <PORTMAP LOGICAL="RxD" PHYSICAL="emio_uart1_rxd"/>
          </PORTMAPS>
        </BUSINTERFACE>
      </BUSINTERFACES>
      <MEMORYMAP>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA0240000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0240FFF" INSTANCE="axi_dma_avg" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_LITE"/>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA0241000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0241FFF" INSTANCE="axi_dma_buf" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_LITE"/>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA0242000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0242FFF" INSTANCE="axi_dma_gen" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_LITE"/>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA0243000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0243FFF" INSTANCE="axi_dma_tproc" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_LITE"/>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0xA0244000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0244FFF" INSTANCE="axis_avg_buffer_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0xA0245000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0245FFF" INSTANCE="axis_avg_buffer_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0xA0246000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0246FFF" INSTANCE="axis_readout_v2_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0xA0247000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0247FFF" INSTANCE="axis_readout_v2_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0xA0248000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0248FFF" INSTANCE="axis_signal_gen_v6_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0xA0249000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0249FFF" INSTANCE="axis_signal_gen_v6_1" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0xA024A000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA024AFFF" INSTANCE="axis_signal_gen_v6_2" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0xA024B000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA024BFFF" INSTANCE="axis_signal_gen_v6_3" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0xA024C000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA024CFFF" INSTANCE="axis_signal_gen_v6_4" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0xA024D000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA024DFFF" INSTANCE="axis_signal_gen_v6_5" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0xA024E000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA024EFFF" INSTANCE="axis_signal_gen_v6_6" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA024F000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA024FFFF" INSTANCE="axis_switch_avg" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_CTRL"/>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA0250000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0250FFF" INSTANCE="axis_switch_buf" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_CTRL"/>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA0251000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0251FFF" INSTANCE="axis_switch_gen" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_CTRL"/>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA0252000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0252FFF" INSTANCE="axi_dma_mr" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_LITE"/>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA0253000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0253FFF" INSTANCE="axi_intc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0xA0254000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0254FFF" INSTANCE="axis_buffer_ddr_v1_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA0255000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0255FFF" INSTANCE="axis_switch_ddr" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_CTRL"/>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA0256000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0256FFF" INSTANCE="axis_switch_mr" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="S_AXI_CTRL"/>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0xA0257000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0257FFF" INSTANCE="mr_buffer_et_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s00_axi"/>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA0258000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0258FFF" INSTANCE="attn_spi" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="AXI_LITE"/>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA0259000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA0259FFF" INSTANCE="dac_bias_spi" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="AXI_LITE"/>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA025A000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA025AFFF" INSTANCE="lo_spi" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="AXI_LITE"/>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA025B000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA025BFFF" INSTANCE="psf_spi" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="AXI_LITE"/>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0xA025C000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA025CFFF" INSTANCE="axis_signal_gen_v6_7" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="reg0" BASENAME="C_BASEADDR" BASEVALUE="0xA025D000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA025DFFF" INSTANCE="qick_processor_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="Reg" BASENAME="C_BASEADDR" BASEVALUE="0xA0280000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0xA02BFFFF" INSTANCE="usp_rf_data_converter_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM0_FPD" MEMTYPE="REGISTER" SLAVEBUSINTERFACE="s_axi"/>
        <MEMRANGE ADDRESSBLOCK="C0_DDR4_ADDRESS_BLOCK" BASENAME="C_BASEADDR" BASEVALUE="0x500000000" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x5FFFFFFFF" INSTANCE="ddr4_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" MASTERBUSINTERFACE="M_AXI_HPM1_FPD" MEMTYPE="MEMORY" SLAVEBUSINTERFACE="C0_DDR4_S_AXI"/>
      </MEMORYMAP>
      <PERIPHERALS>
        <PERIPHERAL INSTANCE="axi_dma_avg"/>
        <PERIPHERAL INSTANCE="axi_dma_buf"/>
        <PERIPHERAL INSTANCE="axi_dma_gen"/>
        <PERIPHERAL INSTANCE="axi_dma_tproc"/>
        <PERIPHERAL INSTANCE="axis_avg_buffer_0"/>
        <PERIPHERAL INSTANCE="axis_avg_buffer_1"/>
        <PERIPHERAL INSTANCE="axis_readout_v2_0"/>
        <PERIPHERAL INSTANCE="axis_readout_v2_1"/>
        <PERIPHERAL INSTANCE="axis_signal_gen_v6_0"/>
        <PERIPHERAL INSTANCE="axis_signal_gen_v6_1"/>
        <PERIPHERAL INSTANCE="axis_signal_gen_v6_2"/>
        <PERIPHERAL INSTANCE="axis_signal_gen_v6_3"/>
        <PERIPHERAL INSTANCE="axis_signal_gen_v6_4"/>
        <PERIPHERAL INSTANCE="axis_signal_gen_v6_5"/>
        <PERIPHERAL INSTANCE="axis_signal_gen_v6_6"/>
        <PERIPHERAL INSTANCE="axis_switch_avg"/>
        <PERIPHERAL INSTANCE="axis_switch_buf"/>
        <PERIPHERAL INSTANCE="axis_switch_gen"/>
        <PERIPHERAL INSTANCE="axi_dma_mr"/>
        <PERIPHERAL INSTANCE="axi_intc_0"/>
        <PERIPHERAL INSTANCE="axis_buffer_ddr_v1_0"/>
        <PERIPHERAL INSTANCE="axis_switch_ddr"/>
        <PERIPHERAL INSTANCE="axis_switch_mr"/>
        <PERIPHERAL INSTANCE="mr_buffer_et_0"/>
        <PERIPHERAL INSTANCE="attn_spi"/>
        <PERIPHERAL INSTANCE="dac_bias_spi"/>
        <PERIPHERAL INSTANCE="lo_spi"/>
        <PERIPHERAL INSTANCE="psf_spi"/>
        <PERIPHERAL INSTANCE="axis_signal_gen_v6_7"/>
        <PERIPHERAL INSTANCE="qick_processor_0"/>
        <PERIPHERAL INSTANCE="usp_rf_data_converter_0"/>
        <PERIPHERAL INSTANCE="ddr4_0"/>
      </PERIPHERALS>
    </MODULE>
  </MODULES>

</EDKSYSTEM>
