for long drive+acquisition at low IF: int4 gens with long envelope buffers readouts with long accumulating buffers QICK configuration: Board: ZCU216 Software version: 0.2.191 Firmware timestamp: Wed Oct 11 12:55:20 2023 Global clocks (MHz): tProcessor 107.520, RF reference 245.760 4 signal generator channels: 0: axis_sg_int4_v1 - tProc output 1, envelope memory 65536 samples DAC tile 2, blk 0, 16-bit DDS, fabric=107.520 MHz, f_dds=430.080 MHz 1: axis_sg_int4_v1 - tProc output 2, envelope memory 65536 samples DAC tile 2, blk 1, 16-bit DDS, fabric=107.520 MHz, f_dds=430.080 MHz 2: axis_sg_int4_v1 - tProc output 3, envelope memory 65536 samples DAC tile 2, blk 2, 16-bit DDS, fabric=107.520 MHz, f_dds=430.080 MHz 3: axis_sg_int4_v1 - tProc output 4, envelope memory 65536 samples DAC tile 2, blk 3, 16-bit DDS, fabric=107.520 MHz, f_dds=430.080 MHz 2 readout channels: 0: axis_readout_v2 - controlled by PYNQ ADC tile 2, blk 0, 32-bit DDS, fabric=107.520 MHz, fs=860.160 MHz maxlen 131072 (avg) 1024 (decimated) triggered by output 0, pin 14, feedback to tProc input 0 1: axis_readout_v2 - controlled by PYNQ ADC tile 2, blk 2, 32-bit DDS, fabric=107.520 MHz, fs=860.160 MHz maxlen 131072 (avg) 1024 (decimated) triggered by output 0, pin 15, feedback to tProc input 1 4 DACs: DAC tile 2, blk 0 is 0_230, on JHC3 DAC tile 2, blk 1 is 1_230, on JHC4 DAC tile 2, blk 2 is 2_230, on JHC3 DAC tile 2, blk 3 is 3_230, on JHC4 2 ADCs: ADC tile 2, blk 0 is 0_226, on JHC7 ADC tile 2, blk 2 is 2_226, on JHC7 8 digital output pins: 0: PMOD0_0_LS (output 0, pin 0) 1: PMOD0_1_LS (output 0, pin 1) 2: PMOD0_2_LS (output 0, pin 2) 3: PMOD0_3_LS (output 0, pin 3) 4: PMOD0_4_LS (output 0, pin 4) 5: PMOD0_5_LS (output 0, pin 5) 6: PMOD0_6_LS (output 0, pin 6) 7: PMOD0_7_LS (output 0, pin 7) tProc axis_tproc64x32_x8: program memory 8192 words, data memory 4096 words external start pin: PMOD1_0_LS DDR4 memory buffer: 1073741824 samples, 128 samples/transfer wired to readouts [0, 1], triggered by output 0, pin 13 MR buffer: 8192 samples, wired to readouts [0, 1], triggered by output 0, pin 12