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"connectedBus": "axis_avg_buffer_0_m2_axis", "port_maps": [ { "logical_port": "TDATA", "physical_pin": { "id": 1, "name": "probe1", "leftBit": 0, "width": 64 } }, { "logical_port": "TLAST", "physical_pin": { "id": 4, "name": "probe4", "leftBit": 0, "width": 1 } }, { "logical_port": "TREADY", "physical_pin": { "id": 3, "name": "probe3", "leftBit": 0, "width": 1 } }, { "logical_port": "TVALID", "physical_pin": { "id": 2, "name": "probe2", "leftBit": 0, "width": 1 } } ] } ], "native_ports": [ { "name": "probe0", "connectedBus": "vect2bits_16_0_dout14", "protocol": "PROBE", "port_maps": [ { "logical_port": "probe0", "physical_pin": { "id": 0, "name": "probe0", "leftBit": 0, "width": 1 } } ] } ] }, { "type": "ILA_V3", "name": "d_1_i/system_ila_1/inst/ila_lib", "spec": "labtools_ila_v6", "ipName": "ila", "core_location": { "user_chain": 1, "slave_index": 1, "bscan_switch_index": 0 }, "uuid": "D4C961B478435D30A512AEFC57A76BEE", "pins": [ { "name": "probe0", "id": 5, "type": "DATA_TRIGGER", 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"d_1_i/system_ila_1/inst/net_slot_0_axis_tdata[9]" }, { "name": "d_1_i/system_ila_1/inst/net_slot_0_axis_tdata[8]" }, { "name": "d_1_i/system_ila_1/inst/net_slot_0_axis_tdata[7]" }, { "name": "d_1_i/system_ila_1/inst/net_slot_0_axis_tdata[6]" }, { "name": "d_1_i/system_ila_1/inst/net_slot_0_axis_tdata[5]" }, { "name": "d_1_i/system_ila_1/inst/net_slot_0_axis_tdata[4]" }, { "name": "d_1_i/system_ila_1/inst/net_slot_0_axis_tdata[3]" }, { "name": "d_1_i/system_ila_1/inst/net_slot_0_axis_tdata[2]" }, { "name": "d_1_i/system_ila_1/inst/net_slot_0_axis_tdata[1]" }, { "name": "d_1_i/system_ila_1/inst/net_slot_0_axis_tdata[0]" } ] } ] }, { "name": "probe2", "id": 7, "type": "DATA_TRIGGER", "direction": "IN", "isVector": false, "leftIndex": 0, "rightIndex": 0, "portIndex": 2, "nets": [ { "name": "d_1_i/system_ila_1/inst/net_slot_0_axis_tvalid", "isBus": false } ] }, { "name": "probe3", "id": 8, "type": "DATA_TRIGGER", "direction": "IN", "isVector": false, "leftIndex": 0, "rightIndex": 0, "portIndex": 3, "nets": [ { "name": "d_1_i/system_ila_1/inst/net_slot_0_axis_tready", "isBus": false } ] }, { "name": "probe4", "id": 9, "type": "DATA_TRIGGER", "direction": "IN", "isVector": false, "leftIndex": 0, "rightIndex": 0, "portIndex": 4, "nets": [ { "name": "d_1_i/system_ila_1/inst/net_slot_0_axis_tlast", "isBus": false } ] } ], "bus_interfaces": [ { "name": "SLOT_0_AXIS", "vlnv": "xilinx.com:interface:axis:1.0", "connectedBus": "axis_clk_cnvrt_avg_0_M_AXIS", "port_maps": [ { "logical_port": "TDATA", "physical_pin": { "id": 6, "name": "probe1", "leftBit": 0, "width": 64 } }, { "logical_port": "TLAST", "physical_pin": { "id": 9, "name": "probe4", "leftBit": 0, "width": 1 } }, { "logical_port": "TREADY", "physical_pin": { "id": 8, "name": "probe3", "leftBit": 0, "width": 1 } }, { "logical_port": "TVALID", "physical_pin": { "id": 7, "name": "probe2", "leftBit": 0, "width": 1 } } ] } ], "native_ports": [ { "name": "probe0", "connectedBus": "vect2bits_16_0_dout14", "protocol": "PROBE", "port_maps": [ { "logical_port": "probe0", "physical_pin": { "id": 5, "name": "probe0", "leftBit": 0, "width": 1 } } ] } ] } ], "parent_nets": [ { "id": 65, "name": "d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/rd2axi_i/Q[0]", "state_reg": [ { "name": "d_1_i/axis_avg_buffer_0/inst/avg_buffer_i/avg_top_i/fifo_i/rd2axi_i/FSM_sequential_current_state_reg[1]", "states": [ { "name": "read_first_st", "val": "01" }, { "name": "read_st", "val": "10" }, { "name": "wait_empty_st", "val": "00" }, { "name": "read_last_st", "val": "11" } ] } ] } ] } ] } }