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%\title[GEANT4/EGS5]{GEANT4/EGS5}

\title{SENSEI DAQ overview}

\author{Sho Uemura}
%\institute{bumming around}
\date[June 17, 2019]

%\titlegraphic{
%\includegraphics[height=0.1\textheight]{SLAC_Logo}\hspace*{4.75cm}~
%\includegraphics[height=0.1\textheight]{partner_logo_v2}
%}

\begin{document}

\begin{frame}
    \titlepage
\end{frame}

\begin{frame}{Overview}
    \begin{center}
        \includegraphics[width=\textwidth]{SENSEI_DAQ-dataflow}
    \end{center}
    \begin{itemize}
        \item The LTA is a single board that replaces the Monsoon system
        \item The core of the DAQ software is the ``daemon'' which communicates to the LTA over the network and writes data to disk: ltaDaemon repo
        \item The daemon is controlled over the network by shell commands: e.g. ``lta set vdd -22'' is aliased to ``echo set vdd -22|nc localhost 8888''
    \end{itemize}
\end{frame}

\begin{frame}{LTA}
    \begin{center}
        \includegraphics[width=\textwidth]{SENSEI_DAQ-LTA}
    \end{center}
    \begin{itemize}
        \item LTAv2 is expected to be the production version
        \item FPGA firmware contains a MicroBlaze soft CPU with embedded software
        \item Not shown: clock distribution and synchronization (for multi-LTA setups --- tested but not yet used)
    \end{itemize}
\end{frame}

\begin{frame}{LTA}
    \begin{center}
        \includegraphics[width=\textwidth]{SENSEI_DAQ-LTA}
    \end{center}
    \begin{itemize}
        \item Current firmware and embedded software: lta-v2-system-firmware, lta-v2-system-software
        \item ``Smart Skipper'' rewrite of the firmware allows for more complex sequencer programs (different number of samples for different regions of the CCD), other enhancements
            \begin{itemize}
                \item VHDL sequencer replaced with a second MicroBlaze CPU
                \item ``Smart Skipper'' firmware and software: lta-v2-sskp-firmware, lta-v2-sskp-ubglobal-software, lta-v2-sskp-ubseq-software
                \item Testing this now, if it works we will use it for SENSEI (we don't care about the ``smart'' stuff but it should fix some bugs)
            \end{itemize}
    \end{itemize}
\end{frame}

\begin{frame}{Data format}
    %\begin{center}
        %\includegraphics[width=\textwidth]{SENSEI_DAQ-LTA}
    %\end{center}
    \begin{itemize}
        \item The LTA transmits raw data to the daemon, just a stream of sample values calculated by the CDS blocks
            \begin{itemize}
                \item It's possible to lose data in transmission if a UDP packet is lost --- if this happens, the output file doesn't have the right dimensions
            \end{itemize}
        \item LTA daemon outputs a FITS file: one file with 4 HDUs (Header Data Unit), one per quadrant
            \begin{itemize}
                \item Before last week, the daemon wrote 4 separate FITS files
            \end{itemize}
        \item Each HDU contains:
            \begin{itemize}
                \item Header: values of LTA variables (voltage settings, sequencer variables and program, ``telemetry'' aka voltage readbacks)
                \item Image: array of floats, NCOL*NSAMP $\times$ NROW, not baseline-sutracted (0 $e^-$ is not 0 ADU, and the baseline shifts from pixel to pixel)
            \end{itemize}
    \end{itemize}
\end{frame}

\begin{frame}{CCD intro (diagrams from arXiv:1106.1839)}
\begin{columns}
\column{0.6\textwidth}
    \begin{itemize}
        \item CCD transfer and readout is controlled by cycling the ``clock'' voltages
        \item Vertical clocks move charge in the active area to the serial register: vertical transfer inefficiency can happen in the active area or at the transfer gate
        \item Horizontal clocks move charge in the serial register to the output stage: horizontal transfer inefficiency (HTI) can happen in the serial register or the output stage
        \item If you cycle the clocks more times than the physical number of rows or columns, you read out virtual pixels
            \begin{itemize}
                \item Overscan (OS): $x>369$ --- exposed while they traverse the serial register
                \item Vertical overscan: $y>624$ --- exposed during readout as they traverse the active area
                \item Prescan: $x<8$ --- cells between the active area and output stage, these should be the same as overscan
            \end{itemize}
    \end{itemize}
%\begin{center}
    %\end{center}
    \column{0.3\textwidth}
    \includegraphics[width=\textwidth]{SkipperCircuit}

    \includegraphics[width=\textwidth]{SkipperDiagram}
\end{columns}
\end{frame}

\begin{frame}{Data processing: skipper2root}
    %\begin{center}
        %\includegraphics[width=\textwidth]{SENSEI_DAQ-LTA}
    %\end{center}
    \begin{itemize}
        \item skipper2root.exe converts the raw FITS file to processed data: a processed FITS file and a ROOT file
            \begin{itemize}
                \item The images in the processed data are arrays NCOL $\times$ NROW, baseline-subtracted
                \item The ROOT file also contains the headers, can be useful for QA/tuning (\url{https://github.com/meeg/skipperAna/blob/master/spurious_charge_scan.py})
            \end{itemize}
        \item The averaging of the Skipper samples is easy, the baseline subtraction is hard
            \begin{itemize}
                \item Basic principle: most pixels in the overscan region have 0 $e^-$
                \item Problem: there is some spurious charge in OS (not much), and HTI can lead to significant charge in OS
            \end{itemize}
        \item With default options: average all the overscan pixels in each row, do linear interpolation between rows to estimate the baseline for every pixel
            \begin{itemize}
                \item If you have HTI, a few rows will have big negative shifts in the 0 $e^-$ peak
            \end{itemize}
        \item Smarter options fit the OS distribution (-z, -a) or use a running baseline (-b), but are not default since they can go nuts if the data is bad
        \item You should look at the options and try them out
    \end{itemize}
\end{frame}


%\begin{frame}{Readout development}
    %\begin{itemize}
        %\item \url{https://p25ext.lanl.gov/maps/readout.html}
            %\begin{itemize}
                %\item Update to final hardware (FELIX v2.x, RU v2.x)
                %\item sPHENIX timing+trigger
                %\item Control over optical link (slow controls, reprogramming)
            %\end{itemize}
        %\item Manpower: Alex T. (Seattle), Gerd, Alex W., Cameron, Yasser
        %\item Possible contributors: UT-Austin, GSU, Yonsei, LBL
        %\item Hardware:
            %\begin{itemize}
                %\item We have full readout chains (ALPIDE, RU v1.1, FELIX v1.5/v2.0) at LANL, UT-Austin, and Seattle
                %\item sPHENIX has a working prototype of the timing+trigger distribution that we can borrow
            %\end{itemize}
    %\end{itemize}
%\end{frame}

%\begin{frame}{Fix vertex fit}
%\begin{columns}
%\column{0.6\textwidth}
%\begin{itemize}
%\item The resolution of the reconstructed mass should be independent of Z but is worse for displaced vertices.
%\item This ad-hoc correction works pretty well: corrM = uncM - 0.15e-3*(elePX/eleP-posPX/posP)*uncVZ/uncM
%\item Hunch: the vertex mass is being calculated using the track directions at $z=0$, or something like that.
%\end{itemize}
%\begin{center}
%\includegraphics[width=\textwidth]{mass_shift_40}
%\end{center}
%\column{0.4\textwidth}
%\includegraphics[width=\textwidth,page=4]{acceptance_40}
%
%\includegraphics[width=\textwidth,page=5]{acceptance_40}
%\end{columns}
%\end{frame}

\end{document}