module ffrscms_test;

/*  verilog test of a clocked RS master-slave flip-flop  */

	wire q,qbar;               // declares two wires to receive outputs
	wire slave_set,slave_reset,slave_clock;
	reg set,reset,clock;       // declares three input variables
	parameter d = 30 ;         // waveform time step

/*  create master RS flip-flop module  */
	ffrsc ff1(slave_set,slave_reset,set,reset,clock);

/*  create slave clock  */
	not #1 (slave_clock,clock);     // inverter has unit delay

/*  create slave RS flip-flop module  */
	ffrsc ff2(q,qbar,slave_set,slave_reset,slave_clock);

/*  describe external stimulus of inputs  */
	initial
		begin
			#d set=0; reset=0; clock=0;
			#d set=1;
			#d set=0;
			#d ;
			#d reset=1;
			#d reset=0;
			#d ;
			#d set=1;
			#d clock=1;
			#d clock=0;
			#d ;
			#d set=0;
			#d ;
			#d reset=1;
			#d clock=1;
			#d clock=0;
			#d ;
			#d reset=0;
			#d ;
			#d ;
			#d set=1;
			#d ;
			#d ;
			#d ;
			#d set=0;
			#d ;
			#d ;
			#d set=1;

			$stop;

		end

/*  monitor system  */
	initial
	     begin
		$gr_waves("set",set,"reset",reset,"clock",clock,
			"slave clock",slave_clock,"q internal",
			slave_set,"qbar internal",slave_reset,"q",q,
			"qbar",qbar);
/*		$monitor($time,,
			"set=%b  reset=%b  clock=%b  q=%b  qbar=%b",
			set,  reset,  clock,  q,  qbar);   */
	     end

endmodule


module ffrsc(q,qbar,set,reset,clock);
	output q, qbar;
	input set, reset, clock;
	wire cs, cr;

/*  clocked RS flip-flop  */

	nand #1      // nand gates have unit delays
		g1(cs, set, clock),
		g2(cr, reset, clock),
		g3(q, qbar, cs),
		g4(qbar, q, cr);

endmodule
