module ffrsc_test;

/*  verilog test of a clocked RS flip-flop  */

	wire q,qbar;               // declares two wires to receive outputs
	reg set,reset,clock;       // declares three input variables
	parameter d = 20 ;         // waveform time step

/*  create clocked RS flip-flop module  */
	ffrsc ff1(q,qbar,set,reset,clock);

/*  describe external stimulus of inputs  */
	initial
		begin
			#d set=0; reset=0; clock=0;
			#d set=1;
			#d set=0;
			#d reset=1;
			#d reset=0;
			#d set=1;
			#d clock=1;
			#d clock=0;
			#d set=0;
			#d reset=1;
			#d clock=1;
			#d clock=0;
			#d reset=0;
		end

/*  monitor system  */
	initial
		$monitor($time,,
			"set=%b  reset=%b  clock=%b  q=%b  qbar=%b",
			set,  reset,  clock,  q,  qbar);

endmodule


module ffrsc(q,qbar,set,reset,clock);
	output q, qbar;
	input set, reset, clock;
	wire cs, cr;

/*  clocked RS flip-flop  */

	nand #1      // nand gates have unit delays
		g1(cs, set, clock),
		g2(cr, reset, clock),
		g3(q, qbar, cs),
		g4(qbar, q, cr);

endmodule
