module ffnand_test;

/*  verilog test of cross-coupled nand description of flip-flop  
	(see p 4-9 in manual) */

	wire q,qbar;          // declares two wires to receive outputs
	reg preset,clear;     // declares two input variables
	parameter d = 10 ;    // waveform time step

/*  create flip-flop module  */
	ffnand ff1(q,qbar,preset,clear);

/*  describe external stimulus of inputs  */
	initial
		begin
			#d preset = 0;  clear = 1;
			#d preset = 1;
			#d clear = 0;
			#d clear = 1;
		end

/*  monitor system  */
	initial
		$monitor($time,,
			"preset=%b  clear=%b  q=%b  qbar=%b",
			preset,  clear,  q,  qbar);

endmodule


module ffnand(q,qbar,preset,clear);
	output q, qbar;
	input preset, clear;

/*  cross-coupled nand description of flip-flop  */

	nand #1     //  nand gates with unit delay
		g1(q, qbar, preset),
		g2(qbar, q, clear);

endmodule
