module aclock_test;

/*  verilog test of simple clock  */  

	wire clock;           // declares one wire to receive output
	reg enable;           // declares one input variable
	parameter d = 20 ;     // waveform time step

/*  create clock module  */
	aclock c1(clock,enable);

/*  describe external stimulus of inputs  */
	initial
		begin
			#d enable = 0;
			#d ;
			#d ;
			#d ;
			#d enable = 1;
			#d ;
			#d ;
			#d ;
//			#d enable = 0;
		end

/*  monitor system  */
	initial
		$gr_waves("enable",enable,"clock",clock);
/*		$monitor($time,,
			"enable=%b  clock=%b ",
			enable, clock);               */

endmodule


module aclock(clock,enable);
	output clock;
	input enable;
	wire clockbar;

/*  a simple clock  */

	and #2   (clock,clockbar,enable);
	not #2   (clockbar,clock);

endmodule