 Date : March 5, 1989

 Library : SSI/MSI STANDARD PARTS

 Product compatibility : VERILOG VERSION 1.3b

 Functional implementation description (behavioral,UDP,gate) : 
      Mostly GATE and UDP Level. Few cells (123 & 221)
      have been modelled at behavioural level.

   For certain models exact delay distribution could not be done. 
   They have been generated by lumping the longest path delays at 
   the outputs of the paths. 

   The User Defined Primitives used in these models are defined 
   in the 'udps' directory. 


 LIBRARY    TOTAL NO. OF PACKAGED    TOTAL NO. OF PORTIONED
                  MODELS                       MODELS
                           
    -----------------------------------------------------------

      ALS          209                         209         
      AS           151                         151
      LS           158                         158
      FAST          78                          78

      ---------------------------------------------
      TOTAL        596                         596
      ---------------------------------------------

   All the models have been generated with all the three delay
   values i.e. MIN, TYP and MAX. 

 Source information :
     Databooks:
     1. TI ALS/AS LOGIC DATA BOOK (1986).
     2. TTL DATA BOOK VOL 2 (STD. TTL, S & LS) - (1985).
     3. SIGNETICS FAST DATA MANUAL (1987).

 Timing implementation description : Distributed delays and  no timing checks.

 Delay calculation implementation description : Direct delay values specified.

