ACD_Timing: ACD timing settings

All of the ACD timing related registers are located on the ACD readout controller (ARC) asics. The setting the widths is just a matter of optimizing efficiency against noise. Setting the delays requires doing scans to optimize for the front-end electronics shaper circuits.

• Registers:
  

  Group	Register Name	Instances	Multiplicity	Subsections	Type	Width (bits)
  ARC	hitmap_deadtime	12	1	1	int	3
  ARC	hold_delay	12	1	1	int	7
  ARC	hitmap_width	12	1	1	int	4
  ARC	hitmap_delay	12	1	1	int	xx
  ARC	veto_delay	12	1	1	int	5
  ARC	adc_tacq	12	1	1	int	6
  ARC	veto_width	12	1	1	int	xx

• Methods: BCAST
• Ancillary files: None.
• Constants: None.