# This file is mechanically-generated DOT code.  Do NOT edit this file!
# See bin/cat_y2d, instead.

digraph G {
  concentrate="true"; nodesep="0.2"; rankdir="LR"; ranksep="0.3"
  node[fontsize="7", fontname="Arial", height="0.25", shape="box" ];

# Nodes: tlm_pkt

{rank="same";
  DiagTemEnvPwr02 [
    style="filled" fillcolor="#AAAAAA"
    URL="P.DiagTemEnvPwr02.shtml"
    tooltip="pkt: Diagnostic TEM power ADCs for TEMs 8-11" ];
}

# Nodes: tlm_bf

{rank="same";
  ADC [
    style="filled" fillcolor="#E8E8E8"
    URL="B.ADC.shtml"
    tooltip="bf: An ADC result" ];
}

# Nodes: tlm_fld

{rank="same";
  ADClimit_LHKADCLMTSTATES [
    label="ADClimit "
    URL="F.ADClimit.shtml"
    tooltip="fld: ADC limit evaluation" ];
  ADCvalue [
    URL="F.ADCvalue.shtml"
    tooltip="fld: Raw ADC value" ];
  Padus16 [
    URL="F.Padus16.shtml"
    tooltip="fld: Explicit 16 bit pad in unsigned short" ];
  status_LHKSETTLESTATES [
    label="status "
    URL="F.status.shtml"
    tooltip="fld: Readout status (ADC or switch)" ];
}

# Nodes: attr

{rank="same";
  LHKADCLMTSTATES [
    style="dashed" label="LHKADCLMTSTATES "
    URL="../../att/dsc-LHKADCLMTSTATES.shtml"
    tooltip="dsc: Enumeration of ADC limit evaluation states" ];
  LHKSETTLESTATES [
    style="dashed" label="LHKSETTLESTATES "
    URL="../../att/dsc-LHKSETTLESTATES.shtml"
    tooltip="dsc: ADC settling state" ];
}

# Edges

  DiagTemEnvPwr02                         ->  ADC;
    ADC                                   ->  ADClimit_LHKADCLMTSTATES;
      ADClimit_LHKADCLMTSTATES            ->  LHKADCLMTSTATES;
    ADC                                   ->  ADCvalue;
    ADC                                   ->  status_LHKSETTLESTATES;
      status_LHKSETTLESTATES              ->  LHKSETTLESTATES;
  DiagTemEnvPwr02                         ->  Padus16;

}