The Director SBC is responsible for programming the Configuration space registers of each PCI module in the crate. It is important that only a single SBC, the Director SBC, perform this function – the Actor SBCs must wait for the Director SBC to finish configuring the PCI bus before accessing the LCB.
Configuring the PCI bus consists of defining the PCI memory spaces for each PCI module detected in the crate. In simple terms you can think of this as plug-n-play configuration.
When a PCI module is detected the Director SBC configures it by setting its Base Address Registers (BARs) and the Interrupt Pin located in the Configuration space of the PCI module.
Next the Director SBC enables the I/O space by programming the PCI Command register located in Configuration space.
The BARs define the PCI addresses of the I/O and Memory spaces and also the size of each space. The size of each space is fixed by the VHDL of the PCI module, but the Director SBC programs the PCI address of each space. The addresses of these spaces is 32-bit aligned.
The PCI configuration space Command register controls various properties of a PCI device including:
Enabling I/O space
Enabling Memory space
Enabling Bus Mastering
The PCI Status register also contains information about the outcome of recent PCI transactions. The Director SBC clears this register at the end of the configuration phase.