\hypertarget{struct__BFregControl}{
\section{\_\-BFreg\-Control Struct Reference}
\label{struct__BFregControl}\index{_BFregControl@{\_\-BFregControl}}
}
map of the comm i/o board 32-bit control register  


{\tt \#include $<$GTB.h$>$}

\subsection*{Data Fields}
\begin{CompactItemize}
\item 
unsigned int \hyperlink{struct__BFregControl_o0}{start\-Acq}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o1}{start\-Acq\-Src}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o2}{chn0clk}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o3}{data\-Chn}:4
\item 
unsigned int \hyperlink{struct__BFregControl_o4}{mode}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o5}{rbfw\-Delay}:8
\item 
unsigned int \hyperlink{struct__BFregControl_o6}{f1pr}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o7}{f1mr}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o8}{f0pr}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o9}{f0mr}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o10}{rsrv1}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o11}{lat\-Addr}:5
\item 
unsigned int \hyperlink{struct__BFregControl_o12}{cno\-Veto\-Mux}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o13}{gem\-Start}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o14}{b31Start}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o15}{fp\-Start}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o16}{clk\-Sel}:2
\end{CompactItemize}


\subsection{Detailed Description}
map of the comm i/o board 32-bit control register 



\subsection{Field Documentation}
\hypertarget{struct__BFregControl_o14}{
\index{_BFregControl@{\_\-BFreg\-Control}!b31Start@{b31Start}}
\index{b31Start@{b31Start}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[b31Start]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o14}{\_\-BFreg\-Control::b31Start}}}
\label{struct__BFregControl_o14}


Enable programmed start, bit 31 of this register \hypertarget{struct__BFregControl_o2}{
\index{_BFregControl@{\_\-BFreg\-Control}!chn0clk@{chn0clk}}
\index{chn0clk@{chn0clk}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[chn0clk]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o2}{\_\-BFreg\-Control::chn0clk}}}
\label{struct__BFregControl_o2}


Channel 0 clock mode: 0 programmable pulse train, 1 continuous clock \hypertarget{struct__BFregControl_o16}{
\index{_BFregControl@{\_\-BFreg\-Control}!clkSel@{clkSel}}
\index{clkSel@{clkSel}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[clkSel]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o16}{\_\-BFreg\-Control::clk\-Sel}}}
\label{struct__BFregControl_o16}


clk select : TEM: 00b = internal 10b = primary ext 11b = redundant ext FREE: 00b = internal 10b = port 0 ext 11b = port 1 ext \hypertarget{struct__BFregControl_o12}{
\index{_BFregControl@{\_\-BFreg\-Control}!cnoVetoMux@{cnoVetoMux}}
\index{cnoVetoMux@{cnoVetoMux}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[cnoVetoMux]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o12}{\_\-BFreg\-Control::cno\-Veto\-Mux}}}
\label{struct__BFregControl_o12}


FREE VETO/CNO mux: 0 = VETO, 1 = CNO \hypertarget{struct__BFregControl_o3}{
\index{_BFregControl@{\_\-BFreg\-Control}!dataChn@{dataChn}}
\index{dataChn@{dataChn}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[dataChn]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o3}{\_\-BFreg\-Control::data\-Chn}}}
\label{struct__BFregControl_o3}


Select input channel when running LATp \hypertarget{struct__BFregControl_o9}{
\index{_BFregControl@{\_\-BFreg\-Control}!f0mr@{f0mr}}
\index{f0mr@{f0mr}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[f0mr]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o9}{\_\-BFreg\-Control::f0mr}}}
\label{struct__BFregControl_o9}


play FIFO master reset: 0 reset, reset data and config \hypertarget{struct__BFregControl_o8}{
\index{_BFregControl@{\_\-BFreg\-Control}!f0pr@{f0pr}}
\index{f0pr@{f0pr}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[f0pr]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o8}{\_\-BFreg\-Control::f0pr}}}
\label{struct__BFregControl_o8}


play FIFO partial reset: 0 reset, reset data, no config \hypertarget{struct__BFregControl_o7}{
\index{_BFregControl@{\_\-BFreg\-Control}!f1mr@{f1mr}}
\index{f1mr@{f1mr}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[f1mr]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o7}{\_\-BFreg\-Control::f1mr}}}
\label{struct__BFregControl_o7}


record FIFO master reset: 0 reset, reset data and config \hypertarget{struct__BFregControl_o6}{
\index{_BFregControl@{\_\-BFreg\-Control}!f1pr@{f1pr}}
\index{f1pr@{f1pr}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[f1pr]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o6}{\_\-BFreg\-Control::f1pr}}}
\label{struct__BFregControl_o6}


record FIFO partial reset: 0 reset, reset data, no config \hypertarget{struct__BFregControl_o15}{
\index{_BFregControl@{\_\-BFreg\-Control}!fpStart@{fpStart}}
\index{fpStart@{fpStart}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[fpStart]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o15}{\_\-BFreg\-Control::fp\-Start}}}
\label{struct__BFregControl_o15}


Enable start from front panel \hypertarget{struct__BFregControl_o13}{
\index{_BFregControl@{\_\-BFreg\-Control}!gemStart@{gemStart}}
\index{gemStart@{gemStart}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[gemStart]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o13}{\_\-BFreg\-Control::gem\-Start}}}
\label{struct__BFregControl_o13}


Enable GEM commanded start \hypertarget{struct__BFregControl_o11}{
\index{_BFregControl@{\_\-BFreg\-Control}!latAddr@{latAddr}}
\index{latAddr@{latAddr}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[latAddr]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o11}{\_\-BFreg\-Control::lat\-Addr}}}
\label{struct__BFregControl_o11}


Address to respond for GEM commanded start \hypertarget{struct__BFregControl_o4}{
\index{_BFregControl@{\_\-BFreg\-Control}!mode@{mode}}
\index{mode@{mode}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[mode]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o4}{\_\-BFreg\-Control::mode}}}
\label{struct__BFregControl_o4}


Record FIFO mode. 0 - \char`\"{}dumb FIFO\char`\"{}, 1 - \char`\"{}LATp FIFO\char`\"{} \hypertarget{struct__BFregControl_o5}{
\index{_BFregControl@{\_\-BFreg\-Control}!rbfwDelay@{rbfwDelay}}
\index{rbfwDelay@{rbfwDelay}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[rbfwDelay]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o5}{\_\-BFreg\-Control::rbfw\-Delay}}}
\label{struct__BFregControl_o5}


Delay of write to record FIFO for up to 6.4 usec \hypertarget{struct__BFregControl_o10}{
\index{_BFregControl@{\_\-BFreg\-Control}!rsrv1@{rsrv1}}
\index{rsrv1@{rsrv1}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[rsrv1]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o10}{\_\-BFreg\-Control::rsrv1}}}
\label{struct__BFregControl_o10}


pad \hypertarget{struct__BFregControl_o0}{
\index{_BFregControl@{\_\-BFreg\-Control}!startAcq@{startAcq}}
\index{startAcq@{startAcq}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[startAcq]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o0}{\_\-BFreg\-Control::start\-Acq}}}
\label{struct__BFregControl_o0}


Start acquisition on 0 to 1 transition \hypertarget{struct__BFregControl_o1}{
\index{_BFregControl@{\_\-BFreg\-Control}!startAcqSrc@{startAcqSrc}}
\index{startAcqSrc@{startAcqSrc}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[startAcqSrc]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o1}{\_\-BFreg\-Control::start\-Acq\-Src}}}
\label{struct__BFregControl_o1}


Select source of start acquisition: 0 start\-Acq, 1 external 

The documentation for this struct was generated from the following file:\begin{CompactItemize}
\item 
\hyperlink{GTB_8h}{GTB.h}\end{CompactItemize}
