\hypertarget{struct__BFregControl}{
\section{\_\-BFreg\-Control Struct Reference}
\label{struct__BFregControl}\index{_BFregControl@{\_\-BFregControl}}
}
map of the comm i/o board 32-bit control register  


{\tt \#include $<$reg\_\-p.h$>$}

\subsection*{Data Fields}
\begin{CompactItemize}
\item 
unsigned int \hyperlink{struct__BFregControl_o0}{start\-Acq}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o1}{start\-Acq\-Src}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o2}{chn0clk}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o3}{data\-Chn}:4
\item 
unsigned int \hyperlink{struct__BFregControl_o4}{mode}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o5}{rbfw\-Delay}:8
\item 
unsigned int \hyperlink{struct__BFregControl_o6}{rfpr}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o7}{rfmr}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o8}{pfpr}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o9}{pfmr}:1
\item 
unsigned int \hyperlink{struct__BFregControl_o10}{rbc\-Delay}:6
\item 
unsigned int \hyperlink{struct__BFregControl_o11}{c0delay}:6
\end{CompactItemize}


\subsection{Detailed Description}
map of the comm i/o board 32-bit control register 



\subsection{Field Documentation}
\hypertarget{struct__BFregControl_o11}{
\index{_BFregControl@{\_\-BFreg\-Control}!c0delay@{c0delay}}
\index{c0delay@{c0delay}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[c0delay]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o11}{\_\-BFreg\-Control::c0delay}}}
\label{struct__BFregControl_o11}


channel 0 delay in 2ns steps. max 60ns \hypertarget{struct__BFregControl_o2}{
\index{_BFregControl@{\_\-BFreg\-Control}!chn0clk@{chn0clk}}
\index{chn0clk@{chn0clk}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[chn0clk]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o2}{\_\-BFreg\-Control::chn0clk}}}
\label{struct__BFregControl_o2}


Channel 0 clock mode: 0 programmable pulse train, 1 continuous clock \hypertarget{struct__BFregControl_o3}{
\index{_BFregControl@{\_\-BFreg\-Control}!dataChn@{dataChn}}
\index{dataChn@{dataChn}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[dataChn]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o3}{\_\-BFreg\-Control::data\-Chn}}}
\label{struct__BFregControl_o3}


Select input channel when running LATp \hypertarget{struct__BFregControl_o4}{
\index{_BFregControl@{\_\-BFreg\-Control}!mode@{mode}}
\index{mode@{mode}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[mode]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o4}{\_\-BFreg\-Control::mode}}}
\label{struct__BFregControl_o4}


Record FIFO mode. 0 - \char`\"{}dumb FIFO\char`\"{}, 1 - \char`\"{}LATp FIFO\char`\"{} \hypertarget{struct__BFregControl_o9}{
\index{_BFregControl@{\_\-BFreg\-Control}!pfmr@{pfmr}}
\index{pfmr@{pfmr}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[pfmr]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o9}{\_\-BFreg\-Control::pfmr}}}
\label{struct__BFregControl_o9}


play FIFO master reset: 0 reset, reset data and config \hypertarget{struct__BFregControl_o8}{
\index{_BFregControl@{\_\-BFreg\-Control}!pfpr@{pfpr}}
\index{pfpr@{pfpr}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[pfpr]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o8}{\_\-BFreg\-Control::pfpr}}}
\label{struct__BFregControl_o8}


play FIFO partial reset: 0 reset, reset data, no config \hypertarget{struct__BFregControl_o10}{
\index{_BFregControl@{\_\-BFreg\-Control}!rbcDelay@{rbcDelay}}
\index{rbcDelay@{rbcDelay}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[rbcDelay]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o10}{\_\-BFreg\-Control::rbc\-Delay}}}
\label{struct__BFregControl_o10}


read back clock dealy in 2ns steps. max 60ns \hypertarget{struct__BFregControl_o5}{
\index{_BFregControl@{\_\-BFreg\-Control}!rbfwDelay@{rbfwDelay}}
\index{rbfwDelay@{rbfwDelay}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[rbfwDelay]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o5}{\_\-BFreg\-Control::rbfw\-Delay}}}
\label{struct__BFregControl_o5}


Delay of write to record FIFO for up to 6.4 usec \hypertarget{struct__BFregControl_o7}{
\index{_BFregControl@{\_\-BFreg\-Control}!rfmr@{rfmr}}
\index{rfmr@{rfmr}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[rfmr]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o7}{\_\-BFreg\-Control::rfmr}}}
\label{struct__BFregControl_o7}


record FIFO master reset: 0 reset, reset data and config \hypertarget{struct__BFregControl_o6}{
\index{_BFregControl@{\_\-BFreg\-Control}!rfpr@{rfpr}}
\index{rfpr@{rfpr}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[rfpr]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o6}{\_\-BFreg\-Control::rfpr}}}
\label{struct__BFregControl_o6}


record FIFO partial reset: 0 reset, reset data, no config \hypertarget{struct__BFregControl_o0}{
\index{_BFregControl@{\_\-BFreg\-Control}!startAcq@{startAcq}}
\index{startAcq@{startAcq}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[startAcq]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o0}{\_\-BFreg\-Control::start\-Acq}}}
\label{struct__BFregControl_o0}


Start acquisition on 0 to 1 transition \hypertarget{struct__BFregControl_o1}{
\index{_BFregControl@{\_\-BFreg\-Control}!startAcqSrc@{startAcqSrc}}
\index{startAcqSrc@{startAcqSrc}!_BFregControl@{\_\-BFreg\-Control}}
\subsubsection[startAcqSrc]{\setlength{\rightskip}{0pt plus 5cm}unsigned int \hyperlink{struct__BFregControl_o1}{\_\-BFreg\-Control::start\-Acq\-Src}}}
\label{struct__BFregControl_o1}


Select source of start acquisition: 0 start\-Acq, 1 external 

The documentation for this struct was generated from the following file:\begin{CompactItemize}
\item 
\hyperlink{reg__p_8h}{reg\_\-p.h}\end{CompactItemize}