\hypertarget{CACHE_8h}{ \section{CACHE.h File Reference} \label{CACHE_8h}\index{CACHE.h@{CACHE.h}} } Cache manipulation routines. Currently NOOPs on all but the VxWorks platforms. {\tt \#include $<$PBS/impl/CACHE.h.xx-xxx-xxx$>$}\par \subsection*{Defines} \begin{CompactItemize} \item \hypertarget{CACHE_8h_49072ebf3bb89a234dc35377af0e73aa}{ \#define \hyperlink{CACHE_8h_49072ebf3bb89a234dc35377af0e73aa}{CACHE\_\-K\_\-DATA\_\-LINE\_\-SIZE}~(1 $<$$<$ CACHE\_\-K\_\-DATA\_\-LINE\_\-SIZE\_\-PWR2)} \label{CACHE_8h_49072ebf3bb89a234dc35377af0e73aa} \begin{CompactList}\small\item\em Size, in bytes, of a data cache line. This is just a convenience symbol and is the equivalent of (1 $<$$<$ CACHE\_\-K\_\-DATA\_\-LINE\_\-SIZE\_\-PWR2). \item\end{CompactList}\item \hypertarget{CACHE_8h_5d73717a055846a6a803e17fac4ff687}{ \#define \hyperlink{CACHE_8h_5d73717a055846a6a803e17fac4ff687}{CACHE\_\-K\_\-DATA\_\-LINE\_\-MASK}~(CACHE\_\-K\_\-DATA\_\-LINE\_\-SIZE - 1)} \label{CACHE_8h_5d73717a055846a6a803e17fac4ff687} \begin{CompactList}\small\item\em Mask of the low bits of a data address cache line. \item\end{CompactList}\item \hypertarget{CACHE_8h_b86eb1eb31b3867bdf4fe17588995c5d}{ \#define \hyperlink{CACHE_8h_b86eb1eb31b3867bdf4fe17588995c5d}{CACHE\_\-K\_\-INSTRUCTION\_\-LINE\_\-SIZE}~(1 $<$$<$ CACHE\_\-K\_\-INSTRUCTION\_\-LINE\_\-SIZE\_\-PWR2)} \label{CACHE_8h_b86eb1eb31b3867bdf4fe17588995c5d} \begin{CompactList}\small\item\em Size, in bytes, of a instruction cache line. This is just a convenience symbol and is the equivalent of (1 $<$$<$ CACHE\_\-K\_\-DATA\_\-LINE\_\-SIZE\_\-PWR2). \item\end{CompactList}\item \hypertarget{CACHE_8h_30a440921947dde892db26fd6cda95ab}{ \#define \hyperlink{CACHE_8h_30a440921947dde892db26fd6cda95ab}{CACHE\_\-K\_\-INSTRUCTION\_\-LINE\_\-MASK}~(CACHE\_\-K\_\-INSTRUCTION\_\-LINE\_\-SIZE - 1)} \label{CACHE_8h_30a440921947dde892db26fd6cda95ab} \begin{CompactList}\small\item\em Mask of the low bits of an instruction address cache line. \item\end{CompactList}\item \hypertarget{CACHE_8h_f7c5d969c2fa44e74aa9ce497ca7769a}{ \#define \hyperlink{CACHE_8h_f7c5d969c2fa44e74aa9ce497ca7769a}{\_\-CACHE\_\-K\_\-INSTRUCTION}~0} \label{CACHE_8h_f7c5d969c2fa44e74aa9ce497ca7769a} \begin{CompactList}\small\item\em Internal use only symbol. \item\end{CompactList}\item \hypertarget{CACHE_8h_e48b8f487e3771dd2a6578e7e90a6fce}{ \#define \hyperlink{CACHE_8h_e48b8f487e3771dd2a6578e7e90a6fce}{\_\-CACHE\_\-K\_\-DATA}~1} \label{CACHE_8h_e48b8f487e3771dd2a6578e7e90a6fce} \begin{CompactList}\small\item\em Internal use only symbol. \item\end{CompactList}\item \hypertarget{CACHE_8h_f9522a76d672d1d15abc696172bbff06}{ \#define \hyperlink{CACHE_8h_f9522a76d672d1d15abc696172bbff06}{\_\-CACHE\_\-K\_\-BRANCH}~2} \label{CACHE_8h_f9522a76d672d1d15abc696172bbff06} \begin{CompactList}\small\item\em Internal use only symbol. \item\end{CompactList}\end{CompactItemize} \subsection*{Typedefs} \begin{CompactItemize} \item \hypertarget{CACHE_8h_5a202fc29e75d2bf3ff160e32b64b575}{ typedef enum \hyperlink{CACHE_8h_ae7b2fa31a7f27b6b0d7d88651859138}{\_\-CACHE\_\-type} \hyperlink{CACHE_8h_5a202fc29e75d2bf3ff160e32b64b575}{CACHE\_\-type}} \label{CACHE_8h_5a202fc29e75d2bf3ff160e32b64b575} \begin{CompactList}\small\item\em Typedef for enum {\em \_\-CACHE\_\-type\/}. \item\end{CompactList}\end{CompactItemize} \subsection*{Enumerations} \begin{CompactItemize} \item enum \hyperlink{CACHE_8h_ae7b2fa31a7f27b6b0d7d88651859138}{\_\-CACHE\_\-type} \{ \par \hyperlink{CACHE_8h_ae7b2fa31a7f27b6b0d7d8865185913821283d4726a5ec9f50df92ea8413a6df}{CACHE\_\-K\_\-INSTRUCTION} = \_\-CACHE\_\-K\_\-INSTRUCTION, \par \hyperlink{CACHE_8h_ae7b2fa31a7f27b6b0d7d88651859138a37743f59b76d2c4c699965f6624dcf8}{CACHE\_\-K\_\-DATA} = \_\-CACHE\_\-K\_\-DATA, \par \hyperlink{CACHE_8h_ae7b2fa31a7f27b6b0d7d8865185913877373d3571fb5c3006204539ff4a1ff4}{CACHE\_\-K\_\-BRANCH} = \_\-CACHE\_\-K\_\-BRANCH \} \begin{CompactList}\small\item\em The target cache type. \item\end{CompactList}\end{CompactItemize} \subsection*{Functions} \begin{CompactItemize} \item int \hyperlink{CACHE_8h_aa111c0a6c0600fbc126e2e5f9f5718b}{CACHE\_\-disable} (\hyperlink{CACHE_8h_5a202fc29e75d2bf3ff160e32b64b575}{CACHE\_\-type} type) \begin{CompactList}\small\item\em Disable the specified cache. \item\end{CompactList}\item int \hyperlink{CACHE_8h_97c0a479f3f2e26fa9566edf564c8c9d}{CACHE\_\-enable} (\hyperlink{CACHE_8h_5a202fc29e75d2bf3ff160e32b64b575}{CACHE\_\-type} type) \begin{CompactList}\small\item\em Enable the specified cache. \item\end{CompactList}\item int \hyperlink{CACHE_8h_5335c065f1eb8f849fb0f947c2e5e688}{CACHE\_\-clear} (\hyperlink{CACHE_8h_5a202fc29e75d2bf3ff160e32b64b575}{CACHE\_\-type} type, void $\ast$address, int nbytes) \begin{CompactList}\small\item\em Clear all or some entries from a cache. \item\end{CompactList}\item int \hyperlink{CACHE_8h_af1dc3d8b6802caf01d1a8434fb01f0c}{CACHE\_\-flush} (\hyperlink{CACHE_8h_5a202fc29e75d2bf3ff160e32b64b575}{CACHE\_\-type} type, void $\ast$address, int nbytes) \begin{CompactList}\small\item\em Flush all or some of a specified cache. \item\end{CompactList}\item int \hyperlink{CACHE_8h_e606d7a14e22ec0c2692f57c970ddb5c}{CACHE\_\-invalidate} (\hyperlink{CACHE_8h_5a202fc29e75d2bf3ff160e32b64b575}{CACHE\_\-type} type, void $\ast$address, int nbytes) \begin{CompactList}\small\item\em invalidate all or some of a specified cache \item\end{CompactList}\item int \hyperlink{CACHE_8h_0bfaa8142ccb92cc9057df75fa2e284c}{CACHE\_\-lock} (\hyperlink{CACHE_8h_5a202fc29e75d2bf3ff160e32b64b575}{CACHE\_\-type} type, void $\ast$address, int nbytes) \begin{CompactList}\small\item\em Lock all or part of a specified cache. \item\end{CompactList}\item int \hyperlink{CACHE_8h_20cea7d7dd39c2829b880e106080f0d7}{CACHE\_\-unlock} (\hyperlink{CACHE_8h_5a202fc29e75d2bf3ff160e32b64b575}{CACHE\_\-type} type, void $\ast$address, int nbytes) \begin{CompactList}\small\item\em Unlock all or part of a specified cache. \item\end{CompactList}\item int \hyperlink{CACHE_8h_59fd64a2c1c2432ef6f8f6c8ad1ab9e1}{CACHE\_\-pipeFlush} (void) \begin{CompactList}\small\item\em Flush the processor write buffers to memory. \item\end{CompactList}\end{CompactItemize} \subsection{Detailed Description} Cache manipulation routines. Currently NOOPs on all but the VxWorks platforms. \begin{Desc} \item[Author:]JJRussell - \href{mailto:russell@slac.stanford.edu}{\tt russell@slac.stanford.edu}\end{Desc} \footnotesize\begin{verbatim} CVS $Id: CACHE.h,v 1.5 2011/03/24 23:05:41 apw Exp $ \end{verbatim} \normalsize \begin{Desc} \item[SYNOPSIS]This provides a series of portable cache manipulation routines. These are implemented as either function aliases or macros depending on the platform. \end{Desc} \subsection{Enumeration Type Documentation} \hypertarget{CACHE_8h_ae7b2fa31a7f27b6b0d7d88651859138}{ \index{CACHE.h@{CACHE.h}!\_\-CACHE\_\-type@{\_\-CACHE\_\-type}} \index{\_\-CACHE\_\-type@{\_\-CACHE\_\-type}!CACHE.h@{CACHE.h}} \subsubsection[{\_\-CACHE\_\-type}]{\setlength{\rightskip}{0pt plus 5cm}enum {\bf \_\-CACHE\_\-type}}} \label{CACHE_8h_ae7b2fa31a7f27b6b0d7d88651859138} The target cache type. \begin{Desc} \item[Enumerator: ]\par \begin{description} \index{CACHE\_\-K\_\-INSTRUCTION@{CACHE\_\-K\_\-INSTRUCTION}!CACHE.h@{CACHE.h}}\index{CACHE.h@{CACHE.h}!CACHE\_\-K\_\-INSTRUCTION@{CACHE\_\-K\_\-INSTRUCTION}}\item[{\em \hypertarget{CACHE_8h_ae7b2fa31a7f27b6b0d7d8865185913821283d4726a5ec9f50df92ea8413a6df}{ CACHE\_\-K\_\-INSTRUCTION} \label{CACHE_8h_ae7b2fa31a7f27b6b0d7d8865185913821283d4726a5ec9f50df92ea8413a6df} }]The instruction cache \index{CACHE\_\-K\_\-DATA@{CACHE\_\-K\_\-DATA}!CACHE.h@{CACHE.h}}\index{CACHE.h@{CACHE.h}!CACHE\_\-K\_\-DATA@{CACHE\_\-K\_\-DATA}}\item[{\em \hypertarget{CACHE_8h_ae7b2fa31a7f27b6b0d7d88651859138a37743f59b76d2c4c699965f6624dcf8}{ CACHE\_\-K\_\-DATA} \label{CACHE_8h_ae7b2fa31a7f27b6b0d7d88651859138a37743f59b76d2c4c699965f6624dcf8} }]The data cache \index{CACHE\_\-K\_\-BRANCH@{CACHE\_\-K\_\-BRANCH}!CACHE.h@{CACHE.h}}\index{CACHE.h@{CACHE.h}!CACHE\_\-K\_\-BRANCH@{CACHE\_\-K\_\-BRANCH}}\item[{\em \hypertarget{CACHE_8h_ae7b2fa31a7f27b6b0d7d8865185913877373d3571fb5c3006204539ff4a1ff4}{ CACHE\_\-K\_\-BRANCH} \label{CACHE_8h_ae7b2fa31a7f27b6b0d7d8865185913877373d3571fb5c3006204539ff4a1ff4} }]The branch cache \end{description} \end{Desc} \subsection{Function Documentation} \hypertarget{CACHE_8h_5335c065f1eb8f849fb0f947c2e5e688}{ \index{CACHE.h@{CACHE.h}!CACHE\_\-clear@{CACHE\_\-clear}} \index{CACHE\_\-clear@{CACHE\_\-clear}!CACHE.h@{CACHE.h}} \subsubsection[{CACHE\_\-clear}]{\setlength{\rightskip}{0pt plus 5cm}int CACHE\_\-clear ({\bf CACHE\_\-type} {\em type}, \/ void $\ast$ {\em address}, \/ int {\em nbytes})}} \label{CACHE_8h_5335c065f1eb8f849fb0f947c2e5e688} Clear all or some entries from a cache. \begin{Desc} \item[Parameters:] \begin{description} \item[{\em type}]The cache type, i.e. one of {\em CACHE\_\-K\_\-BRANCH\/}, {\em CACHE\_\-K\_\-DATA\/} or {\em CACHE\_\-K\_\-INSTRUCTION\/}. \item[{\em address}]The address to start clearing at \item[{\em nbytes}]The number of bytes to clear \end{description} \end{Desc} \begin{Desc} \item[Returns:]Status, OK, unless the cache type is invalid or not supported on the target architecture.\end{Desc} Flushes and invalidates all of some of the entries in the specified cache. \hypertarget{CACHE_8h_aa111c0a6c0600fbc126e2e5f9f5718b}{ \index{CACHE.h@{CACHE.h}!CACHE\_\-disable@{CACHE\_\-disable}} \index{CACHE\_\-disable@{CACHE\_\-disable}!CACHE.h@{CACHE.h}} \subsubsection[{CACHE\_\-disable}]{\setlength{\rightskip}{0pt plus 5cm}int CACHE\_\-disable ({\bf CACHE\_\-type} {\em type})}} \label{CACHE_8h_aa111c0a6c0600fbc126e2e5f9f5718b} Disable the specified cache. \begin{Desc} \item[Parameters:] \begin{description} \item[{\em type}]The cache type, i.e. one of {\em CACHE\_\-K\_\-DATA\/} or {\em CACHE\_\-K\_\-INSTRUCTION\/}. \end{description} \end{Desc} \begin{Desc} \item[Returns:]Status, OK, unless the cache type is invalid or not supported on the target architecture.\end{Desc} Flushes the specified cache and disables the instruction or data cache. \hypertarget{CACHE_8h_97c0a479f3f2e26fa9566edf564c8c9d}{ \index{CACHE.h@{CACHE.h}!CACHE\_\-enable@{CACHE\_\-enable}} \index{CACHE\_\-enable@{CACHE\_\-enable}!CACHE.h@{CACHE.h}} \subsubsection[{CACHE\_\-enable}]{\setlength{\rightskip}{0pt plus 5cm}int CACHE\_\-enable ({\bf CACHE\_\-type} {\em type})}} \label{CACHE_8h_97c0a479f3f2e26fa9566edf564c8c9d} Enable the specified cache. \begin{Desc} \item[Parameters:] \begin{description} \item[{\em type}]The cache type, i.e. one of {\em CACHE\_\-K\_\-DATA\/} or {\em CACHE\_\-K\_\-INSTRUCTION\/}. \end{description} \end{Desc} \begin{Desc} \item[Returns:]Status, OK, unless the cache type is invalid or not supported on the target architecture.\end{Desc} Invalidates the cache tags and enables the instruction or date cache. \hypertarget{CACHE_8h_af1dc3d8b6802caf01d1a8434fb01f0c}{ \index{CACHE.h@{CACHE.h}!CACHE\_\-flush@{CACHE\_\-flush}} \index{CACHE\_\-flush@{CACHE\_\-flush}!CACHE.h@{CACHE.h}} \subsubsection[{CACHE\_\-flush}]{\setlength{\rightskip}{0pt plus 5cm}int CACHE\_\-flush ({\bf CACHE\_\-type} {\em type}, \/ void $\ast$ {\em address}, \/ int {\em nbytes})}} \label{CACHE_8h_af1dc3d8b6802caf01d1a8434fb01f0c} Flush all or some of a specified cache. \begin{Desc} \item[Parameters:] \begin{description} \item[{\em type}]The cache type, i.e. one of {\em CACHE\_\-K\_\-BRANCH\/}, {\em CACHE\_\-K\_\-DATA\/} or {\em CACHE\_\-K\_\-INSTRUCTION\/}. \item[{\em address}]The address to start flushing at \item[{\em nbytes}]The number of bytes to flush \end{description} \end{Desc} \begin{Desc} \item[Returns:]Status, OK, unless the cache type is invalid or not supported on the target architecture.\end{Desc} Flushes (writes to memory) all or some of the entries in the specified cache. Depending on the cache desing, this operation may also invalidate the cache tags. For write-through caches, no work needs to be done since RAM already matches the cache entries. Note that write buffer on the chip may need to be flushed to complete the flush. See CACHE\_\-pipeFlush. \hypertarget{CACHE_8h_e606d7a14e22ec0c2692f57c970ddb5c}{ \index{CACHE.h@{CACHE.h}!CACHE\_\-invalidate@{CACHE\_\-invalidate}} \index{CACHE\_\-invalidate@{CACHE\_\-invalidate}!CACHE.h@{CACHE.h}} \subsubsection[{CACHE\_\-invalidate}]{\setlength{\rightskip}{0pt plus 5cm}int CACHE\_\-invalidate ({\bf CACHE\_\-type} {\em type}, \/ void $\ast$ {\em address}, \/ int {\em nbytes})}} \label{CACHE_8h_e606d7a14e22ec0c2692f57c970ddb5c} invalidate all or some of a specified cache \begin{Desc} \item[Parameters:] \begin{description} \item[{\em type}]The cache type, i.e. one of {\em CACHE\_\-K\_\-BRANCH\/}, a$\backslash$ CACHE\_\-K\_\-DATA or {\em CACHE\_\-K\_\-INSTRUCTION\/}. \item[{\em address}]The address to start invalidating at \item[{\em nbytes}]The number of bytes to invalidate \end{description} \end{Desc} \begin{Desc} \item[Returns:]Status, OK, unless the cache type is invalid or not supported on the target architecture.\end{Desc} Invalidates all or some of the entries in the specified cache. Depending on the cache design, the invalidate may be similar to the flush, or the tags may be invalidate directly. \hypertarget{CACHE_8h_0bfaa8142ccb92cc9057df75fa2e284c}{ \index{CACHE.h@{CACHE.h}!CACHE\_\-lock@{CACHE\_\-lock}} \index{CACHE\_\-lock@{CACHE\_\-lock}!CACHE.h@{CACHE.h}} \subsubsection[{CACHE\_\-lock}]{\setlength{\rightskip}{0pt plus 5cm}int CACHE\_\-lock ({\bf CACHE\_\-type} {\em type}, \/ void $\ast$ {\em address}, \/ int {\em nbytes})}} \label{CACHE_8h_0bfaa8142ccb92cc9057df75fa2e284c} Lock all or part of a specified cache. \begin{Desc} \item[Parameters:] \begin{description} \item[{\em type}]The cache type, i.e. one of {\em CACHE\_\-K\_\-DATA\/} or {\em CACHE\_\-K\_\-INSTRUCTION\/}. \item[{\em address}]The address to start locking at \item[{\em nbytes}]The number of bytes to lock \end{description} \end{Desc} \begin{Desc} \item[Returns:]Status, OK, unless the cache type is invalid or not supported on the target architecture.\end{Desc} Locks entries in the specified cache. Currently only the MCP750 supports cache locking. \hypertarget{CACHE_8h_59fd64a2c1c2432ef6f8f6c8ad1ab9e1}{ \index{CACHE.h@{CACHE.h}!CACHE\_\-pipeFlush@{CACHE\_\-pipeFlush}} \index{CACHE\_\-pipeFlush@{CACHE\_\-pipeFlush}!CACHE.h@{CACHE.h}} \subsubsection[{CACHE\_\-pipeFlush}]{\setlength{\rightskip}{0pt plus 5cm}int CACHE\_\-pipeFlush (void)}} \label{CACHE_8h_59fd64a2c1c2432ef6f8f6c8ad1ab9e1} Flush the processor write buffers to memory. \begin{Desc} \item[Returns:]Status, OK or ERROR if this operation is not supported. supported on the target architecture.\end{Desc} Forces the output (write) buffers to write their contents to RAM. A cache flush may have forced the data into the write buffers, but then the buffers need to be flushed to RAM to maintain coherency. \hypertarget{CACHE_8h_20cea7d7dd39c2829b880e106080f0d7}{ \index{CACHE.h@{CACHE.h}!CACHE\_\-unlock@{CACHE\_\-unlock}} \index{CACHE\_\-unlock@{CACHE\_\-unlock}!CACHE.h@{CACHE.h}} \subsubsection[{CACHE\_\-unlock}]{\setlength{\rightskip}{0pt plus 5cm}int CACHE\_\-unlock ({\bf CACHE\_\-type} {\em type}, \/ void $\ast$ {\em address}, \/ int {\em nbytes})}} \label{CACHE_8h_20cea7d7dd39c2829b880e106080f0d7} Unlock all or part of a specified cache. \begin{Desc} \item[Parameters:] \begin{description} \item[{\em type}]The cache type, i.e. one of {\em CACHE\_\-K\_\-DATA\/} or {\em CACHE\_\-K\_\-INSTRUCTION\/}. \item[{\em address}]The address to start locking at \item[{\em nbytes}]The number of bytes to lock \end{description} \end{Desc} \begin{Desc} \item[Returns:]Status, OK, unless the cache type is invalid or not supported on the target architecture.\end{Desc} Locks entries in the specified cache. Currently only the MCP750 supports cache locking.