\hypertarget{UNIV_8h}{ \section{UNIV.h File Reference} \label{UNIV_8h}\index{UNIV.h@{UNIV.h}} } Universe II Utilities, Interface. \subsection*{Data Structures} \begin{CompactItemize} \item struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} \begin{CompactList}\small\item\em Universe II DMA Control Packet.\item\end{CompactList}\end{CompactItemize} \subsection*{Defines} \begin{CompactItemize} \item \hypertarget{UNIV_8h_a0}{ \index{UNIV_K_DCTL_LD64EN@{UNIV\_\-K\_\-DCTL\_\-LD64EN}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_LD64EN@{UNIV\_\-K\_\-DCTL\_\-LD64EN}} \#define \hyperlink{UNIV_8h_a0}{UNIV\_\-K\_\-DCTL\_\-LD64EN}\ ( 1 $<$$<$ UNIV\_\-V\_\-DCTL\_\-LD64EN)} \label{UNIV_8h_a0} \begin{CompactList}\small\item\em Enable PCI 64 Bit Bus Transactions.\item\end{CompactList}\item \hypertarget{UNIV_8h_a1}{ \index{UNIV_K_DCTL_VCT_NO_BLT@{UNIV\_\-K\_\-DCTL\_\-VCT\_\-NO\_\-BLT}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_VCT_NO_BLT@{UNIV\_\-K\_\-DCTL\_\-VCT\_\-NO\_\-BLT}} \#define \hyperlink{UNIV_8h_a1}{UNIV\_\-K\_\-DCTL\_\-VCT\_\-NO\_\-BLT}\ ( 0 $<$$<$ UNIV\_\-V\_\-DCTL\_\-VCT)} \label{UNIV_8h_a1} \begin{CompactList}\small\item\em Disallow BLT's.\item\end{CompactList}\item \hypertarget{UNIV_8h_a2}{ \index{UNIV_K_DCTL_VCT_BLT@{UNIV\_\-K\_\-DCTL\_\-VCT\_\-BLT}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_VCT_BLT@{UNIV\_\-K\_\-DCTL\_\-VCT\_\-BLT}} \#define \hyperlink{UNIV_8h_a2}{UNIV\_\-K\_\-DCTL\_\-VCT\_\-BLT}\ ( 1 $<$$<$ UNIV\_\-V\_\-DCTL\_\-VCT)} \label{UNIV_8h_a2} \begin{CompactList}\small\item\em Allow BLT's.\item\end{CompactList}\item \hypertarget{UNIV_8h_a3}{ \index{UNIV_K_DCTL_SUPER_USER@{UNIV\_\-K\_\-DCTL\_\-SUPER\_\-USER}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_SUPER_USER@{UNIV\_\-K\_\-DCTL\_\-SUPER\_\-USER}} \#define \hyperlink{UNIV_8h_a3}{UNIV\_\-K\_\-DCTL\_\-SUPER\_\-USER}\ (0x00 $<$$<$ UNIV\_\-V\_\-DCTL\_\-SUPER)} \label{UNIV_8h_a3} \begin{CompactList}\small\item\em User AM Code.\item\end{CompactList}\item \hypertarget{UNIV_8h_a4}{ \index{UNIV_K_DCTL_SUPER_SUPER@{UNIV\_\-K\_\-DCTL\_\-SUPER\_\-SUPER}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_SUPER_SUPER@{UNIV\_\-K\_\-DCTL\_\-SUPER\_\-SUPER}} \#define \hyperlink{UNIV_8h_a4}{UNIV\_\-K\_\-DCTL\_\-SUPER\_\-SUPER}\ (0x01 $<$$<$ UNIV\_\-V\_\-DCTL\_\-SUPER)} \label{UNIV_8h_a4} \begin{CompactList}\small\item\em Supervisor AM Code.\item\end{CompactList}\item \hypertarget{UNIV_8h_a5}{ \index{UNIV_K_DCTL_PGM_DATA@{UNIV\_\-K\_\-DCTL\_\-PGM\_\-DATA}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_PGM_DATA@{UNIV\_\-K\_\-DCTL\_\-PGM\_\-DATA}} \#define \hyperlink{UNIV_8h_a5}{UNIV\_\-K\_\-DCTL\_\-PGM\_\-DATA}\ (0x00 $<$$<$ UNIV\_\-V\_\-DCTL\_\-PGM)} \label{UNIV_8h_a5} \begin{CompactList}\small\item\em Data AM Code.\item\end{CompactList}\item \hypertarget{UNIV_8h_a6}{ \index{UNIV_K_DCTL_PGM_PROGRAM@{UNIV\_\-K\_\-DCTL\_\-PGM\_\-PROGRAM}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_PGM_PROGRAM@{UNIV\_\-K\_\-DCTL\_\-PGM\_\-PROGRAM}} \#define \hyperlink{UNIV_8h_a6}{UNIV\_\-K\_\-DCTL\_\-PGM\_\-PROGRAM}\ (0x01 $<$$<$ UNIV\_\-V\_\-DCTL\_\-PGM)} \label{UNIV_8h_a6} \begin{CompactList}\small\item\em Program AM Code.\item\end{CompactList}\item \hypertarget{UNIV_8h_a7}{ \index{UNIV_K_DCTL_VAS_A16@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-A16}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_VAS_A16@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-A16}} \#define \hyperlink{UNIV_8h_a7}{UNIV\_\-K\_\-DCTL\_\-VAS\_\-A16}\ (0x00 $<$$<$ UNIV\_\-V\_\-DCTL\_\-VAS)} \label{UNIV_8h_a7} \begin{CompactList}\small\item\em VME Address Space = A16.\item\end{CompactList}\item \hypertarget{UNIV_8h_a8}{ \index{UNIV_K_DCTL_VAS_A24@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-A24}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_VAS_A24@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-A24}} \#define \hyperlink{UNIV_8h_a8}{UNIV\_\-K\_\-DCTL\_\-VAS\_\-A24}\ (0x01 $<$$<$ UNIV\_\-V\_\-DCTL\_\-VAS)} \label{UNIV_8h_a8} \begin{CompactList}\small\item\em VME Address Space = A24.\item\end{CompactList}\item \hypertarget{UNIV_8h_a9}{ \index{UNIV_K_DCTL_VAS_A32@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-A32}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_VAS_A32@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-A32}} \#define \hyperlink{UNIV_8h_a9}{UNIV\_\-K\_\-DCTL\_\-VAS\_\-A32}\ (0x02 $<$$<$ UNIV\_\-V\_\-DCTL\_\-VAS)} \label{UNIV_8h_a9} \begin{CompactList}\small\item\em VME Address Space = A32.\item\end{CompactList}\item \hypertarget{UNIV_8h_a10}{ \index{UNIV_K_DCTL_VAS_RSVD_3@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-RSVD\_\-3}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_VAS_RSVD_3@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-RSVD\_\-3}} \#define \hyperlink{UNIV_8h_a10}{UNIV\_\-K\_\-DCTL\_\-VAS\_\-RSVD\_\-3}\ (0x03 $<$$<$ UNIV\_\-V\_\-DCTL\_\-VAS)} \label{UNIV_8h_a10} \begin{CompactList}\small\item\em VME Address Space = Reserved.\item\end{CompactList}\item \hypertarget{UNIV_8h_a11}{ \index{UNIV_K_DCTL_VAS_RSVD_4@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-RSVD\_\-4}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_VAS_RSVD_4@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-RSVD\_\-4}} \#define \hyperlink{UNIV_8h_a11}{UNIV\_\-K\_\-DCTL\_\-VAS\_\-RSVD\_\-4}\ (0x04 $<$$<$ UNIV\_\-V\_\-DCTL\_\-VAS)} \label{UNIV_8h_a11} \begin{CompactList}\small\item\em VME Address Space = Reserved.\item\end{CompactList}\item \hypertarget{UNIV_8h_a12}{ \index{UNIV_K_DCTL_VAS_RSVD_5@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-RSVD\_\-5}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_VAS_RSVD_5@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-RSVD\_\-5}} \#define \hyperlink{UNIV_8h_a12}{UNIV\_\-K\_\-DCTL\_\-VAS\_\-RSVD\_\-5}\ (0x05 $<$$<$ UNIV\_\-V\_\-DCTL\_\-VAS)} \label{UNIV_8h_a12} \begin{CompactList}\small\item\em VME Address Space = Reserved.\item\end{CompactList}\item \hypertarget{UNIV_8h_a13}{ \index{UNIV_K_DCTL_VAS_USER1@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-USER1}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_VAS_USER1@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-USER1}} \#define \hyperlink{UNIV_8h_a13}{UNIV\_\-K\_\-DCTL\_\-VAS\_\-USER1}\ (0x06 $<$$<$ UNIV\_\-V\_\-DCTL\_\-VAS)} \label{UNIV_8h_a13} \begin{CompactList}\small\item\em VME Address Space = User 1.\item\end{CompactList}\item \hypertarget{UNIV_8h_a14}{ \index{UNIV_K_DCTL_VAS_USER2@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-USER2}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_VAS_USER2@{UNIV\_\-K\_\-DCTL\_\-VAS\_\-USER2}} \#define \hyperlink{UNIV_8h_a14}{UNIV\_\-K\_\-DCTL\_\-VAS\_\-USER2}\ (0x07 $<$$<$ UNIV\_\-V\_\-DCTL\_\-VAS)} \label{UNIV_8h_a14} \begin{CompactList}\small\item\em VME Address Space = User 2.\item\end{CompactList}\item \hypertarget{UNIV_8h_a15}{ \index{UNIV_K_DCTL_VDW_08@{UNIV\_\-K\_\-DCTL\_\-VDW\_\-08}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_VDW_08@{UNIV\_\-K\_\-DCTL\_\-VDW\_\-08}} \#define \hyperlink{UNIV_8h_a15}{UNIV\_\-K\_\-DCTL\_\-VDW\_\-08}\ (0x00 $<$$<$ UNIV\_\-V\_\-DCTL\_\-VDW)} \label{UNIV_8h_a15} \begin{CompactList}\small\item\em VME Maximum Datawidth = 8 bits.\item\end{CompactList}\item \hypertarget{UNIV_8h_a16}{ \index{UNIV_K_DCTL_VDW_16@{UNIV\_\-K\_\-DCTL\_\-VDW\_\-16}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_VDW_16@{UNIV\_\-K\_\-DCTL\_\-VDW\_\-16}} \#define \hyperlink{UNIV_8h_a16}{UNIV\_\-K\_\-DCTL\_\-VDW\_\-16}\ (0x01 $<$$<$ UNIV\_\-V\_\-DCTL\_\-VDW)} \label{UNIV_8h_a16} \begin{CompactList}\small\item\em VME Maximum Datawidth = 16 bits.\item\end{CompactList}\item \hypertarget{UNIV_8h_a17}{ \index{UNIV_K_DCTL_VDW_32@{UNIV\_\-K\_\-DCTL\_\-VDW\_\-32}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_VDW_32@{UNIV\_\-K\_\-DCTL\_\-VDW\_\-32}} \#define \hyperlink{UNIV_8h_a17}{UNIV\_\-K\_\-DCTL\_\-VDW\_\-32}\ (0x02 $<$$<$ UNIV\_\-V\_\-DCTL\_\-VDW)} \label{UNIV_8h_a17} \begin{CompactList}\small\item\em VME Maximum Datawidth = 32 bits.\item\end{CompactList}\item \hypertarget{UNIV_8h_a18}{ \index{UNIV_K_DCTL_VDW_64@{UNIV\_\-K\_\-DCTL\_\-VDW\_\-64}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_VDW_64@{UNIV\_\-K\_\-DCTL\_\-VDW\_\-64}} \#define \hyperlink{UNIV_8h_a18}{UNIV\_\-K\_\-DCTL\_\-VDW\_\-64}\ (0x03 $<$$<$ UNIV\_\-V\_\-DCTL\_\-VDW)} \label{UNIV_8h_a18} \begin{CompactList}\small\item\em VME Maximum Datawidth = 64 bits.\item\end{CompactList}\item \hypertarget{UNIV_8h_a19}{ \index{UNIV_K_DCTL_L2V_V2L@{UNIV\_\-K\_\-DCTL\_\-L2V\_\-V2L}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_L2V_V2L@{UNIV\_\-K\_\-DCTL\_\-L2V\_\-V2L}} \#define \hyperlink{UNIV_8h_a19}{UNIV\_\-K\_\-DCTL\_\-L2V\_\-V2L}\ (0x00 $<$$<$ UNIV\_\-V\_\-DCTL\_\-L2V)} \label{UNIV_8h_a19} \begin{CompactList}\small\item\em Transfer direction is PCI =$>$ VME.\item\end{CompactList}\item \hypertarget{UNIV_8h_a20}{ \index{UNIV_K_DCTL_L2V_L2V@{UNIV\_\-K\_\-DCTL\_\-L2V\_\-L2V}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_K_DCTL_L2V_L2V@{UNIV\_\-K\_\-DCTL\_\-L2V\_\-L2V}} \#define \hyperlink{UNIV_8h_a20}{UNIV\_\-K\_\-DCTL\_\-L2V\_\-L2V}\ (0x01 $<$$<$ UNIV\_\-V\_\-DCTL\_\-V2L)} \label{UNIV_8h_a20} \begin{CompactList}\small\item\em Transfer direction is VME =$>$ PCI.\item\end{CompactList}\end{CompactItemize} \subsection*{Typedefs} \begin{CompactItemize} \item typedef \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} $\ast$ \hyperlink{UNIV_8h_a21}{UNIV\_\-dcpp} \begin{CompactList}\small\item\em Typedef for a pointer to struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp}.\item\end{CompactList}\item \hypertarget{UNIV_8h_a22}{ \index{UNIV_dcp@{UNIV\_\-dcp}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_dcp@{UNIV\_\-dcp}} typedef \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} \hyperlink{UNIV_8h_a22}{UNIV\_\-dcp}} \label{UNIV_8h_a22} \begin{CompactList}\small\item\em Typedef for struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp}.\item\end{CompactList}\item typedef void($\ast$ \hyperlink{UNIV_8h_a23}{UNIV\_\-isr} )(void $\ast$parameter) \begin{CompactList}\small\item\em Signature for a UNIV interrupt service routine.\item\end{CompactList}\item typedef enum \hyperlink{UNIV_8h_a177}{\_\-UNIV\_\-V\_\-dctl} \hyperlink{UNIV_8h_a24}{UNIV\_\-V\_\-dctl} \begin{CompactList}\small\item\em Typedef for enum \_\-UNIV\_\-V\_\-dctl.\item\end{CompactList}\item \hypertarget{UNIV_8h_a25}{ \index{UNIV_S_dctl@{UNIV\_\-S\_\-dctl}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_dctl@{UNIV\_\-S\_\-dctl}} typedef enum \hyperlink{UNIV_8h_a178}{\_\-UNIV\_\-S\_\-dctl} \hyperlink{UNIV_8h_a25}{UNIV\_\-S\_\-dctl}} \label{UNIV_8h_a25} \begin{CompactList}\small\item\em Typedef for enum \_\-UNIV\_\-S\_\-dctl.\item\end{CompactList}\item \hypertarget{UNIV_8h_a26}{ \index{UNIV_M_dctl@{UNIV\_\-M\_\-dctl}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_dctl@{UNIV\_\-M\_\-dctl}} typedef enum \hyperlink{UNIV_8h_a179}{\_\-UNIV\_\-M\_\-dctl} \hyperlink{UNIV_8h_a26}{UNIV\_\-M\_\-dctl}} \label{UNIV_8h_a26} \begin{CompactList}\small\item\em Typedef for enum \_\-UNIV\_\-M\_\-dctl.\item\end{CompactList}\item typedef enum \hyperlink{UNIV_8h_a180}{\_\-UNIV\_\-V\_\-dgcs} \hyperlink{UNIV_8h_a27}{UNIV\_\-V\_\-dgcs} \begin{CompactList}\small\item\em Typedef for enum \_\-UNIV\_\-V\_\-dgcs.\item\end{CompactList}\item \hypertarget{UNIV_8h_a28}{ \index{UNIV_S_dgcs@{UNIV\_\-S\_\-dgcs}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_dgcs@{UNIV\_\-S\_\-dgcs}} typedef enum \hyperlink{UNIV_8h_a181}{\_\-UNIV\_\-S\_\-dgcs} \hyperlink{UNIV_8h_a28}{UNIV\_\-S\_\-dgcs}} \label{UNIV_8h_a28} \begin{CompactList}\small\item\em Typedef for enum \_\-UNIV\_\-S\_\-dgcs.\item\end{CompactList}\item \hypertarget{UNIV_8h_a29}{ \index{UNIV_M_dgcs@{UNIV\_\-M\_\-dgcs}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_dgcs@{UNIV\_\-M\_\-dgcs}} typedef enum \hyperlink{UNIV_8h_a182}{\_\-UNIV\_\-M\_\-dgcs} \hyperlink{UNIV_8h_a29}{UNIV\_\-M\_\-dgcs}} \label{UNIV_8h_a29} \begin{CompactList}\small\item\em Typedef for enum \_\-UNIV\_\-S\_\-dgcs.\item\end{CompactList}\end{CompactItemize} \subsection*{Enumerations} \begin{CompactItemize} \item enum \hyperlink{UNIV_8h_a177}{\_\-UNIV\_\-V\_\-dctl} \{ \hyperlink{UNIV_8h_a177a30}{UNIV\_\-V\_\-DCTL\_\-RSVD\_\-0} = 6, \hyperlink{UNIV_8h_a177a31}{UNIV\_\-V\_\-DCTL\_\-LD64EN} = 7, \hyperlink{UNIV_8h_a177a32}{UNIV\_\-V\_\-DCTL\_\-VCT} = 8, \hyperlink{UNIV_8h_a177a33}{UNIV\_\-V\_\-DCTL\_\-RSVD\_\-1} = 9, \hyperlink{UNIV_8h_a177a34}{UNIV\_\-V\_\-DCTL\_\-SUPER} = 12, \hyperlink{UNIV_8h_a177a35}{UNIV\_\-V\_\-DCTL\_\-PGM} = 14, \hyperlink{UNIV_8h_a177a36}{UNIV\_\-V\_\-DCTL\_\-VAS} = 16, \hyperlink{UNIV_8h_a177a37}{UNIV\_\-V\_\-DCTL\_\-RSVD\_\-2} = 19, \hyperlink{UNIV_8h_a177a38}{UNIV\_\-V\_\-DCTL\_\-VDW} = 22, \hyperlink{UNIV_8h_a177a39}{UNIV\_\-V\_\-DCTL\_\-RSVD\_\-3} = 24, \hyperlink{UNIV_8h_a177a40}{UNIV\_\-V\_\-DCTL\_\-L2V} = 31 \} \begin{CompactList}\small\item\em Gives the number of bits to shift needed to right justify the bits field in the DCTL control word.\item\end{CompactList}\item enum \hyperlink{UNIV_8h_a178}{\_\-UNIV\_\-S\_\-dctl} \{ \hyperlink{UNIV_8h_a178a41}{UNIV\_\-S\_\-DCTL\_\-RSVD\_\-0} = 7, \hyperlink{UNIV_8h_a178a42}{UNIV\_\-S\_\-DCTL\_\-LD64EN} = 1, \hyperlink{UNIV_8h_a178a43}{UNIV\_\-S\_\-DCTL\_\-VCT} = 1, \hyperlink{UNIV_8h_a178a44}{UNIV\_\-S\_\-DCTL\_\-RSVD\_\-1} = 3, \hyperlink{UNIV_8h_a178a45}{UNIV\_\-S\_\-DCTL\_\-SUPER} = 3, \hyperlink{UNIV_8h_a178a46}{UNIV\_\-S\_\-DCTL\_\-PGM} = 2, \hyperlink{UNIV_8h_a178a47}{UNIV\_\-S\_\-DCTL\_\-VAS} = 3, \hyperlink{UNIV_8h_a178a48}{UNIV\_\-S\_\-DCTL\_\-RSVD\_\-2} = 3, \hyperlink{UNIV_8h_a178a49}{UNIV\_\-S\_\-DCTL\_\-VDW} = 2, \hyperlink{UNIV_8h_a178a50}{UNIV\_\-S\_\-DCTL\_\-RSVD\_\-3} = 7, \hyperlink{UNIV_8h_a178a51}{UNIV\_\-S\_\-DCTL\_\-L2V} = 1 \} \begin{CompactList}\small\item\em Gives the size of each of the bit fields in the DCTL control word.\item\end{CompactList}\item enum \hyperlink{UNIV_8h_a179}{\_\-UNIV\_\-M\_\-dctl} \{ \hyperlink{UNIV_8h_a179a52}{UNIV\_\-M\_\-DCTL\_\-RSVD\_\-0} = 0x0000007E, \hyperlink{UNIV_8h_a179a53}{UNIV\_\-M\_\-DCTL\_\-LD64EN} = 0x00000080, \hyperlink{UNIV_8h_a179a54}{UNIV\_\-M\_\-DCTL\_\-VCT} = 0x00000100, \hyperlink{UNIV_8h_a179a55}{UNIV\_\-M\_\-DCTL\_\-RSVD\_\-1} = 0x00000E00, \hyperlink{UNIV_8h_a179a56}{UNIV\_\-M\_\-DCTL\_\-SUPER} = 0x00003000, \hyperlink{UNIV_8h_a179a57}{UNIV\_\-M\_\-DCTL\_\-PGM} = 0x0000C000, \hyperlink{UNIV_8h_a179a58}{UNIV\_\-M\_\-DCTL\_\-VAS} = 0x00070000, \hyperlink{UNIV_8h_a179a59}{UNIV\_\-M\_\-DCTL\_\-RSVD\_\-2} = 0x00380000, \hyperlink{UNIV_8h_a179a60}{UNIV\_\-M\_\-DCTL\_\-VDW} = 0x00C00000, \hyperlink{UNIV_8h_a179a61}{UNIV\_\-M\_\-DCTL\_\-RSVD\_\-3} = 0x7F000000, \hyperlink{UNIV_8h_a179a62}{UNIV\_\-M\_\-DCTL\_\-L2V} = 0x80000000 \} \begin{CompactList}\small\item\em Gives in place extraction masks for each of the bit fields in the DCTL control word.\item\end{CompactList}\item enum \hyperlink{UNIV_8h_a180}{\_\-UNIV\_\-V\_\-dgcs} \{ \hyperlink{UNIV_8h_a180a63}{UNIV\_\-V\_\-DGCS\_\-INT\_\-P\_\-ERR} = 0, \hyperlink{UNIV_8h_a180a64}{UNIV\_\-V\_\-DGCS\_\-INT\_\-VERR} = 1, \hyperlink{UNIV_8h_a180a65}{UNIV\_\-V\_\-DGCS\_\-INT\_\-LERR} = 2, \hyperlink{UNIV_8h_a180a66}{UNIV\_\-V\_\-DGCS\_\-INT\_\-DONE} = 3, \hyperlink{UNIV_8h_a180a67}{UNIV\_\-V\_\-DGCS\_\-INT\_\-RSVD4} = 4, \hyperlink{UNIV_8h_a180a68}{UNIV\_\-V\_\-DGCS\_\-INT\_\-HALT} = 5, \hyperlink{UNIV_8h_a180a69}{UNIV\_\-V\_\-DGCS\_\-INT\_\-STOP} = 6, \hyperlink{UNIV_8h_a180a70}{UNIV\_\-V\_\-DGCS\_\-INT\_\-RSVD7} = 7, \hyperlink{UNIV_8h_a180a71}{UNIV\_\-V\_\-DGCS\_\-P\_\-ERR} = 8, \hyperlink{UNIV_8h_a180a72}{UNIV\_\-V\_\-DGCS\_\-VERR} = 9, \hyperlink{UNIV_8h_a180a73}{UNIV\_\-V\_\-DGCS\_\-LERR} = 10, \hyperlink{UNIV_8h_a180a74}{UNIV\_\-V\_\-DGCS\_\-DONE} = 11, \hyperlink{UNIV_8h_a180a75}{UNIV\_\-V\_\-DGCS\_\-RSVD12} = 12, \hyperlink{UNIV_8h_a180a76}{UNIV\_\-V\_\-DGCS\_\-HALT} = 13, \hyperlink{UNIV_8h_a180a77}{UNIV\_\-V\_\-DGCS\_\-STOP} = 14, \hyperlink{UNIV_8h_a180a78}{UNIV\_\-V\_\-DGCS\_\-ACT} = 15, \hyperlink{UNIV_8h_a180a79}{UNIV\_\-V\_\-DGCS\_\-VOFF} = 16, \hyperlink{UNIV_8h_a180a80}{UNIV\_\-V\_\-DGCS\_\-VON} = 20, \hyperlink{UNIV_8h_a180a81}{UNIV\_\-V\_\-DGCS\_\-RSVD23} = 23, \hyperlink{UNIV_8h_a180a82}{UNIV\_\-V\_\-DGCS\_\-RSVD24} = 24, \hyperlink{UNIV_8h_a180a83}{UNIV\_\-V\_\-DGCS\_\-CHAIN} = 27, \hyperlink{UNIV_8h_a180a84}{UNIV\_\-V\_\-DGCS\_\-RSVD28} = 28, \hyperlink{UNIV_8h_a180a85}{UNIV\_\-V\_\-DGCS\_\-HALT\_\-REQ} = 29, \hyperlink{UNIV_8h_a180a86}{UNIV\_\-V\_\-DGCS\_\-STOP\_\-REQ} = 30, \hyperlink{UNIV_8h_a180a87}{UNIV\_\-V\_\-DGCS\_\-GO} = 31, \hyperlink{UNIV_8h_a180a88}{UNIV\_\-V\_\-DGCS\_\-INT\_\-ENB\_\-ERR} = 0, \hyperlink{UNIV_8h_a180a89}{UNIV\_\-V\_\-DGCS\_\-INT\_\-ENB\_\-SUC} = 3, \hyperlink{UNIV_8h_a180a90}{UNIV\_\-V\_\-DGCS\_\-INT\_\-ENB\_\-ALL} = 0, \hyperlink{UNIV_8h_a180a91}{UNIV\_\-V\_\-DGCS\_\-INT\_\-STS\_\-ERR} = 8, \hyperlink{UNIV_8h_a180a92}{UNIV\_\-V\_\-DGCS\_\-INT\_\-STS\_\-SUC} = 11, \hyperlink{UNIV_8h_a180a93}{UNIV\_\-V\_\-DGCS\_\-INT\_\-STS\_\-ALL} = 8, \hyperlink{UNIV_8h_a180a94}{UNIV\_\-V\_\-DGCS\_\-STS\_\-ALL} = 8 \} \begin{CompactList}\small\item\em Maps out the DMA General Control/Status Register.\item\end{CompactList}\item enum \hyperlink{UNIV_8h_a181}{\_\-UNIV\_\-S\_\-dgcs} \{ \hyperlink{UNIV_8h_a181a95}{UNIV\_\-S\_\-DGCS\_\-INT\_\-P\_\-ERR} = 1, \hyperlink{UNIV_8h_a181a96}{UNIV\_\-S\_\-DGCS\_\-INT\_\-VERR} = 1, \hyperlink{UNIV_8h_a181a97}{UNIV\_\-S\_\-DGCS\_\-INT\_\-LERR} = 1, \hyperlink{UNIV_8h_a181a98}{UNIV\_\-S\_\-DGCS\_\-INT\_\-RSVD4} = 1, \hyperlink{UNIV_8h_a181a99}{UNIV\_\-S\_\-DGCS\_\-INT\_\-DONE} = 1, \hyperlink{UNIV_8h_a181a100}{UNIV\_\-S\_\-DGCS\_\-INT\_\-HALT} = 1, \hyperlink{UNIV_8h_a181a101}{UNIV\_\-S\_\-DGCS\_\-INT\_\-STOP} = 1, \hyperlink{UNIV_8h_a181a102}{UNIV\_\-S\_\-DGCS\_\-INT\_\-RSVD7} = 1, \hyperlink{UNIV_8h_a181a103}{UNIV\_\-S\_\-DGCS\_\-P\_\-ERR} = 1, \hyperlink{UNIV_8h_a181a104}{UNIV\_\-S\_\-DGCS\_\-VERR} = 1, \hyperlink{UNIV_8h_a181a105}{UNIV\_\-S\_\-DGCS\_\-LERR} = 1, \hyperlink{UNIV_8h_a181a106}{UNIV\_\-S\_\-DGCS\_\-DONE} = 1, \hyperlink{UNIV_8h_a181a107}{UNIV\_\-S\_\-DGCS\_\-RSVD12} = 1, \hyperlink{UNIV_8h_a181a108}{UNIV\_\-S\_\-DGCS\_\-HALT} = 1, \hyperlink{UNIV_8h_a181a109}{UNIV\_\-S\_\-DGCS\_\-STOP} = 1, \hyperlink{UNIV_8h_a181a110}{UNIV\_\-S\_\-DGCS\_\-ACT} = 1, \hyperlink{UNIV_8h_a181a111}{UNIV\_\-S\_\-DGCS\_\-VOFF} = 4, \hyperlink{UNIV_8h_a181a112}{UNIV\_\-S\_\-DGCS\_\-VON} = 3, \hyperlink{UNIV_8h_a181a113}{UNIV\_\-S\_\-DGCS\_\-RSVD23} = 1, \hyperlink{UNIV_8h_a181a114}{UNIV\_\-S\_\-DGCS\_\-RSVD24} = 3, \hyperlink{UNIV_8h_a181a115}{UNIV\_\-S\_\-DGCS\_\-CHAIN} = 1, \hyperlink{UNIV_8h_a181a116}{UNIV\_\-S\_\-DGCS\_\-RSVD28} = 1, \hyperlink{UNIV_8h_a181a117}{UNIV\_\-S\_\-DGCS\_\-HALT\_\-REQ} = 1, \hyperlink{UNIV_8h_a181a118}{UNIV\_\-S\_\-DGCS\_\-STOP\_\-REQ} = 1, \hyperlink{UNIV_8h_a181a119}{UNIV\_\-S\_\-DGCS\_\-GO} = 1, \hyperlink{UNIV_8h_a181a120}{UNIV\_\-S\_\-DGCS\_\-INT\_\-ENB\_\-ERR} = 3, \hyperlink{UNIV_8h_a181a121}{UNIV\_\-S\_\-DGCS\_\-INT\_\-ENB\_\-SUC} = 4, \hyperlink{UNIV_8h_a181a122}{UNIV\_\-S\_\-DGCS\_\-INT\_\-ENB\_\-ALL} = 7, \hyperlink{UNIV_8h_a181a123}{UNIV\_\-S\_\-DGCS\_\-INT\_\-STS\_\-ERR} = 3, \hyperlink{UNIV_8h_a181a124}{UNIV\_\-S\_\-DGCS\_\-INT\_\-STS\_\-SUC} = 4, \hyperlink{UNIV_8h_a181a125}{UNIV\_\-S\_\-DGCS\_\-INT\_\-STS\_\-ALL} = 3, \hyperlink{UNIV_8h_a181a126}{UNIV\_\-S\_\-DGCS\_\-STS\_\-ALL} = 8 \} \begin{CompactList}\small\item\em Maps out the sizes of bit fields in the DMA General Control/Status Register.\item\end{CompactList}\item enum \hyperlink{UNIV_8h_a182}{\_\-UNIV\_\-M\_\-dgcs} \{ \hyperlink{UNIV_8h_a182a127}{UNIV\_\-M\_\-DGCS\_\-INT\_\-P\_\-ERR} = (1$<$$<$UNIV\_\-V\_\-DGCS\_\-INT\_\-P\_\-ERR), \hyperlink{UNIV_8h_a182a128}{UNIV\_\-M\_\-DGCS\_\-INT\_\-VERR} = (1$<$$<$UNIV\_\-V\_\-DGCS\_\-INT\_\-VERR ), \hyperlink{UNIV_8h_a182a129}{UNIV\_\-M\_\-DGCS\_\-INT\_\-LERR} = (1$<$$<$UNIV\_\-V\_\-DGCS\_\-INT\_\-LERR ), \hyperlink{UNIV_8h_a182a130}{UNIV\_\-M\_\-DGCS\_\-INT\_\-DONE} = (1$<$$<$UNIV\_\-V\_\-DGCS\_\-INT\_\-DONE ), \hyperlink{UNIV_8h_a182a131}{UNIV\_\-M\_\-DGCS\_\-INT\_\-RSVD4} = (1$<$$<$UNIV\_\-V\_\-DGCS\_\-INT\_\-RSVD4), \hyperlink{UNIV_8h_a182a132}{UNIV\_\-M\_\-DGCS\_\-INT\_\-HALT} = (1$<$$<$UNIV\_\-V\_\-DGCS\_\-INT\_\-HALT ), \hyperlink{UNIV_8h_a182a133}{UNIV\_\-M\_\-DGCS\_\-INT\_\-STOP} = (1$<$$<$UNIV\_\-V\_\-DGCS\_\-INT\_\-STOP ), {\bf UNIV\_\-M\_\-DGCS\_\-INT\_\-RSVD7} = (1$<$$<$UNIV\_\-V\_\-DGCS\_\-INT\_\-RSVD7), \hyperlink{UNIV_8h_a182a135}{UNIV\_\-M\_\-DGCS\_\-P\_\-ERR} = (1 $<$$<$ UNIV\_\-V\_\-DGCS\_\-P\_\-ERR), \hyperlink{UNIV_8h_a182a136}{UNIV\_\-M\_\-DGCS\_\-VERR} = (1 $<$$<$ UNIV\_\-V\_\-DGCS\_\-VERR ), \hyperlink{UNIV_8h_a182a137}{UNIV\_\-M\_\-DGCS\_\-LERR} = (1 $<$$<$ UNIV\_\-V\_\-DGCS\_\-LERR ), \hyperlink{UNIV_8h_a182a138}{UNIV\_\-M\_\-DGCS\_\-DONE} = (1 $<$$<$ UNIV\_\-V\_\-DGCS\_\-DONE ), \hyperlink{UNIV_8h_a182a139}{UNIV\_\-M\_\-DGCS\_\-HALT} = (1 $<$$<$ UNIV\_\-V\_\-DGCS\_\-HALT ), \hyperlink{UNIV_8h_a182a140}{UNIV\_\-M\_\-DGCS\_\-STOP} = (1 $<$$<$ UNIV\_\-V\_\-DGCS\_\-STOP ), \hyperlink{UNIV_8h_a182a141}{UNIV\_\-M\_\-DGCS\_\-ACT} = (1 $<$$<$ UNIV\_\-V\_\-DGCS\_\-ACT ), \hyperlink{UNIV_8h_a182a142}{UNIV\_\-M\_\-DGCS\_\-VOFF} = (0xf$<$$<$UNIV\_\-V\_\-DGCS\_\-VOFF ), \hyperlink{UNIV_8h_a182a143}{UNIV\_\-M\_\-DGCS\_\-VON} = (0x7$<$$<$UNIV\_\-V\_\-DGCS\_\-VOFF ), \hyperlink{UNIV_8h_a182a144}{UNIV\_\-M\_\-DGCS\_\-RSVD23} = (1 $<$$<$UNIV\_\-V\_\-DGCS\_\-RSVD23), \hyperlink{UNIV_8h_a182a145}{UNIV\_\-M\_\-DGCS\_\-RSVD24} = (0x7$<$$<$UNIV\_\-V\_\-DGCS\_\-RSVD24), \hyperlink{UNIV_8h_a182a146}{UNIV\_\-M\_\-DGCS\_\-CHAIN} = (1 $<$$<$UNIV\_\-V\_\-DGCS\_\-CHAIN), \hyperlink{UNIV_8h_a182a147}{UNIV\_\-M\_\-DGCS\_\-RSVD28} = (1 $<$$<$UNIV\_\-V\_\-DGCS\_\-RSVD28), \hyperlink{UNIV_8h_a182a148}{UNIV\_\-M\_\-DGCS\_\-HALT\_\-REQ} = (1$<$$<$UNIV\_\-V\_\-DGCS\_\-HALT\_\-REQ), \hyperlink{UNIV_8h_a182a149}{UNIV\_\-M\_\-DGCS\_\-STOP\_\-REQ} = (1$<$$<$UNIV\_\-V\_\-DGCS\_\-STOP\_\-REQ), \hyperlink{UNIV_8h_a182a150}{UNIV\_\-M\_\-DGCS\_\-GO} = (1 $<$$<$UNIV\_\-V\_\-DGCS\_\-GO), \hyperlink{UNIV_8h_a182a151}{UNIV\_\-M\_\-DGCS\_\-INT\_\-ENB\_\-ERR}, \hyperlink{UNIV_8h_a182a152}{UNIV\_\-M\_\-DGCS\_\-INT\_\-ENB\_\-SUC}, \hyperlink{UNIV_8h_a182a153}{UNIV\_\-M\_\-DGCS\_\-INT\_\-ENB\_\-ALL}, \hyperlink{UNIV_8h_a182a154}{UNIV\_\-M\_\-DGCS\_\-INT\_\-STS\_\-ERR}, \hyperlink{UNIV_8h_a182a155}{UNIV\_\-M\_\-DGCS\_\-INT\_\-STS\_\-SUC}, \hyperlink{UNIV_8h_a182a156}{UNIV\_\-M\_\-DGCS\_\-INT\_\-STS\_\-ALL}, \hyperlink{UNIV_8h_a182a157}{UNIV\_\-M\_\-DGCS\_\-STS\_\-ALL} = (UNIV\_\-M\_\-DGCS\_\-INT\_\-STS\_\-ALL $|$ UNIV\_\-M\_\-DGCS\_\-ACT) \} \begin{CompactList}\small\item\em Maps out in place masks of the bit fields in the DMA General Control/Status Register.\item\end{CompactList}\end{CompactItemize} \subsection*{Functions} \begin{CompactItemize} \item \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} $\ast$ \hyperlink{UNIV_8h_a158}{UNIV\_\-DCPP\_\-read} (void) \begin{CompactList}\small\item\em Reads the DCPP register, (Command Packet Pointer).\item\end{CompactList}\item void \hyperlink{UNIV_8h_a159}{UNIV\_\-DCPP\_\-write} (const struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} $\ast$cmd) \begin{CompactList}\small\item\em Write the DCPP register with the head of a DMA linked list.\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8h_a160}{UNIV\_\-DTBC\_\-read} (void) \begin{CompactList}\small\item\em Reads the DTBC register, (Transfer Byte Count).\item\end{CompactList}\item void \hyperlink{UNIV_8h_a161}{UNIV\_\-DTBC\_\-write} (unsigned int byte\_\-count) \begin{CompactList}\small\item\em Writes the DTBC register, (Transfer Byte Count).\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8h_a162}{UNIV\_\-DGCS\_\-read} (void) \begin{CompactList}\small\item\em Reads the DGCS register, (General Control/Status Register.\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8h_a163}{UNIV\_\-go} (void) \begin{CompactList}\small\item\em Initiates a start on on a DMA operation by hitting to GO bit in the DGCS register.\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8h_a164}{UNIV\_\-request\_\-halt} (void) \begin{CompactList}\small\item\em Request a halt on an ongoing DMA operation.\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8h_a165}{UNIV\_\-request\_\-stop} (void) \begin{CompactList}\small\item\em Request a stop on an ongoing DMA operation.\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8h_a166}{UNIV\_\-DGCS\_\-bclr} (unsigned int bits\_\-to\_\-clr) \begin{CompactList}\small\item\em Clears the specified bits in the DGCS register, (General Control/Status Register).\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8h_a167}{UNIV\_\-DGCS\_\-bmod} (unsigned int bits\_\-to\_\-mod, unsigned int value) \begin{CompactList}\small\item\em Modifies a selected set of bits in the DGCS register.\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8h_a168}{UNIV\_\-DGCS\_\-bset} (unsigned int bits\_\-to\_\-set) \begin{CompactList}\small\item\em Sets the specified bits in the DGCS register.\item\end{CompactList}\item void \hyperlink{UNIV_8h_a169}{UNIV\_\-DGCS\_\-write} (unsigned int value) \begin{CompactList}\small\item\em Writes the DGCS register, (General Control/Status Register).\item\end{CompactList}\item int \hyperlink{UNIV_8h_a170}{UNIV\_\-int\_\-connect} (unsigned int which, \hyperlink{UNIV_8h_a23}{UNIV\_\-isr} service, void $\ast$parameter) \begin{CompactList}\small\item\em Connects a ISR routine to service the UNIVERSET II interrupts.\item\end{CompactList}\item int \hyperlink{UNIV_8h_a171}{UNIV\_\-int\_\-enable} (void) \begin{CompactList}\small\item\em Enables delivery of interrupts from the UNIVERSE II.\item\end{CompactList}\item int \hyperlink{UNIV_8h_a172}{UNIV\_\-int\_\-disable} (void) \begin{CompactList}\small\item\em Disables delivery of interrupts from the UNIVERSE II.\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8h_a173}{UNIV\_\-bus\_\-master\_\-set} (void) \begin{CompactList}\small\item\em Ensures the UNIVERSE II is a PCI bus master.\item\end{CompactList}\item void \hyperlink{UNIV_8h_a174}{UNIV\_\-dcp\_\-array\_\-init} (struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} $\ast$dcpp, int cnt) \begin{CompactList}\small\item\em Initializes an array of Universe DMA Command packets to form a circular list. Only the link field is filled in.\item\end{CompactList}\item void \hyperlink{UNIV_8h_a175}{UNIV\_\-dcp\_\-complete} (struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} $\ast$dcpp, unsigned int dctl, unsigned int vme\-Adr, unsigned char $\ast$dst\-Adr, int nbytes) \begin{CompactList}\small\item\em Complete the DMA Command Packet, ie finishes the job UNIV\_\-dcp\_\-array\_\-init started.\item\end{CompactList}\item void \hyperlink{UNIV_8h_a176}{UNIV\_\-go\_\-at} (struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} $\ast$dcpp) \begin{CompactList}\small\item\em This initiates a chain UNIV transfer by the Universe at the specified command head.\item\end{CompactList}\end{CompactItemize} \subsection{Detailed Description} Universe II Utilities, Interface. \begin{Desc} \item[Author: ]\par JJRussell - \href{mailto:russell@slac.stanford.edu}{\tt russell@slac.stanford.edu}\end{Desc} \subsection{Typedef Documentation} \hypertarget{UNIV_8h_a21}{ \index{UNIV.h@{UNIV.h}!UNIV_dcpp@{UNIV\_\-dcpp}} \index{UNIV_dcpp@{UNIV\_\-dcpp}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-dcpp]{\setlength{\rightskip}{0pt plus 5cm}UNIV\_\-dcpp}} \label{UNIV_8h_a21} Typedef for a pointer to struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp}. Defines the DMA Control Packet. These packets can be linked together to form a chained DMA operation, which is seeded in the Universe's DCPP control register. \hypertarget{UNIV_8h_a23}{ \index{UNIV.h@{UNIV.h}!UNIV_isr@{UNIV\_\-isr}} \index{UNIV_isr@{UNIV\_\-isr}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-isr]{\setlength{\rightskip}{0pt plus 5cm}UNIV\_\-isr}} \label{UNIV_8h_a23} Signature for a UNIV interrupt service routine. A Universe interrupt is serviced by a callback routine with this signature. \footnotesize\begin{verbatim} void (*isr)(void *parameter) \end{verbatim}\normalsize \hypertarget{UNIV_8h_a24}{ \index{UNIV.h@{UNIV.h}!UNIV_V_dctl@{UNIV\_\-V\_\-dctl}} \index{UNIV_V_dctl@{UNIV\_\-V\_\-dctl}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-V\_\-dctl]{\setlength{\rightskip}{0pt plus 5cm}UNIV\_\-V\_\-dctl}} \label{UNIV_8h_a24} Typedef for enum \_\-UNIV\_\-V\_\-dctl. The UNIVERSE control word contains bit fields which control the transfer of data between the PCI and VME busses. In addition to definitions of the bare bit fields, several useful collections are defined. These are confined to the interrupt and status bits. There are basically two sets of the same bits, one set for enabling interrupt sources and one set of reporting/clearing interrupt status. Each set is confined to a byte, the enabling set in the least significant byte and the reporting/clearing set in the next byte out. These sets are referenced by UNIV\_\-x\_\-DGCS\_\-INT\_\-ENB\_\-xxx and UNIV\_\-x\_\-DGCS\_\-INT\_\-STS\_\-xxx. Each of these sets are broken into two sets, a set which deal with error conditions and a set that deal with normal (expected, like DMA complete) conditions. These are referenced by the symbols with \_\-ERR\_\- and \_\-SUC\_\- in their names. \begin{Desc} \item[Warning: ]\par The narrative descriptions of the bit fields where lifted straight out of the UNIVERSE II User Manual. That manual serves as the ultimate source of the information. An descrepancies between this documentation and the documentation in the UNIVERSE II User Manual is always resolved in favor of UNIVERSE II User Manual. \end{Desc} \hypertarget{UNIV_8h_a27}{ \index{UNIV.h@{UNIV.h}!UNIV_V_dgcs@{UNIV\_\-V\_\-dgcs}} \index{UNIV_V_dgcs@{UNIV\_\-V\_\-dgcs}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-V\_\-dgcs]{\setlength{\rightskip}{0pt plus 5cm}UNIV\_\-V\_\-dgcs}} \label{UNIV_8h_a27} Typedef for enum \_\-UNIV\_\-V\_\-dgcs. The UNIVERSE DMA General Control/Status Register contains enables, status and action bits. Enable bits are set by the user and are {\em sticky}, ie the stay in whatever state the user places them in. Status bits are set by the hardware in response to some condition it detects and cleared by the user after acknowledging them. Action bits are used to initiate some action. They are generally self-clearing. That is one sets them, and after the action is completed or acknowledged, the bit clears. \begin{Desc} \item[Warning: ]\par The narrative descriptions of the bit fields where lifted straight out of the UNIVERSE II User Manual. That manual serves as the ultimate source of the information. An descrepancies between this documentation and the documentation in the UNIVERSE II User Manual is always resolved in favor of UNIVERSE II User Manual. \end{Desc} \subsection{Enumeration Type Documentation} \hypertarget{UNIV_8h_a179}{ \index{UNIV.h@{UNIV.h}!_UNIV_M_dctl@{\_\-UNIV\_\-M\_\-dctl}} \index{_UNIV_M_dctl@{\_\-UNIV\_\-M\_\-dctl}!UNIV.h@{UNIV.h}} \subsubsection[\_\-UNIV\_\-M\_\-dctl]{\setlength{\rightskip}{0pt plus 5cm}enum \_\-UNIV\_\-M\_\-dctl}} \label{UNIV_8h_a179} Gives in place extraction masks for each of the bit fields in the DCTL control word. \begin{Desc} \item[Enumeration values:]\par \begin{description} \index{UNIV_M_DCTL_RSVD_0@{UNIV\_\-M\_\-DCTL\_\-RSVD\_\-0}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DCTL_RSVD_0@{UNIV\_\-M\_\-DCTL\_\-RSVD\_\-0}}\item[{\em \hypertarget{UNIV_8h_a179a52}{ {\em UNIV\_\-M\_\-DCTL\_\-RSVD\_\-0}} \label{UNIV_8h_a179a52} }]Mask for this unused field \index{UNIV_M_DCTL_LD64EN@{UNIV\_\-M\_\-DCTL\_\-LD64EN}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DCTL_LD64EN@{UNIV\_\-M\_\-DCTL\_\-LD64EN}}\item[{\em \hypertarget{UNIV_8h_a179a53}{ {\em UNIV\_\-M\_\-DCTL\_\-LD64EN}} \label{UNIV_8h_a179a53} }]Mask for Enable PCI 64-bit transaction field \index{UNIV_M_DCTL_VCT@{UNIV\_\-M\_\-DCTL\_\-VCT}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DCTL_VCT@{UNIV\_\-M\_\-DCTL\_\-VCT}}\item[{\em \hypertarget{UNIV_8h_a179a54}{ {\em UNIV\_\-M\_\-DCTL\_\-VCT}} \label{UNIV_8h_a179a54} }]Mask for VME Bus Cycle type field \index{UNIV_M_DCTL_RSVD_1@{UNIV\_\-M\_\-DCTL\_\-RSVD\_\-1}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DCTL_RSVD_1@{UNIV\_\-M\_\-DCTL\_\-RSVD\_\-1}}\item[{\em \hypertarget{UNIV_8h_a179a55}{ {\em UNIV\_\-M\_\-DCTL\_\-RSVD\_\-1}} \label{UNIV_8h_a179a55} }]Mask for this unused field \index{UNIV_M_DCTL_SUPER@{UNIV\_\-M\_\-DCTL\_\-SUPER}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DCTL_SUPER@{UNIV\_\-M\_\-DCTL\_\-SUPER}}\item[{\em \hypertarget{UNIV_8h_a179a56}{ {\em UNIV\_\-M\_\-DCTL\_\-SUPER}} \label{UNIV_8h_a179a56} }]Mask for Supervisor/User AM code field \index{UNIV_M_DCTL_PGM@{UNIV\_\-M\_\-DCTL\_\-PGM}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DCTL_PGM@{UNIV\_\-M\_\-DCTL\_\-PGM}}\item[{\em \hypertarget{UNIV_8h_a179a57}{ {\em UNIV\_\-M\_\-DCTL\_\-PGM}} \label{UNIV_8h_a179a57} }]Mask for Program/Data AM code field \index{UNIV_M_DCTL_VAS@{UNIV\_\-M\_\-DCTL\_\-VAS}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DCTL_VAS@{UNIV\_\-M\_\-DCTL\_\-VAS}}\item[{\em \hypertarget{UNIV_8h_a179a58}{ {\em UNIV\_\-M\_\-DCTL\_\-VAS}} \label{UNIV_8h_a179a58} }]Mask for VME Bus Address Space field \index{UNIV_M_DCTL_RSVD_2@{UNIV\_\-M\_\-DCTL\_\-RSVD\_\-2}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DCTL_RSVD_2@{UNIV\_\-M\_\-DCTL\_\-RSVD\_\-2}}\item[{\em \hypertarget{UNIV_8h_a179a59}{ {\em UNIV\_\-M\_\-DCTL\_\-RSVD\_\-2}} \label{UNIV_8h_a179a59} }]Mask for this unused field \index{UNIV_M_DCTL_VDW@{UNIV\_\-M\_\-DCTL\_\-VDW}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DCTL_VDW@{UNIV\_\-M\_\-DCTL\_\-VDW}}\item[{\em \hypertarget{UNIV_8h_a179a60}{ {\em UNIV\_\-M\_\-DCTL\_\-VDW}} \label{UNIV_8h_a179a60} }]Mask for VME Maximum Datawidth field \index{UNIV_M_DCTL_RSVD_3@{UNIV\_\-M\_\-DCTL\_\-RSVD\_\-3}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DCTL_RSVD_3@{UNIV\_\-M\_\-DCTL\_\-RSVD\_\-3}}\item[{\em \hypertarget{UNIV_8h_a179a61}{ {\em UNIV\_\-M\_\-DCTL\_\-RSVD\_\-3}} \label{UNIV_8h_a179a61} }]Mask for this unused field \index{UNIV_M_DCTL_L2V@{UNIV\_\-M\_\-DCTL\_\-L2V}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DCTL_L2V@{UNIV\_\-M\_\-DCTL\_\-L2V}}\item[{\em \hypertarget{UNIV_8h_a179a62}{ {\em UNIV\_\-M\_\-DCTL\_\-L2V}} \label{UNIV_8h_a179a62} }]Mask for Transaction Direction field \end{description} \end{Desc} \hypertarget{UNIV_8h_a182}{ \index{UNIV.h@{UNIV.h}!_UNIV_M_dgcs@{\_\-UNIV\_\-M\_\-dgcs}} \index{_UNIV_M_dgcs@{\_\-UNIV\_\-M\_\-dgcs}!UNIV.h@{UNIV.h}} \subsubsection[\_\-UNIV\_\-M\_\-dgcs]{\setlength{\rightskip}{0pt plus 5cm}enum \_\-UNIV\_\-M\_\-dgcs}} \label{UNIV_8h_a182} Maps out in place masks of the bit fields in the DMA General Control/Status Register. \begin{Desc} \item[Enumeration values:]\par \begin{description} \index{UNIV_M_DGCS_INT_P_ERR@{UNIV\_\-M\_\-DGCS\_\-INT\_\-P\_\-ERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_INT_P_ERR@{UNIV\_\-M\_\-DGCS\_\-INT\_\-P\_\-ERR}}\item[{\em \hypertarget{UNIV_8h_a182a127}{ {\em UNIV\_\-M\_\-DGCS\_\-INT\_\-P\_\-ERR}} \label{UNIV_8h_a182a127} }]P\_\-ERR Enb mask \index{UNIV_M_DGCS_INT_VERR@{UNIV\_\-M\_\-DGCS\_\-INT\_\-VERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_INT_VERR@{UNIV\_\-M\_\-DGCS\_\-INT\_\-VERR}}\item[{\em \hypertarget{UNIV_8h_a182a128}{ {\em UNIV\_\-M\_\-DGCS\_\-INT\_\-VERR}} \label{UNIV_8h_a182a128} }]VERR Enable mask \index{UNIV_M_DGCS_INT_LERR@{UNIV\_\-M\_\-DGCS\_\-INT\_\-LERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_INT_LERR@{UNIV\_\-M\_\-DGCS\_\-INT\_\-LERR}}\item[{\em \hypertarget{UNIV_8h_a182a129}{ {\em UNIV\_\-M\_\-DGCS\_\-INT\_\-LERR}} \label{UNIV_8h_a182a129} }]LERR Enable mask \index{UNIV_M_DGCS_INT_DONE@{UNIV\_\-M\_\-DGCS\_\-INT\_\-DONE}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_INT_DONE@{UNIV\_\-M\_\-DGCS\_\-INT\_\-DONE}}\item[{\em \hypertarget{UNIV_8h_a182a130}{ {\em UNIV\_\-M\_\-DGCS\_\-INT\_\-DONE}} \label{UNIV_8h_a182a130} }]DONE Enable mask \index{UNIV_M_DGCS_INT_RSVD4@{UNIV\_\-M\_\-DGCS\_\-INT\_\-RSVD4}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_INT_RSVD4@{UNIV\_\-M\_\-DGCS\_\-INT\_\-RSVD4}}\item[{\em \hypertarget{UNIV_8h_a182a131}{ {\em UNIV\_\-M\_\-DGCS\_\-INT\_\-RSVD4}} \label{UNIV_8h_a182a131} }]Unused \index{UNIV_M_DGCS_INT_HALT@{UNIV\_\-M\_\-DGCS\_\-INT\_\-HALT}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_INT_HALT@{UNIV\_\-M\_\-DGCS\_\-INT\_\-HALT}}\item[{\em \hypertarget{UNIV_8h_a182a132}{ {\em UNIV\_\-M\_\-DGCS\_\-INT\_\-HALT}} \label{UNIV_8h_a182a132} }]HALT Enable mask \index{UNIV_M_DGCS_INT_STOP@{UNIV\_\-M\_\-DGCS\_\-INT\_\-STOP}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_INT_STOP@{UNIV\_\-M\_\-DGCS\_\-INT\_\-STOP}}\item[{\em \hypertarget{UNIV_8h_a182a133}{ {\em UNIV\_\-M\_\-DGCS\_\-INT\_\-STOP}} \label{UNIV_8h_a182a133} }]STOP Enable mask \index{UNIV_M_DGCS_P_ERR@{UNIV\_\-M\_\-DGCS\_\-P\_\-ERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_P_ERR@{UNIV\_\-M\_\-DGCS\_\-P\_\-ERR}}\item[{\em \hypertarget{UNIV_8h_a182a135}{ {\em UNIV\_\-M\_\-DGCS\_\-P\_\-ERR}} \label{UNIV_8h_a182a135} }]Status, Protocol error \index{UNIV_M_DGCS_VERR@{UNIV\_\-M\_\-DGCS\_\-VERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_VERR@{UNIV\_\-M\_\-DGCS\_\-VERR}}\item[{\em \hypertarget{UNIV_8h_a182a136}{ {\em UNIV\_\-M\_\-DGCS\_\-VERR}} \label{UNIV_8h_a182a136} }]Status, VME bus error \index{UNIV_M_DGCS_LERR@{UNIV\_\-M\_\-DGCS\_\-LERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_LERR@{UNIV\_\-M\_\-DGCS\_\-LERR}}\item[{\em \hypertarget{UNIV_8h_a182a137}{ {\em UNIV\_\-M\_\-DGCS\_\-LERR}} \label{UNIV_8h_a182a137} }]Status, PCI bus error \index{UNIV_M_DGCS_DONE@{UNIV\_\-M\_\-DGCS\_\-DONE}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_DONE@{UNIV\_\-M\_\-DGCS\_\-DONE}}\item[{\em \hypertarget{UNIV_8h_a182a138}{ {\em UNIV\_\-M\_\-DGCS\_\-DONE}} \label{UNIV_8h_a182a138} }]Status, DMA done \index{UNIV_M_DGCS_HALT@{UNIV\_\-M\_\-DGCS\_\-HALT}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_HALT@{UNIV\_\-M\_\-DGCS\_\-HALT}}\item[{\em \hypertarget{UNIV_8h_a182a139}{ {\em UNIV\_\-M\_\-DGCS\_\-HALT}} \label{UNIV_8h_a182a139} }]Status, DMA halted \index{UNIV_M_DGCS_STOP@{UNIV\_\-M\_\-DGCS\_\-STOP}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_STOP@{UNIV\_\-M\_\-DGCS\_\-STOP}}\item[{\em \hypertarget{UNIV_8h_a182a140}{ {\em UNIV\_\-M\_\-DGCS\_\-STOP}} \label{UNIV_8h_a182a140} }]Status, DMA stopped \index{UNIV_M_DGCS_ACT@{UNIV\_\-M\_\-DGCS\_\-ACT}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_ACT@{UNIV\_\-M\_\-DGCS\_\-ACT}}\item[{\em \hypertarget{UNIV_8h_a182a141}{ {\em UNIV\_\-M\_\-DGCS\_\-ACT}} \label{UNIV_8h_a182a141} }]Status, DMA active \index{UNIV_M_DGCS_VOFF@{UNIV\_\-M\_\-DGCS\_\-VOFF}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_VOFF@{UNIV\_\-M\_\-DGCS\_\-VOFF}}\item[{\em \hypertarget{UNIV_8h_a182a142}{ {\em UNIV\_\-M\_\-DGCS\_\-VOFF}} \label{UNIV_8h_a182a142} }]VOFF counter mask \index{UNIV_M_DGCS_VON@{UNIV\_\-M\_\-DGCS\_\-VON}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_VON@{UNIV\_\-M\_\-DGCS\_\-VON}}\item[{\em \hypertarget{UNIV_8h_a182a143}{ {\em UNIV\_\-M\_\-DGCS\_\-VON}} \label{UNIV_8h_a182a143} }]VOFF counter mask \index{UNIV_M_DGCS_RSVD23@{UNIV\_\-M\_\-DGCS\_\-RSVD23}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_RSVD23@{UNIV\_\-M\_\-DGCS\_\-RSVD23}}\item[{\em \hypertarget{UNIV_8h_a182a144}{ {\em UNIV\_\-M\_\-DGCS\_\-RSVD23}} \label{UNIV_8h_a182a144} }]Unused \index{UNIV_M_DGCS_RSVD24@{UNIV\_\-M\_\-DGCS\_\-RSVD24}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_RSVD24@{UNIV\_\-M\_\-DGCS\_\-RSVD24}}\item[{\em \hypertarget{UNIV_8h_a182a145}{ {\em UNIV\_\-M\_\-DGCS\_\-RSVD24}} \label{UNIV_8h_a182a145} }]Unused \index{UNIV_M_DGCS_CHAIN@{UNIV\_\-M\_\-DGCS\_\-CHAIN}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_CHAIN@{UNIV\_\-M\_\-DGCS\_\-CHAIN}}\item[{\em \hypertarget{UNIV_8h_a182a146}{ {\em UNIV\_\-M\_\-DGCS\_\-CHAIN}} \label{UNIV_8h_a182a146} }]DMA Chaining mask \index{UNIV_M_DGCS_RSVD28@{UNIV\_\-M\_\-DGCS\_\-RSVD28}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_RSVD28@{UNIV\_\-M\_\-DGCS\_\-RSVD28}}\item[{\em \hypertarget{UNIV_8h_a182a147}{ {\em UNIV\_\-M\_\-DGCS\_\-RSVD28}} \label{UNIV_8h_a182a147} }]Unused \index{UNIV_M_DGCS_HALT_REQ@{UNIV\_\-M\_\-DGCS\_\-HALT\_\-REQ}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_HALT_REQ@{UNIV\_\-M\_\-DGCS\_\-HALT\_\-REQ}}\item[{\em \hypertarget{UNIV_8h_a182a148}{ {\em UNIV\_\-M\_\-DGCS\_\-HALT\_\-REQ}} \label{UNIV_8h_a182a148} }]Halt Request mask \index{UNIV_M_DGCS_STOP_REQ@{UNIV\_\-M\_\-DGCS\_\-STOP\_\-REQ}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_STOP_REQ@{UNIV\_\-M\_\-DGCS\_\-STOP\_\-REQ}}\item[{\em \hypertarget{UNIV_8h_a182a149}{ {\em UNIV\_\-M\_\-DGCS\_\-STOP\_\-REQ}} \label{UNIV_8h_a182a149} }]Stop Request mask \index{UNIV_M_DGCS_GO@{UNIV\_\-M\_\-DGCS\_\-GO}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_GO@{UNIV\_\-M\_\-DGCS\_\-GO}}\item[{\em \hypertarget{UNIV_8h_a182a150}{ {\em UNIV\_\-M\_\-DGCS\_\-GO}} \label{UNIV_8h_a182a150} }]Go Request mask \index{UNIV_M_DGCS_INT_ENB_ERR@{UNIV\_\-M\_\-DGCS\_\-INT\_\-ENB\_\-ERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_INT_ENB_ERR@{UNIV\_\-M\_\-DGCS\_\-INT\_\-ENB\_\-ERR}}\item[{\em \hypertarget{UNIV_8h_a182a151}{ {\em UNIV\_\-M\_\-DGCS\_\-INT\_\-ENB\_\-ERR}} \label{UNIV_8h_a182a151} }]Mask of all error interrupt enable bits \index{UNIV_M_DGCS_INT_ENB_SUC@{UNIV\_\-M\_\-DGCS\_\-INT\_\-ENB\_\-SUC}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_INT_ENB_SUC@{UNIV\_\-M\_\-DGCS\_\-INT\_\-ENB\_\-SUC}}\item[{\em \hypertarget{UNIV_8h_a182a152}{ {\em UNIV\_\-M\_\-DGCS\_\-INT\_\-ENB\_\-SUC}} \label{UNIV_8h_a182a152} }]Mask of all successful interrupt enable bits \index{UNIV_M_DGCS_INT_ENB_ALL@{UNIV\_\-M\_\-DGCS\_\-INT\_\-ENB\_\-ALL}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_INT_ENB_ALL@{UNIV\_\-M\_\-DGCS\_\-INT\_\-ENB\_\-ALL}}\item[{\em \hypertarget{UNIV_8h_a182a153}{ {\em UNIV\_\-M\_\-DGCS\_\-INT\_\-ENB\_\-ALL}} \label{UNIV_8h_a182a153} }]Mask of all interrupt enable bits \index{UNIV_M_DGCS_INT_STS_ERR@{UNIV\_\-M\_\-DGCS\_\-INT\_\-STS\_\-ERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_INT_STS_ERR@{UNIV\_\-M\_\-DGCS\_\-INT\_\-STS\_\-ERR}}\item[{\em \hypertarget{UNIV_8h_a182a154}{ {\em UNIV\_\-M\_\-DGCS\_\-INT\_\-STS\_\-ERR}} \label{UNIV_8h_a182a154} }]Mask of all error interrupt status bits \index{UNIV_M_DGCS_INT_STS_SUC@{UNIV\_\-M\_\-DGCS\_\-INT\_\-STS\_\-SUC}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_INT_STS_SUC@{UNIV\_\-M\_\-DGCS\_\-INT\_\-STS\_\-SUC}}\item[{\em \hypertarget{UNIV_8h_a182a155}{ {\em UNIV\_\-M\_\-DGCS\_\-INT\_\-STS\_\-SUC}} \label{UNIV_8h_a182a155} }]Mask of all successful interrupt status bits \index{UNIV_M_DGCS_INT_STS_ALL@{UNIV\_\-M\_\-DGCS\_\-INT\_\-STS\_\-ALL}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_INT_STS_ALL@{UNIV\_\-M\_\-DGCS\_\-INT\_\-STS\_\-ALL}}\item[{\em \hypertarget{UNIV_8h_a182a156}{ {\em UNIV\_\-M\_\-DGCS\_\-INT\_\-STS\_\-ALL}} \label{UNIV_8h_a182a156} }]Mask of all interrupt status bits \index{UNIV_M_DGCS_STS_ALL@{UNIV\_\-M\_\-DGCS\_\-STS\_\-ALL}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_M_DGCS_STS_ALL@{UNIV\_\-M\_\-DGCS\_\-STS\_\-ALL}}\item[{\em \hypertarget{UNIV_8h_a182a157}{ {\em UNIV\_\-M\_\-DGCS\_\-STS\_\-ALL}} \label{UNIV_8h_a182a157} }]Mask of all status bits \end{description} \end{Desc} \hypertarget{UNIV_8h_a178}{ \index{UNIV.h@{UNIV.h}!_UNIV_S_dctl@{\_\-UNIV\_\-S\_\-dctl}} \index{_UNIV_S_dctl@{\_\-UNIV\_\-S\_\-dctl}!UNIV.h@{UNIV.h}} \subsubsection[\_\-UNIV\_\-S\_\-dctl]{\setlength{\rightskip}{0pt plus 5cm}enum \_\-UNIV\_\-S\_\-dctl}} \label{UNIV_8h_a178} Gives the size of each of the bit fields in the DCTL control word. \begin{Desc} \item[Enumeration values:]\par \begin{description} \index{UNIV_S_DCTL_RSVD_0@{UNIV\_\-S\_\-DCTL\_\-RSVD\_\-0}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DCTL_RSVD_0@{UNIV\_\-S\_\-DCTL\_\-RSVD\_\-0}}\item[{\em \hypertarget{UNIV_8h_a178a41}{ {\em UNIV\_\-S\_\-DCTL\_\-RSVD\_\-0}} \label{UNIV_8h_a178a41} }]Size of this unused field \index{UNIV_S_DCTL_LD64EN@{UNIV\_\-S\_\-DCTL\_\-LD64EN}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DCTL_LD64EN@{UNIV\_\-S\_\-DCTL\_\-LD64EN}}\item[{\em \hypertarget{UNIV_8h_a178a42}{ {\em UNIV\_\-S\_\-DCTL\_\-LD64EN}} \label{UNIV_8h_a178a42} }]Size of Enable 64-Bit PCI Transaction \index{UNIV_S_DCTL_VCT@{UNIV\_\-S\_\-DCTL\_\-VCT}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DCTL_VCT@{UNIV\_\-S\_\-DCTL\_\-VCT}}\item[{\em \hypertarget{UNIV_8h_a178a43}{ {\em UNIV\_\-S\_\-DCTL\_\-VCT}} \label{UNIV_8h_a178a43} }]Size of VME Bus Cycle Type field \index{UNIV_S_DCTL_RSVD_1@{UNIV\_\-S\_\-DCTL\_\-RSVD\_\-1}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DCTL_RSVD_1@{UNIV\_\-S\_\-DCTL\_\-RSVD\_\-1}}\item[{\em \hypertarget{UNIV_8h_a178a44}{ {\em UNIV\_\-S\_\-DCTL\_\-RSVD\_\-1}} \label{UNIV_8h_a178a44} }]Size of this unused field \index{UNIV_S_DCTL_SUPER@{UNIV\_\-S\_\-DCTL\_\-SUPER}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DCTL_SUPER@{UNIV\_\-S\_\-DCTL\_\-SUPER}}\item[{\em \hypertarget{UNIV_8h_a178a45}{ {\em UNIV\_\-S\_\-DCTL\_\-SUPER}} \label{UNIV_8h_a178a45} }]Size of Supervisor/User AM code field \index{UNIV_S_DCTL_PGM@{UNIV\_\-S\_\-DCTL\_\-PGM}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DCTL_PGM@{UNIV\_\-S\_\-DCTL\_\-PGM}}\item[{\em \hypertarget{UNIV_8h_a178a46}{ {\em UNIV\_\-S\_\-DCTL\_\-PGM}} \label{UNIV_8h_a178a46} }]Size of Program/Data AM code field \index{UNIV_S_DCTL_VAS@{UNIV\_\-S\_\-DCTL\_\-VAS}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DCTL_VAS@{UNIV\_\-S\_\-DCTL\_\-VAS}}\item[{\em \hypertarget{UNIV_8h_a178a47}{ {\em UNIV\_\-S\_\-DCTL\_\-VAS}} \label{UNIV_8h_a178a47} }]Size of VME Bus Address field \index{UNIV_S_DCTL_RSVD_2@{UNIV\_\-S\_\-DCTL\_\-RSVD\_\-2}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DCTL_RSVD_2@{UNIV\_\-S\_\-DCTL\_\-RSVD\_\-2}}\item[{\em \hypertarget{UNIV_8h_a178a48}{ {\em UNIV\_\-S\_\-DCTL\_\-RSVD\_\-2}} \label{UNIV_8h_a178a48} }]Size of this unused field \index{UNIV_S_DCTL_VDW@{UNIV\_\-S\_\-DCTL\_\-VDW}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DCTL_VDW@{UNIV\_\-S\_\-DCTL\_\-VDW}}\item[{\em \hypertarget{UNIV_8h_a178a49}{ {\em UNIV\_\-S\_\-DCTL\_\-VDW}} \label{UNIV_8h_a178a49} }]Size of VME Bus Maximum Datawidth field \index{UNIV_S_DCTL_RSVD_3@{UNIV\_\-S\_\-DCTL\_\-RSVD\_\-3}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DCTL_RSVD_3@{UNIV\_\-S\_\-DCTL\_\-RSVD\_\-3}}\item[{\em \hypertarget{UNIV_8h_a178a50}{ {\em UNIV\_\-S\_\-DCTL\_\-RSVD\_\-3}} \label{UNIV_8h_a178a50} }]Size of this unused field \index{UNIV_S_DCTL_L2V@{UNIV\_\-S\_\-DCTL\_\-L2V}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DCTL_L2V@{UNIV\_\-S\_\-DCTL\_\-L2V}}\item[{\em \hypertarget{UNIV_8h_a178a51}{ {\em UNIV\_\-S\_\-DCTL\_\-L2V}} \label{UNIV_8h_a178a51} }]Size of Transfer Direction field \end{description} \end{Desc} \hypertarget{UNIV_8h_a181}{ \index{UNIV.h@{UNIV.h}!_UNIV_S_dgcs@{\_\-UNIV\_\-S\_\-dgcs}} \index{_UNIV_S_dgcs@{\_\-UNIV\_\-S\_\-dgcs}!UNIV.h@{UNIV.h}} \subsubsection[\_\-UNIV\_\-S\_\-dgcs]{\setlength{\rightskip}{0pt plus 5cm}enum \_\-UNIV\_\-S\_\-dgcs}} \label{UNIV_8h_a181} Maps out the sizes of bit fields in the DMA General Control/Status Register. \begin{Desc} \item[Enumeration values:]\par \begin{description} \index{UNIV_S_DGCS_INT_P_ERR@{UNIV\_\-S\_\-DGCS\_\-INT\_\-P\_\-ERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_INT_P_ERR@{UNIV\_\-S\_\-DGCS\_\-INT\_\-P\_\-ERR}}\item[{\em \hypertarget{UNIV_8h_a181a95}{ {\em UNIV\_\-S\_\-DGCS\_\-INT\_\-P\_\-ERR}} \label{UNIV_8h_a181a95} }]Size of the P\_\-ERR enable bit field \index{UNIV_S_DGCS_INT_VERR@{UNIV\_\-S\_\-DGCS\_\-INT\_\-VERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_INT_VERR@{UNIV\_\-S\_\-DGCS\_\-INT\_\-VERR}}\item[{\em \hypertarget{UNIV_8h_a181a96}{ {\em UNIV\_\-S\_\-DGCS\_\-INT\_\-VERR}} \label{UNIV_8h_a181a96} }]Size of the VERR enable bit field \index{UNIV_S_DGCS_INT_LERR@{UNIV\_\-S\_\-DGCS\_\-INT\_\-LERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_INT_LERR@{UNIV\_\-S\_\-DGCS\_\-INT\_\-LERR}}\item[{\em \hypertarget{UNIV_8h_a181a97}{ {\em UNIV\_\-S\_\-DGCS\_\-INT\_\-LERR}} \label{UNIV_8h_a181a97} }]Size of the LERR enable bit field \index{UNIV_S_DGCS_INT_RSVD4@{UNIV\_\-S\_\-DGCS\_\-INT\_\-RSVD4}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_INT_RSVD4@{UNIV\_\-S\_\-DGCS\_\-INT\_\-RSVD4}}\item[{\em \hypertarget{UNIV_8h_a181a98}{ {\em UNIV\_\-S\_\-DGCS\_\-INT\_\-RSVD4}} \label{UNIV_8h_a181a98} }]Unused \index{UNIV_S_DGCS_INT_DONE@{UNIV\_\-S\_\-DGCS\_\-INT\_\-DONE}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_INT_DONE@{UNIV\_\-S\_\-DGCS\_\-INT\_\-DONE}}\item[{\em \hypertarget{UNIV_8h_a181a99}{ {\em UNIV\_\-S\_\-DGCS\_\-INT\_\-DONE}} \label{UNIV_8h_a181a99} }]Size of the DONE enable bit field \index{UNIV_S_DGCS_INT_HALT@{UNIV\_\-S\_\-DGCS\_\-INT\_\-HALT}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_INT_HALT@{UNIV\_\-S\_\-DGCS\_\-INT\_\-HALT}}\item[{\em \hypertarget{UNIV_8h_a181a100}{ {\em UNIV\_\-S\_\-DGCS\_\-INT\_\-HALT}} \label{UNIV_8h_a181a100} }]Size of the HALT enable bit field \index{UNIV_S_DGCS_INT_STOP@{UNIV\_\-S\_\-DGCS\_\-INT\_\-STOP}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_INT_STOP@{UNIV\_\-S\_\-DGCS\_\-INT\_\-STOP}}\item[{\em \hypertarget{UNIV_8h_a181a101}{ {\em UNIV\_\-S\_\-DGCS\_\-INT\_\-STOP}} \label{UNIV_8h_a181a101} }]Size of the STOP enable bit field \index{UNIV_S_DGCS_INT_RSVD7@{UNIV\_\-S\_\-DGCS\_\-INT\_\-RSVD7}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_INT_RSVD7@{UNIV\_\-S\_\-DGCS\_\-INT\_\-RSVD7}}\item[{\em \hypertarget{UNIV_8h_a181a102}{ {\em UNIV\_\-S\_\-DGCS\_\-INT\_\-RSVD7}} \label{UNIV_8h_a181a102} }]Unused \index{UNIV_S_DGCS_P_ERR@{UNIV\_\-S\_\-DGCS\_\-P\_\-ERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_P_ERR@{UNIV\_\-S\_\-DGCS\_\-P\_\-ERR}}\item[{\em \hypertarget{UNIV_8h_a181a103}{ {\em UNIV\_\-S\_\-DGCS\_\-P\_\-ERR}} \label{UNIV_8h_a181a103} }]Size of the P\_\-ERR status bit field \index{UNIV_S_DGCS_VERR@{UNIV\_\-S\_\-DGCS\_\-VERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_VERR@{UNIV\_\-S\_\-DGCS\_\-VERR}}\item[{\em \hypertarget{UNIV_8h_a181a104}{ {\em UNIV\_\-S\_\-DGCS\_\-VERR}} \label{UNIV_8h_a181a104} }]Size of the VERR status bit field \index{UNIV_S_DGCS_LERR@{UNIV\_\-S\_\-DGCS\_\-LERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_LERR@{UNIV\_\-S\_\-DGCS\_\-LERR}}\item[{\em \hypertarget{UNIV_8h_a181a105}{ {\em UNIV\_\-S\_\-DGCS\_\-LERR}} \label{UNIV_8h_a181a105} }]Size of the LERR status bit field \index{UNIV_S_DGCS_DONE@{UNIV\_\-S\_\-DGCS\_\-DONE}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_DONE@{UNIV\_\-S\_\-DGCS\_\-DONE}}\item[{\em \hypertarget{UNIV_8h_a181a106}{ {\em UNIV\_\-S\_\-DGCS\_\-DONE}} \label{UNIV_8h_a181a106} }]Size of the DONE status bit field \index{UNIV_S_DGCS_RSVD12@{UNIV\_\-S\_\-DGCS\_\-RSVD12}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_RSVD12@{UNIV\_\-S\_\-DGCS\_\-RSVD12}}\item[{\em \hypertarget{UNIV_8h_a181a107}{ {\em UNIV\_\-S\_\-DGCS\_\-RSVD12}} \label{UNIV_8h_a181a107} }]Unused \index{UNIV_S_DGCS_HALT@{UNIV\_\-S\_\-DGCS\_\-HALT}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_HALT@{UNIV\_\-S\_\-DGCS\_\-HALT}}\item[{\em \hypertarget{UNIV_8h_a181a108}{ {\em UNIV\_\-S\_\-DGCS\_\-HALT}} \label{UNIV_8h_a181a108} }]Size of the HALT status bit field \index{UNIV_S_DGCS_STOP@{UNIV\_\-S\_\-DGCS\_\-STOP}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_STOP@{UNIV\_\-S\_\-DGCS\_\-STOP}}\item[{\em \hypertarget{UNIV_8h_a181a109}{ {\em UNIV\_\-S\_\-DGCS\_\-STOP}} \label{UNIV_8h_a181a109} }]Size of the STOP status bit field \index{UNIV_S_DGCS_ACT@{UNIV\_\-S\_\-DGCS\_\-ACT}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_ACT@{UNIV\_\-S\_\-DGCS\_\-ACT}}\item[{\em \hypertarget{UNIV_8h_a181a110}{ {\em UNIV\_\-S\_\-DGCS\_\-ACT}} \label{UNIV_8h_a181a110} }]Size of the ACT status bit field \index{UNIV_S_DGCS_VOFF@{UNIV\_\-S\_\-DGCS\_\-VOFF}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_VOFF@{UNIV\_\-S\_\-DGCS\_\-VOFF}}\item[{\em \hypertarget{UNIV_8h_a181a111}{ {\em UNIV\_\-S\_\-DGCS\_\-VOFF}} \label{UNIV_8h_a181a111} }]Size of the VOFF bit field \index{UNIV_S_DGCS_VON@{UNIV\_\-S\_\-DGCS\_\-VON}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_VON@{UNIV\_\-S\_\-DGCS\_\-VON}}\item[{\em \hypertarget{UNIV_8h_a181a112}{ {\em UNIV\_\-S\_\-DGCS\_\-VON}} \label{UNIV_8h_a181a112} }]Size of the VON bit field \index{UNIV_S_DGCS_RSVD23@{UNIV\_\-S\_\-DGCS\_\-RSVD23}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_RSVD23@{UNIV\_\-S\_\-DGCS\_\-RSVD23}}\item[{\em \hypertarget{UNIV_8h_a181a113}{ {\em UNIV\_\-S\_\-DGCS\_\-RSVD23}} \label{UNIV_8h_a181a113} }]Unused \index{UNIV_S_DGCS_RSVD24@{UNIV\_\-S\_\-DGCS\_\-RSVD24}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_RSVD24@{UNIV\_\-S\_\-DGCS\_\-RSVD24}}\item[{\em \hypertarget{UNIV_8h_a181a114}{ {\em UNIV\_\-S\_\-DGCS\_\-RSVD24}} \label{UNIV_8h_a181a114} }]Unused \index{UNIV_S_DGCS_CHAIN@{UNIV\_\-S\_\-DGCS\_\-CHAIN}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_CHAIN@{UNIV\_\-S\_\-DGCS\_\-CHAIN}}\item[{\em \hypertarget{UNIV_8h_a181a115}{ {\em UNIV\_\-S\_\-DGCS\_\-CHAIN}} \label{UNIV_8h_a181a115} }]Size of the CHAIN enable bit field \index{UNIV_S_DGCS_RSVD28@{UNIV\_\-S\_\-DGCS\_\-RSVD28}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_RSVD28@{UNIV\_\-S\_\-DGCS\_\-RSVD28}}\item[{\em \hypertarget{UNIV_8h_a181a116}{ {\em UNIV\_\-S\_\-DGCS\_\-RSVD28}} \label{UNIV_8h_a181a116} }]Unused \index{UNIV_S_DGCS_HALT_REQ@{UNIV\_\-S\_\-DGCS\_\-HALT\_\-REQ}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_HALT_REQ@{UNIV\_\-S\_\-DGCS\_\-HALT\_\-REQ}}\item[{\em \hypertarget{UNIV_8h_a181a117}{ {\em UNIV\_\-S\_\-DGCS\_\-HALT\_\-REQ}} \label{UNIV_8h_a181a117} }]Size of the HALT Requeset bit field \index{UNIV_S_DGCS_STOP_REQ@{UNIV\_\-S\_\-DGCS\_\-STOP\_\-REQ}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_STOP_REQ@{UNIV\_\-S\_\-DGCS\_\-STOP\_\-REQ}}\item[{\em \hypertarget{UNIV_8h_a181a118}{ {\em UNIV\_\-S\_\-DGCS\_\-STOP\_\-REQ}} \label{UNIV_8h_a181a118} }]Size of the STOP Requeset bit field \index{UNIV_S_DGCS_GO@{UNIV\_\-S\_\-DGCS\_\-GO}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_GO@{UNIV\_\-S\_\-DGCS\_\-GO}}\item[{\em \hypertarget{UNIV_8h_a181a119}{ {\em UNIV\_\-S\_\-DGCS\_\-GO}} \label{UNIV_8h_a181a119} }]Size of the DMA Go bit field \index{UNIV_S_DGCS_INT_ENB_ERR@{UNIV\_\-S\_\-DGCS\_\-INT\_\-ENB\_\-ERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_INT_ENB_ERR@{UNIV\_\-S\_\-DGCS\_\-INT\_\-ENB\_\-ERR}}\item[{\em \hypertarget{UNIV_8h_a181a120}{ {\em UNIV\_\-S\_\-DGCS\_\-INT\_\-ENB\_\-ERR}} \label{UNIV_8h_a181a120} }]Size of ERR interrupt enable bits \index{UNIV_S_DGCS_INT_ENB_SUC@{UNIV\_\-S\_\-DGCS\_\-INT\_\-ENB\_\-SUC}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_INT_ENB_SUC@{UNIV\_\-S\_\-DGCS\_\-INT\_\-ENB\_\-SUC}}\item[{\em \hypertarget{UNIV_8h_a181a121}{ {\em UNIV\_\-S\_\-DGCS\_\-INT\_\-ENB\_\-SUC}} \label{UNIV_8h_a181a121} }]Size of SUC interrupt enable bits Note that this field has 1 unused bit in it \index{UNIV_S_DGCS_INT_ENB_ALL@{UNIV\_\-S\_\-DGCS\_\-INT\_\-ENB\_\-ALL}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_INT_ENB_ALL@{UNIV\_\-S\_\-DGCS\_\-INT\_\-ENB\_\-ALL}}\item[{\em \hypertarget{UNIV_8h_a181a122}{ {\em UNIV\_\-S\_\-DGCS\_\-INT\_\-ENB\_\-ALL}} \label{UNIV_8h_a181a122} }]Beginning of all interrupt enable bits \index{UNIV_S_DGCS_INT_STS_ERR@{UNIV\_\-S\_\-DGCS\_\-INT\_\-STS\_\-ERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_INT_STS_ERR@{UNIV\_\-S\_\-DGCS\_\-INT\_\-STS\_\-ERR}}\item[{\em \hypertarget{UNIV_8h_a181a123}{ {\em UNIV\_\-S\_\-DGCS\_\-INT\_\-STS\_\-ERR}} \label{UNIV_8h_a181a123} }]Size of ERR interrupt status bits \index{UNIV_S_DGCS_INT_STS_SUC@{UNIV\_\-S\_\-DGCS\_\-INT\_\-STS\_\-SUC}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_INT_STS_SUC@{UNIV\_\-S\_\-DGCS\_\-INT\_\-STS\_\-SUC}}\item[{\em \hypertarget{UNIV_8h_a181a124}{ {\em UNIV\_\-S\_\-DGCS\_\-INT\_\-STS\_\-SUC}} \label{UNIV_8h_a181a124} }]Size of SUC interrupt status bits \index{UNIV_S_DGCS_INT_STS_ALL@{UNIV\_\-S\_\-DGCS\_\-INT\_\-STS\_\-ALL}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_INT_STS_ALL@{UNIV\_\-S\_\-DGCS\_\-INT\_\-STS\_\-ALL}}\item[{\em \hypertarget{UNIV_8h_a181a125}{ {\em UNIV\_\-S\_\-DGCS\_\-INT\_\-STS\_\-ALL}} \label{UNIV_8h_a181a125} }]Size of ALL interrupt status bits \index{UNIV_S_DGCS_STS_ALL@{UNIV\_\-S\_\-DGCS\_\-STS\_\-ALL}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_S_DGCS_STS_ALL@{UNIV\_\-S\_\-DGCS\_\-STS\_\-ALL}}\item[{\em \hypertarget{UNIV_8h_a181a126}{ {\em UNIV\_\-S\_\-DGCS\_\-STS\_\-ALL}} \label{UNIV_8h_a181a126} }]Size of ALL status bits \end{description} \end{Desc} \hypertarget{UNIV_8h_a177}{ \index{UNIV.h@{UNIV.h}!_UNIV_V_dctl@{\_\-UNIV\_\-V\_\-dctl}} \index{_UNIV_V_dctl@{\_\-UNIV\_\-V\_\-dctl}!UNIV.h@{UNIV.h}} \subsubsection[\_\-UNIV\_\-V\_\-dctl]{\setlength{\rightskip}{0pt plus 5cm}enum \_\-UNIV\_\-V\_\-dctl}} \label{UNIV_8h_a177} Gives the number of bits to shift needed to right justify the bits field in the DCTL control word. \begin{Desc} \item[Enumeration values:]\par \begin{description} \index{UNIV_V_DCTL_RSVD_0@{UNIV\_\-V\_\-DCTL\_\-RSVD\_\-0}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DCTL_RSVD_0@{UNIV\_\-V\_\-DCTL\_\-RSVD\_\-0}}\item[{\em \hypertarget{UNIV_8h_a177a30}{ {\em UNIV\_\-V\_\-DCTL\_\-RSVD\_\-0}} \label{UNIV_8h_a177a30} }]Unused \index{UNIV_V_DCTL_LD64EN@{UNIV\_\-V\_\-DCTL\_\-LD64EN}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DCTL_LD64EN@{UNIV\_\-V\_\-DCTL\_\-LD64EN}}\item[{\em \hypertarget{UNIV_8h_a177a31}{ {\em UNIV\_\-V\_\-DCTL\_\-LD64EN}} \label{UNIV_8h_a177a31} }]Enable 64-bit PCI Bus Transactions 0 = Disable 1 = Enable \index{UNIV_V_DCTL_VCT@{UNIV\_\-V\_\-DCTL\_\-VCT}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DCTL_VCT@{UNIV\_\-V\_\-DCTL\_\-VCT}}\item[{\em \hypertarget{UNIV_8h_a177a32}{ {\em UNIV\_\-V\_\-DCTL\_\-VCT}} \label{UNIV_8h_a177a32} }]VME Bus Cycle Type 0 = No BLT's on VMEbus, 1 = BLT's on VME \index{UNIV_V_DCTL_RSVD_1@{UNIV\_\-V\_\-DCTL\_\-RSVD\_\-1}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DCTL_RSVD_1@{UNIV\_\-V\_\-DCTL\_\-RSVD\_\-1}}\item[{\em \hypertarget{UNIV_8h_a177a33}{ {\em UNIV\_\-V\_\-DCTL\_\-RSVD\_\-1}} \label{UNIV_8h_a177a33} }]Unused \index{UNIV_V_DCTL_SUPER@{UNIV\_\-V\_\-DCTL\_\-SUPER}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DCTL_SUPER@{UNIV\_\-V\_\-DCTL\_\-SUPER}}\item[{\em \hypertarget{UNIV_8h_a177a34}{ {\em UNIV\_\-V\_\-DCTL\_\-SUPER}} \label{UNIV_8h_a177a34} }]Supervisor/User AM code 00 = Non-Privledged, 01 = Supervisor, Others = reserved \index{UNIV_V_DCTL_PGM@{UNIV\_\-V\_\-DCTL\_\-PGM}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DCTL_PGM@{UNIV\_\-V\_\-DCTL\_\-PGM}}\item[{\em \hypertarget{UNIV_8h_a177a35}{ {\em UNIV\_\-V\_\-DCTL\_\-PGM}} \label{UNIV_8h_a177a35} }]Program/Data AM code 00 = Data, 01 = Program, Others = Reserved \index{UNIV_V_DCTL_VAS@{UNIV\_\-V\_\-DCTL\_\-VAS}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DCTL_VAS@{UNIV\_\-V\_\-DCTL\_\-VAS}}\item[{\em \hypertarget{UNIV_8h_a177a36}{ {\em UNIV\_\-V\_\-DCTL\_\-VAS}} \label{UNIV_8h_a177a36} }]VME Bus Address space 000 = A16, 001 = A24, 010 = A32 011 = Reserved, 101 = Reserved 110 = User 1, 111 = User 2 \index{UNIV_V_DCTL_RSVD_2@{UNIV\_\-V\_\-DCTL\_\-RSVD\_\-2}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DCTL_RSVD_2@{UNIV\_\-V\_\-DCTL\_\-RSVD\_\-2}}\item[{\em \hypertarget{UNIV_8h_a177a37}{ {\em UNIV\_\-V\_\-DCTL\_\-RSVD\_\-2}} \label{UNIV_8h_a177a37} }]Unused \index{UNIV_V_DCTL_VDW@{UNIV\_\-V\_\-DCTL\_\-VDW}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DCTL_VDW@{UNIV\_\-V\_\-DCTL\_\-VDW}}\item[{\em \hypertarget{UNIV_8h_a177a38}{ {\em UNIV\_\-V\_\-DCTL\_\-VDW}} \label{UNIV_8h_a177a38} }]VME Maximum Bus Width 00 = 8-bit data width, 01 = 16-bit data width, 10 = 32-bit data width, 11 = 64-bit data width \index{UNIV_V_DCTL_RSVD_3@{UNIV\_\-V\_\-DCTL\_\-RSVD\_\-3}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DCTL_RSVD_3@{UNIV\_\-V\_\-DCTL\_\-RSVD\_\-3}}\item[{\em \hypertarget{UNIV_8h_a177a39}{ {\em UNIV\_\-V\_\-DCTL\_\-RSVD\_\-3}} \label{UNIV_8h_a177a39} }]Unused \index{UNIV_V_DCTL_L2V@{UNIV\_\-V\_\-DCTL\_\-L2V}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DCTL_L2V@{UNIV\_\-V\_\-DCTL\_\-L2V}}\item[{\em \hypertarget{UNIV_8h_a177a40}{ {\em UNIV\_\-V\_\-DCTL\_\-L2V}} \label{UNIV_8h_a177a40} }]Transfer Direction 0 = Transfer from VME Bus to PCI Bus 1 = Transfer from PCI Bus to VME Bus \end{description} \end{Desc} \hypertarget{UNIV_8h_a180}{ \index{UNIV.h@{UNIV.h}!_UNIV_V_dgcs@{\_\-UNIV\_\-V\_\-dgcs}} \index{_UNIV_V_dgcs@{\_\-UNIV\_\-V\_\-dgcs}!UNIV.h@{UNIV.h}} \subsubsection[\_\-UNIV\_\-V\_\-dgcs]{\setlength{\rightskip}{0pt plus 5cm}enum \_\-UNIV\_\-V\_\-dgcs}} \label{UNIV_8h_a180} Maps out the DMA General Control/Status Register. \begin{Desc} \item[Enumeration values:]\par \begin{description} \index{UNIV_V_DGCS_INT_P_ERR@{UNIV\_\-V\_\-DGCS\_\-INT\_\-P\_\-ERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_INT_P_ERR@{UNIV\_\-V\_\-DGCS\_\-INT\_\-P\_\-ERR}}\item[{\em \hypertarget{UNIV_8h_a180a63}{ {\em UNIV\_\-V\_\-DGCS\_\-INT\_\-P\_\-ERR}} \label{UNIV_8h_a180a63} }]Enable Interrupt On Master Error \index{UNIV_V_DGCS_INT_VERR@{UNIV\_\-V\_\-DGCS\_\-INT\_\-VERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_INT_VERR@{UNIV\_\-V\_\-DGCS\_\-INT\_\-VERR}}\item[{\em \hypertarget{UNIV_8h_a180a64}{ {\em UNIV\_\-V\_\-DGCS\_\-INT\_\-VERR}} \label{UNIV_8h_a180a64} }]Enable Interrupt on VERR (VME error) \index{UNIV_V_DGCS_INT_LERR@{UNIV\_\-V\_\-DGCS\_\-INT\_\-LERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_INT_LERR@{UNIV\_\-V\_\-DGCS\_\-INT\_\-LERR}}\item[{\em \hypertarget{UNIV_8h_a180a65}{ {\em UNIV\_\-V\_\-DGCS\_\-INT\_\-LERR}} \label{UNIV_8h_a180a65} }]Enable Interrupt on LERR \index{UNIV_V_DGCS_INT_DONE@{UNIV\_\-V\_\-DGCS\_\-INT\_\-DONE}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_INT_DONE@{UNIV\_\-V\_\-DGCS\_\-INT\_\-DONE}}\item[{\em \hypertarget{UNIV_8h_a180a66}{ {\em UNIV\_\-V\_\-DGCS\_\-INT\_\-DONE}} \label{UNIV_8h_a180a66} }]Enable Interrupt when Done \index{UNIV_V_DGCS_INT_RSVD4@{UNIV\_\-V\_\-DGCS\_\-INT\_\-RSVD4}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_INT_RSVD4@{UNIV\_\-V\_\-DGCS\_\-INT\_\-RSVD4}}\item[{\em \hypertarget{UNIV_8h_a180a67}{ {\em UNIV\_\-V\_\-DGCS\_\-INT\_\-RSVD4}} \label{UNIV_8h_a180a67} }]Unused \index{UNIV_V_DGCS_INT_HALT@{UNIV\_\-V\_\-DGCS\_\-INT\_\-HALT}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_INT_HALT@{UNIV\_\-V\_\-DGCS\_\-INT\_\-HALT}}\item[{\em \hypertarget{UNIV_8h_a180a68}{ {\em UNIV\_\-V\_\-DGCS\_\-INT\_\-HALT}} \label{UNIV_8h_a180a68} }]Enable Interrupt when Halted \index{UNIV_V_DGCS_INT_STOP@{UNIV\_\-V\_\-DGCS\_\-INT\_\-STOP}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_INT_STOP@{UNIV\_\-V\_\-DGCS\_\-INT\_\-STOP}}\item[{\em \hypertarget{UNIV_8h_a180a69}{ {\em UNIV\_\-V\_\-DGCS\_\-INT\_\-STOP}} \label{UNIV_8h_a180a69} }]Enable Interrupt when Stopped \index{UNIV_V_DGCS_INT_RSVD7@{UNIV\_\-V\_\-DGCS\_\-INT\_\-RSVD7}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_INT_RSVD7@{UNIV\_\-V\_\-DGCS\_\-INT\_\-RSVD7}}\item[{\em \hypertarget{UNIV_8h_a180a70}{ {\em UNIV\_\-V\_\-DGCS\_\-INT\_\-RSVD7}} \label{UNIV_8h_a180a70} }]Unused \index{UNIV_V_DGCS_P_ERR@{UNIV\_\-V\_\-DGCS\_\-P\_\-ERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_P_ERR@{UNIV\_\-V\_\-DGCS\_\-P\_\-ERR}}\item[{\em \hypertarget{UNIV_8h_a180a71}{ {\em UNIV\_\-V\_\-DGCS\_\-P\_\-ERR}} \label{UNIV_8h_a180a71} }]Protocol error Asserted if PCI master interface disabled or lower 3 bits of the PCI and VME address fields differ. Also (determined experimentally) if the DMA packet is not 8 byte aligned \index{UNIV_V_DGCS_VERR@{UNIV\_\-V\_\-DGCS\_\-VERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_VERR@{UNIV\_\-V\_\-DGCS\_\-VERR}}\item[{\em \hypertarget{UNIV_8h_a180a72}{ {\em UNIV\_\-V\_\-DGCS\_\-VERR}} \label{UNIV_8h_a180a72} }]VME bus error \index{UNIV_V_DGCS_LERR@{UNIV\_\-V\_\-DGCS\_\-LERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_LERR@{UNIV\_\-V\_\-DGCS\_\-LERR}}\item[{\em \hypertarget{UNIV_8h_a180a73}{ {\em UNIV\_\-V\_\-DGCS\_\-LERR}} \label{UNIV_8h_a180a73} }]PCI bus error \index{UNIV_V_DGCS_DONE@{UNIV\_\-V\_\-DGCS\_\-DONE}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_DONE@{UNIV\_\-V\_\-DGCS\_\-DONE}}\item[{\em \hypertarget{UNIV_8h_a180a74}{ {\em UNIV\_\-V\_\-DGCS\_\-DONE}} \label{UNIV_8h_a180a74} }]DMA done \index{UNIV_V_DGCS_RSVD12@{UNIV\_\-V\_\-DGCS\_\-RSVD12}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_RSVD12@{UNIV\_\-V\_\-DGCS\_\-RSVD12}}\item[{\em \hypertarget{UNIV_8h_a180a75}{ {\em UNIV\_\-V\_\-DGCS\_\-RSVD12}} \label{UNIV_8h_a180a75} }]Unused \index{UNIV_V_DGCS_HALT@{UNIV\_\-V\_\-DGCS\_\-HALT}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_HALT@{UNIV\_\-V\_\-DGCS\_\-HALT}}\item[{\em \hypertarget{UNIV_8h_a180a76}{ {\em UNIV\_\-V\_\-DGCS\_\-HALT}} \label{UNIV_8h_a180a76} }]DMA halted \index{UNIV_V_DGCS_STOP@{UNIV\_\-V\_\-DGCS\_\-STOP}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_STOP@{UNIV\_\-V\_\-DGCS\_\-STOP}}\item[{\em \hypertarget{UNIV_8h_a180a77}{ {\em UNIV\_\-V\_\-DGCS\_\-STOP}} \label{UNIV_8h_a180a77} }]DMA stopped \index{UNIV_V_DGCS_ACT@{UNIV\_\-V\_\-DGCS\_\-ACT}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_ACT@{UNIV\_\-V\_\-DGCS\_\-ACT}}\item[{\em \hypertarget{UNIV_8h_a180a78}{ {\em UNIV\_\-V\_\-DGCS\_\-ACT}} \label{UNIV_8h_a180a78} }]DMA active \index{UNIV_V_DGCS_VOFF@{UNIV\_\-V\_\-DGCS\_\-VOFF}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_VOFF@{UNIV\_\-V\_\-DGCS\_\-VOFF}}\item[{\em \hypertarget{UNIV_8h_a180a79}{ {\em UNIV\_\-V\_\-DGCS\_\-VOFF}} \label{UNIV_8h_a180a79} }]VME Bus Off Counter (timer) 0000 = 0usec, 0001 = 16usec, 0010 = 32usec, 0011 = 64usec, 0100 = 128usec, 0101 = 256usec, 0110 = 512usec, 0111 = 1024usec, 1000 = 2usec, 1001 = 4usec, 1010 = 8usec, Others = reserved The DMA will not re-request the VME Master until this timer expires. \index{UNIV_V_DGCS_VON@{UNIV\_\-V\_\-DGCS\_\-VON}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_VON@{UNIV\_\-V\_\-DGCS\_\-VON}}\item[{\em \hypertarget{UNIV_8h_a180a80}{ {\em UNIV\_\-V\_\-DGCS\_\-VON}} \label{UNIV_8h_a180a80} }]VME Bus On Counter (bytes) 000 = until done, 001 = 256 bytes, 010 = 512 bytes, 011 = 1024 bytes, 100 = 2048 bytes, 101 = 4096 bytes, 110 = 8192 bytes, 111 = 16384 bytes others = reserved (what others?) \index{UNIV_V_DGCS_RSVD23@{UNIV\_\-V\_\-DGCS\_\-RSVD23}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_RSVD23@{UNIV\_\-V\_\-DGCS\_\-RSVD23}}\item[{\em \hypertarget{UNIV_8h_a180a81}{ {\em UNIV\_\-V\_\-DGCS\_\-RSVD23}} \label{UNIV_8h_a180a81} }]Unused \index{UNIV_V_DGCS_RSVD24@{UNIV\_\-V\_\-DGCS\_\-RSVD24}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_RSVD24@{UNIV\_\-V\_\-DGCS\_\-RSVD24}}\item[{\em \hypertarget{UNIV_8h_a180a82}{ {\em UNIV\_\-V\_\-DGCS\_\-RSVD24}} \label{UNIV_8h_a180a82} }]Unused \index{UNIV_V_DGCS_CHAIN@{UNIV\_\-V\_\-DGCS\_\-CHAIN}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_CHAIN@{UNIV\_\-V\_\-DGCS\_\-CHAIN}}\item[{\em \hypertarget{UNIV_8h_a180a83}{ {\em UNIV\_\-V\_\-DGCS\_\-CHAIN}} \label{UNIV_8h_a180a83} }]Enable DMA chaining \index{UNIV_V_DGCS_RSVD28@{UNIV\_\-V\_\-DGCS\_\-RSVD28}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_RSVD28@{UNIV\_\-V\_\-DGCS\_\-RSVD28}}\item[{\em \hypertarget{UNIV_8h_a180a84}{ {\em UNIV\_\-V\_\-DGCS\_\-RSVD28}} \label{UNIV_8h_a180a84} }]Unused \index{UNIV_V_DGCS_HALT_REQ@{UNIV\_\-V\_\-DGCS\_\-HALT\_\-REQ}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_HALT_REQ@{UNIV\_\-V\_\-DGCS\_\-HALT\_\-REQ}}\item[{\em \hypertarget{UNIV_8h_a180a85}{ {\em UNIV\_\-V\_\-DGCS\_\-HALT\_\-REQ}} \label{UNIV_8h_a180a85} }]DMA Halt Request 0 = No Effect, 1 = Halt the DMA transfer at the completion of the current command packet. \index{UNIV_V_DGCS_STOP_REQ@{UNIV\_\-V\_\-DGCS\_\-STOP\_\-REQ}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_STOP_REQ@{UNIV\_\-V\_\-DGCS\_\-STOP\_\-REQ}}\item[{\em \hypertarget{UNIV_8h_a180a86}{ {\em UNIV\_\-V\_\-DGCS\_\-STOP\_\-REQ}} \label{UNIV_8h_a180a86} }]DMA Stop Request 0 = No Effect, 1 = Stop the DMA transfer when all buffered data has been written \index{UNIV_V_DGCS_GO@{UNIV\_\-V\_\-DGCS\_\-GO}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_GO@{UNIV\_\-V\_\-DGCS\_\-GO}}\item[{\em \hypertarget{UNIV_8h_a180a87}{ {\em UNIV\_\-V\_\-DGCS\_\-GO}} \label{UNIV_8h_a180a87} }]DMA Go Bit \index{UNIV_V_DGCS_INT_ENB_ERR@{UNIV\_\-V\_\-DGCS\_\-INT\_\-ENB\_\-ERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_INT_ENB_ERR@{UNIV\_\-V\_\-DGCS\_\-INT\_\-ENB\_\-ERR}}\item[{\em \hypertarget{UNIV_8h_a180a88}{ {\em UNIV\_\-V\_\-DGCS\_\-INT\_\-ENB\_\-ERR}} \label{UNIV_8h_a180a88} }]Beginning of ERR interrupt enable bits \index{UNIV_V_DGCS_INT_ENB_SUC@{UNIV\_\-V\_\-DGCS\_\-INT\_\-ENB\_\-SUC}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_INT_ENB_SUC@{UNIV\_\-V\_\-DGCS\_\-INT\_\-ENB\_\-SUC}}\item[{\em \hypertarget{UNIV_8h_a180a89}{ {\em UNIV\_\-V\_\-DGCS\_\-INT\_\-ENB\_\-SUC}} \label{UNIV_8h_a180a89} }]Beginning of SUC interrupt nable bits Note that this field has 1 unused bit in it \index{UNIV_V_DGCS_INT_ENB_ALL@{UNIV\_\-V\_\-DGCS\_\-INT\_\-ENB\_\-ALL}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_INT_ENB_ALL@{UNIV\_\-V\_\-DGCS\_\-INT\_\-ENB\_\-ALL}}\item[{\em \hypertarget{UNIV_8h_a180a90}{ {\em UNIV\_\-V\_\-DGCS\_\-INT\_\-ENB\_\-ALL}} \label{UNIV_8h_a180a90} }]Beginning of all interrupt enable bits \index{UNIV_V_DGCS_INT_STS_ERR@{UNIV\_\-V\_\-DGCS\_\-INT\_\-STS\_\-ERR}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_INT_STS_ERR@{UNIV\_\-V\_\-DGCS\_\-INT\_\-STS\_\-ERR}}\item[{\em \hypertarget{UNIV_8h_a180a91}{ {\em UNIV\_\-V\_\-DGCS\_\-INT\_\-STS\_\-ERR}} \label{UNIV_8h_a180a91} }]Beginning of ERR interrupt status bits \index{UNIV_V_DGCS_INT_STS_SUC@{UNIV\_\-V\_\-DGCS\_\-INT\_\-STS\_\-SUC}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_INT_STS_SUC@{UNIV\_\-V\_\-DGCS\_\-INT\_\-STS\_\-SUC}}\item[{\em \hypertarget{UNIV_8h_a180a92}{ {\em UNIV\_\-V\_\-DGCS\_\-INT\_\-STS\_\-SUC}} \label{UNIV_8h_a180a92} }]Beginning of SUC interrupt status bits \index{UNIV_V_DGCS_INT_STS_ALL@{UNIV\_\-V\_\-DGCS\_\-INT\_\-STS\_\-ALL}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_INT_STS_ALL@{UNIV\_\-V\_\-DGCS\_\-INT\_\-STS\_\-ALL}}\item[{\em \hypertarget{UNIV_8h_a180a93}{ {\em UNIV\_\-V\_\-DGCS\_\-INT\_\-STS\_\-ALL}} \label{UNIV_8h_a180a93} }]Beginning of ALL interrupt status bits \index{UNIV_V_DGCS_STS_ALL@{UNIV\_\-V\_\-DGCS\_\-STS\_\-ALL}!UNIV.h@{UNIV.h}}\index{UNIV.h@{UNIV.h}!UNIV_V_DGCS_STS_ALL@{UNIV\_\-V\_\-DGCS\_\-STS\_\-ALL}}\item[{\em \hypertarget{UNIV_8h_a180a94}{ {\em UNIV\_\-V\_\-DGCS\_\-STS\_\-ALL}} \label{UNIV_8h_a180a94} }]Beginning of all status bits \end{description} \end{Desc} \subsection{Function Documentation} \hypertarget{UNIV_8h_a173}{ \index{UNIV.h@{UNIV.h}!UNIV_bus_master_set@{UNIV\_\-bus\_\-master\_\-set}} \index{UNIV_bus_master_set@{UNIV\_\-bus\_\-master\_\-set}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-bus\_\-master\_\-set]{\setlength{\rightskip}{0pt plus 5cm}int UNIV\_\-bus\_\-master\_\-set (void)}} \label{UNIV_8h_a173} Ensures the UNIVERSE II is a PCI bus master. \begin{Desc} \item[Returns: ]\par The original value of the PCI CSR register.\end{Desc} There is very little reason to use this routine. Vx\-Works initializes the UNIVERSE II to be a PCI bus master, so unless it has been 'unset' there is no reason to set it. It is provided only in the interest of completeness. \hypertarget{UNIV_8h_a174}{ \index{UNIV.h@{UNIV.h}!UNIV_dcp_array_init@{UNIV\_\-dcp\_\-array\_\-init}} \index{UNIV_dcp_array_init@{UNIV\_\-dcp\_\-array\_\-init}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-dcp\_\-array\_\-init]{\setlength{\rightskip}{0pt plus 5cm}void UNIV\_\-dcp\_\-array\_\-init (struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} $\ast$ {\em dcpp}, int {\em cnt})}} \label{UNIV_8h_a174} Initializes an array of Universe DMA Command packets to form a circular list. Only the link field is filled in. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em dcpp}]An array of command packets. \item[{\em cnt}]The number of elements in the command packets.\end{description} \end{Desc} This routine is provided only as a convenience. It will probably be used as an example for the user to write his own initialization. \hypertarget{UNIV_8h_a175}{ \index{UNIV.h@{UNIV.h}!UNIV_dcp_complete@{UNIV\_\-dcp\_\-complete}} \index{UNIV_dcp_complete@{UNIV\_\-dcp\_\-complete}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-dcp\_\-complete]{\setlength{\rightskip}{0pt plus 5cm}void UNIV\_\-dcp\_\-complete (struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} $\ast$ {\em dcpp}, unsigned int {\em dctl}, unsigned int {\em vme\-Adr}, unsigned char $\ast$ {\em lcl\-Adr}, int {\em nbytes})}} \label{UNIV_8h_a175} Complete the DMA Command Packet, ie finishes the job UNIV\_\-dcp\_\-array\_\-init started. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em dcpp}]Pointer the the DMA Command Packet to complete. \item[{\em dctl}]The DCTL control word. \item[{\em vme\-Adr}]The VME address \item[{\em lcl\-Adr}]The local address \item[{\em nbytes}]The number of bytes to transfer.\end{description} \end{Desc} This completes the DMA command packet. The attributes of the transfer, ie, the direction, the datawidth, the VME address space, etc. are all controlled by the DCTL control word. \hypertarget{UNIV_8h_a158}{ \index{UNIV.h@{UNIV.h}!UNIV_DCPP_read@{UNIV\_\-DCPP\_\-read}} \index{UNIV_DCPP_read@{UNIV\_\-DCPP\_\-read}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-DCPP\_\-read]{\setlength{\rightskip}{0pt plus 5cm}unsigned int UNIV\_\-DCPP\_\-read (void)}} \label{UNIV_8h_a158} Reads the DCPP register, (Command Packet Pointer). \begin{Desc} \item[Returns: ]\par The read value. \end{Desc} \hypertarget{UNIV_8h_a159}{ \index{UNIV.h@{UNIV.h}!UNIV_DCPP_write@{UNIV\_\-DCPP\_\-write}} \index{UNIV_DCPP_write@{UNIV\_\-DCPP\_\-write}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-DCPP\_\-write]{\setlength{\rightskip}{0pt plus 5cm}void UNIV\_\-DCPP\_\-write (const struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} $\ast$ {\em dcpp})}} \label{UNIV_8h_a159} Write the DCPP register with the head of a DMA linked list. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em dcpp}]The DMA linked list head. \end{description} \end{Desc} \hypertarget{UNIV_8h_a166}{ \index{UNIV.h@{UNIV.h}!UNIV_DGCS_bclr@{UNIV\_\-DGCS\_\-bclr}} \index{UNIV_DGCS_bclr@{UNIV\_\-DGCS\_\-bclr}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-DGCS\_\-bclr]{\setlength{\rightskip}{0pt plus 5cm}unsigned int UNIV\_\-DGCS\_\-bclr (unsigned int {\em bits\-To\-Clr})}} \label{UNIV_8h_a166} Clears the specified bits in the DGCS register, (General Control/Status Register). \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em bits\-To\-Clr}]The value to write. \end{description} \end{Desc} \begin{Desc} \item[Returns: ]\par The original value before modification.\end{Desc} Clears the specified bits. This implements the following pseudocode \footnotesize\begin{verbatim} *adr &= ~bitsToClr; \end{verbatim}\normalsize \begin{Desc} \item[Warning: ]\par This is not done in an indivisible manner. \end{Desc} \hypertarget{UNIV_8h_a167}{ \index{UNIV.h@{UNIV.h}!UNIV_DGCS_bmod@{UNIV\_\-DGCS\_\-bmod}} \index{UNIV_DGCS_bmod@{UNIV\_\-DGCS\_\-bmod}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-DGCS\_\-bmod]{\setlength{\rightskip}{0pt plus 5cm}unsigned int UNIV\_\-DGCS\_\-bmod (unsigned int {\em mod\-Msk}, unsigned int {\em value})}} \label{UNIV_8h_a167} Modifies a selected set of bits in the DGCS register. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em mod\-Msk}]Which bits to modify. \item[{\em value}]The new values. \end{description} \end{Desc} \begin{Desc} \item[Returns: ]\par The original value before modification.\end{Desc} \begin{Desc} \item[Warning: ]\par This is not done in an indivisible manner. \end{Desc} \hypertarget{UNIV_8h_a168}{ \index{UNIV.h@{UNIV.h}!UNIV_DGCS_bset@{UNIV\_\-DGCS\_\-bset}} \index{UNIV_DGCS_bset@{UNIV\_\-DGCS\_\-bset}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-DGCS\_\-bset]{\setlength{\rightskip}{0pt plus 5cm}unsigned int UNIV\_\-DGCS\_\-bset (unsigned int {\em bits\-To\-Set})}} \label{UNIV_8h_a168} Sets the specified bits in the DGCS register. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em bits\-To\-Set}]The set mask. Bits set to 1 are set. \end{description} \end{Desc} \begin{Desc} \item[Returns: ]\par The original value before the bits are set.\end{Desc} Sets the specified bits. This implements the following pseudocode \footnotesize\begin{verbatim} *adr |= bitsToSet; \end{verbatim}\normalsize \begin{Desc} \item[Warning: ]\par This is not done in an indivisible manner. \end{Desc} \hypertarget{UNIV_8h_a162}{ \index{UNIV.h@{UNIV.h}!UNIV_DGCS_read@{UNIV\_\-DGCS\_\-read}} \index{UNIV_DGCS_read@{UNIV\_\-DGCS\_\-read}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-DGCS\_\-read]{\setlength{\rightskip}{0pt plus 5cm}unsigned int UNIV\_\-DGCS\_\-read (void)}} \label{UNIV_8h_a162} Reads the DGCS register, (General Control/Status Register. \begin{Desc} \item[Returns: ]\par The read value. \end{Desc} \hypertarget{UNIV_8h_a169}{ \index{UNIV.h@{UNIV.h}!UNIV_DGCS_write@{UNIV\_\-DGCS\_\-write}} \index{UNIV_DGCS_write@{UNIV\_\-DGCS\_\-write}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-DGCS\_\-write]{\setlength{\rightskip}{0pt plus 5cm}unsigned int UNIV\_\-DGCS\_\-write (unsigned int {\em value})}} \label{UNIV_8h_a169} Writes the DGCS register, (General Control/Status Register). \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em value}]The value to write. \end{description} \end{Desc} \hypertarget{UNIV_8h_a160}{ \index{UNIV.h@{UNIV.h}!UNIV_DTBC_read@{UNIV\_\-DTBC\_\-read}} \index{UNIV_DTBC_read@{UNIV\_\-DTBC\_\-read}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-DTBC\_\-read]{\setlength{\rightskip}{0pt plus 5cm}unsigned int UNIV\_\-DTBC\_\-read (void)}} \label{UNIV_8h_a160} Reads the DTBC register, (Transfer Byte Count). \begin{Desc} \item[Returns: ]\par The read value. \end{Desc} \hypertarget{UNIV_8h_a161}{ \index{UNIV.h@{UNIV.h}!UNIV_DTBC_write@{UNIV\_\-DTBC\_\-write}} \index{UNIV_DTBC_write@{UNIV\_\-DTBC\_\-write}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-DTBC\_\-write]{\setlength{\rightskip}{0pt plus 5cm}void UNIV\_\-DTBC\_\-write (unsigned int {\em byte\-Count})}} \label{UNIV_8h_a161} Writes the DTBC register, (Transfer Byte Count). \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em byte\-Count}]The value of the transfer byte counter. \end{description} \end{Desc} \hypertarget{UNIV_8h_a163}{ \index{UNIV.h@{UNIV.h}!UNIV_go@{UNIV\_\-go}} \index{UNIV_go@{UNIV\_\-go}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-go]{\setlength{\rightskip}{0pt plus 5cm}unsigned int UNIV\_\-go (void)}} \label{UNIV_8h_a163} Initiates a start on on a DMA operation by hitting to GO bit in the DGCS register. \begin{Desc} \item[Returns: ]\par The original value of the DGCS register before the GO bit was set. \end{Desc} \hypertarget{UNIV_8h_a176}{ \index{UNIV.h@{UNIV.h}!UNIV_go_at@{UNIV\_\-go\_\-at}} \index{UNIV_go_at@{UNIV\_\-go\_\-at}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-go\_\-at]{\setlength{\rightskip}{0pt plus 5cm}void UNIV\_\-go\_\-at (struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} $\ast$ {\em head})}} \label{UNIV_8h_a176} This initiates a chain UNIV transfer by the Universe at the specified command head. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em head}]Pointer to the head of the linked list of command packets.\end{description} \end{Desc} This initiates a chain UNIV transfer by the Universe at the specified command head. It is assumed that the linked list has been programmed and is properly terminated. After the transfer count is cleared and the head of the command packet is placed in the Command Packet Pointer register, the GO bit is set. An EIEIO instruction should be performed right before the GO bit is set to ensure that the previous two writes have been flushed to the UNIV registers. It is recommended that this function, rather the combination be used, since this function avoids unnecessary EIEIO's. \hypertarget{UNIV_8h_a170}{ \index{UNIV.h@{UNIV.h}!UNIV_int_connect@{UNIV\_\-int\_\-connect}} \index{UNIV_int_connect@{UNIV\_\-int\_\-connect}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-int\_\-connect]{\setlength{\rightskip}{0pt plus 5cm}int UNIV\_\-int\_\-connect (unsigned int {\em which}, \hyperlink{UNIV_8h_a23}{UNIV\_\-isr} {\em routine}, void $\ast$ {\em parameter})}} \label{UNIV_8h_a170} Connects a ISR routine to service the UNIVERSET II interrupts. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em which}]A bit mask of which interrupts to service. \item[{\em routine}]The interrupt service routine. The callback signature is defined by the typedef UNIV\_\-isr and is\end{description} \end{Desc} \footnotesize\begin{verbatim} void (*isr_routine) (void *parameter) \end{verbatim}\normalsize \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em parameter}]A user supplied parameter passed transparently through to the ISR routine. \end{description} \end{Desc} \begin{Desc} \item[Returns: ]\par Status.\end{Desc} Except in very simple cases, any realistic implementation will connect to all possible sources. A layer of software will then have to be written to handle the dispatching of the interrupts to correct user. A possible model is a QIO model, where the user submits IO requests to a central 'driver'. The IOs are placed on a que and the driver services them one by one. Part of the IO information would be a user supplied callback routine to handle the asynchronous completion. The {\em which} parameter enable the sources on the Universe to generate interrupts. These are from the set \footnotesize\begin{verbatim} UNIV_M_DGCS_INT_P_ERR UNIV_M_DGCS_INT_VERR UNIV_M_DGCS_INT_LERR UNIV_M_DGCS_INT_DONE UNIV_M_DGCS_INT_HALT UNIV_M_DGCS_INT_STOP \end{verbatim}\normalsize These indicate which sources this particular ISR is willing to service. \hypertarget{UNIV_8h_a172}{ \index{UNIV.h@{UNIV.h}!UNIV_int_disable@{UNIV\_\-int\_\-disable}} \index{UNIV_int_disable@{UNIV\_\-int\_\-disable}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-int\_\-disable]{\setlength{\rightskip}{0pt plus 5cm}int UNIV\_\-int\_\-disable (void)}} \label{UNIV_8h_a172} Disables delivery of interrupts from the UNIVERSE II. \begin{Desc} \item[Returns: ]\par Status \end{Desc} \hypertarget{UNIV_8h_a171}{ \index{UNIV.h@{UNIV.h}!UNIV_int_enable@{UNIV\_\-int\_\-enable}} \index{UNIV_int_enable@{UNIV\_\-int\_\-enable}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-int\_\-enable]{\setlength{\rightskip}{0pt plus 5cm}int UNIV\_\-int\_\-enable (void)}} \label{UNIV_8h_a171} Enables delivery of interrupts from the UNIVERSE II. \begin{Desc} \item[Returns: ]\par Status \end{Desc} \hypertarget{UNIV_8h_a164}{ \index{UNIV.h@{UNIV.h}!UNIV_request_halt@{UNIV\_\-request\_\-halt}} \index{UNIV_request_halt@{UNIV\_\-request\_\-halt}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-request\_\-halt]{\setlength{\rightskip}{0pt plus 5cm}unsigned int UNIV\_\-request\_\-halt (void)}} \label{UNIV_8h_a164} Request a halt on an ongoing DMA operation. \begin{Desc} \item[Returns: ]\par The original value of the DGCS register before the HALT\_\-REQ bit was set.\end{Desc} A HALT request is honored at the end of processing a DMA packet. The UNIVERSE II User's manual (p 2-90) states: \char`\"{}Linked-list operation can be halted by setting the HALT\_\-REQ bit in the DGCS register. When the HALT\_\-REG bit is set, the DMA terminates when all transfers defined by the current command packet is complete. It then load the next command packtet into its registers. The HALT bit in the DGCS register is asserted, and the ACT bit in the DGCS register is cleared. The PROCESSED bit in the linked-list is set to \char`\"{}1\char`\"{} approximately 1us after the HALT bit is set: therefore after a DMA halt the user should wait at least 1us before checking the PROCESSED bit.\char`\"{} \char`\"{}The DMA can be restarted by clearing the HALT status bit and setting the GO bit if desired during the same register write. If the DMA is restarted, the ACT is set by the Universe II and execution continues as if no HALT had occurred: i.e. the Universe II processes the current command packet.\char`\"{} Note that the HALT is done as an asynchronous operation, it is merely a request to HALT. The user must wait till the halt is actually done by either fielding the HALT interrupt or polling the HALTED status bit. \hypertarget{UNIV_8h_a165}{ \index{UNIV.h@{UNIV.h}!UNIV_request_stop@{UNIV\_\-request\_\-stop}} \index{UNIV_request_stop@{UNIV\_\-request\_\-stop}!UNIV.h@{UNIV.h}} \subsubsection[UNIV\_\-request\_\-stop]{\setlength{\rightskip}{0pt plus 5cm}unsigned int UNIV\_\-request\_\-stop (void)}} \label{UNIV_8h_a165} Request a stop on an ongoing DMA operation. \begin{Desc} \item[Returns: ]\par The original value of the DGCS register before the STOP\_\-REQ bit was set.\end{Desc} A STOP request waits until all buffered data is written. The Universe II User's manual (page 2-90) states: \char`\"{}In contrast to a HALT, the DMA can also be immediately terminated through the STOP\_\-REQ bit. This will stop all DMA operations on the source bus immediately, and set the STOP bit in the same register when the last piece of queued data in the DMA FIFO has been written to the destination bus.\char`\"{} \char`\"{}Once stopped the DVA, DLA and DTBC registers contain values indicating the addresses to read/write and the number of bytes remaining in the transfer. Clearing the STOP bit and setting the GO bit will cause the DMA to start up agian from where it left off, including continuing with subsequent command packets in the list.\char`\"{} Note that the STOP is done as an asynchronous operation, it is merely a request to STOP. The user must wait till the halt is actually done by either fielding the STOP interrupt or polling the HALTED status bit.