\hypertarget{UNIV_8c}{ \section{UNIV.c File Reference} \label{UNIV_8c}\index{UNIV.c@{UNIV.c}} } Universe II Utilities, Interface. {\tt \#include $<$vx\-Works.h$>$}\par {\tt \#include $<$sys\-Lib.h$>$}\par {\tt \#include $<$int\-Lib.h$>$}\par {\tt \#include $<$iv.h$>$}\par {\tt \#include \char`\"{}MV2X/mv2600.h\char`\"{}}\par {\tt \#include \char`\"{}./universe.h\char`\"{}}\par {\tt \#include \char`\"{}UNIV\_\-vxworks.h\char`\"{}}\par {\tt \#include \char`\"{}BVME/UNIV.h\char`\"{}}\par {\tt \#include \char`\"{}BBC/BSWP.ih\char`\"{}}\par \subsection*{Defines} \begin{CompactItemize} \item \hypertarget{UNIV_8c_a0}{ \index{UNIV_A_DGCS@{UNIV\_\-A\_\-DGCS}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_A_DGCS@{UNIV\_\-A\_\-DGCS}} \#define \hyperlink{UNIV_8c_a0}{UNIV\_\-A\_\-DGCS}\ (volatile unsigned int $\ast$)UNIVERSE\_\-DGCS} \label{UNIV_8c_a0} \begin{CompactList}\small\item\em Address of General Control/Status Register.\item\end{CompactList}\item \hypertarget{UNIV_8c_a1}{ \index{UNIV_A_DCPP@{UNIV\_\-A\_\-DCPP}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_A_DCPP@{UNIV\_\-A\_\-DCPP}} \#define \hyperlink{UNIV_8c_a1}{UNIV\_\-A\_\-DCPP}\ (volatile unsigned int $\ast$)UNIVERSE\_\-DCPP} \label{UNIV_8c_a1} \begin{CompactList}\small\item\em Address of Command Packet Pointer Register.\item\end{CompactList}\item \hypertarget{UNIV_8c_a2}{ \index{UNIV_A_DTBC@{UNIV\_\-A\_\-DTBC}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_A_DTBC@{UNIV\_\-A\_\-DTBC}} \#define \hyperlink{UNIV_8c_a2}{UNIV\_\-A\_\-DTBC}\ (volatile unsigned int $\ast$)UNIVERSE\_\-DTBC} \label{UNIV_8c_a2} \begin{CompactList}\small\item\em Address of Transfer Byte Count Register.\item\end{CompactList}\item \hypertarget{UNIV_8c_a3}{ \index{UNIV_A_PCI_CSR@{UNIV\_\-A\_\-PCI\_\-CSR}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_A_PCI_CSR@{UNIV\_\-A\_\-PCI\_\-CSR}} \#define \hyperlink{UNIV_8c_a3}{UNIV\_\-A\_\-PCI\_\-CSR}\ (volatile unsigned int $\ast$)UNIVERSE\_\-PCI\_\-CSR} \label{UNIV_8c_a3} \begin{CompactList}\small\item\em Address of PCI CSR Register.\item\end{CompactList}\item \hypertarget{UNIV_8c_a4}{ \index{UNIV_A_LINT_EN@{UNIV\_\-A\_\-LINT\_\-EN}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_A_LINT_EN@{UNIV\_\-A\_\-LINT\_\-EN}} \#define \hyperlink{UNIV_8c_a4}{UNIV\_\-A\_\-LINT\_\-EN}\ (volatile unsigned int $\ast$)UNIVERSE\_\-LINT\_\-EN} \label{UNIV_8c_a4} \begin{CompactList}\small\item\em Address of LINT Enable (PCI interrupt).\item\end{CompactList}\item \hypertarget{UNIV_8c_a5}{ \index{UNIV_A_LINT_STAT@{UNIV\_\-A\_\-LINT\_\-STAT}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_A_LINT_STAT@{UNIV\_\-A\_\-LINT\_\-STAT}} \#define \hyperlink{UNIV_8c_a5}{UNIV\_\-A\_\-LINT\_\-STAT}\ (volatile unsigned int $\ast$)UNIVERSE\_\-LINT\_\-STAT} \label{UNIV_8c_a5} \begin{CompactList}\small\item\em Addesss of LINT Status Register.\item\end{CompactList}\item \hypertarget{UNIV_8c_a6}{ \index{DGCS_ERRMSK@{DGCS\_\-ERRMSK}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!DGCS_ERRMSK@{DGCS\_\-ERRMSK}} \#define \hyperlink{UNIV_8c_a6}{DGCS\_\-ERRMSK}\ (DGCS\_\-LERR $|$ DGCS\_\-VERR $|$ DGCS\_\-P\_\-ERR)} \label{UNIV_8c_a6} \begin{CompactList}\small\item\em Error status bits.\item\end{CompactList}\item \hypertarget{UNIV_8c_a7}{ \index{DGCS_STATUS@{DGCS\_\-STATUS}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!DGCS_STATUS@{DGCS\_\-STATUS}} \#define \hyperlink{UNIV_8c_a7}{DGCS\_\-STATUS}\ (DGCS\_\-ACT $|$ DGCS\_\-DONE $|$ DGCS\_\-ERRMSK)} \label{UNIV_8c_a7} \begin{CompactList}\small\item\em Success Status bits.\item\end{CompactList}\item \hypertarget{UNIV_8c_a8}{ \index{eieio@{eieio}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!eieio@{eieio}} \#define \hyperlink{UNIV_8c_a8}{eieio}\ asm volatile (\char`\"{}eieio\char`\"{}::)} \label{UNIV_8c_a8} \begin{CompactList}\small\item\em Drops an eieio instruction.\item\end{CompactList}\end{CompactItemize} \subsection*{Functions} \begin{CompactItemize} \item unsigned int \hyperlink{UNIV_8c_a9}{read\-Reg} (volatile unsigned int $\ast$adr) \begin{CompactList}\small\item\em Internal function to read a 32 PCI address, with eieio synch.\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8c_a10}{mread\-Reg} (volatile unsigned int $\ast$adr) \begin{CompactList}\small\item\em Internal function to read a 32 PCI address, no eieio synch.\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8c_a11}{bclr\-Reg} (volatile unsigned int $\ast$adr, unsigned int clr\-Msk) \begin{CompactList}\small\item\em Clears the specified bits.\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8c_a12}{bmod\-Reg} (volatile unsigned int $\ast$adr, unsigned int mod\-Msk, unsigned int val) \begin{CompactList}\small\item\em Modifies a selected set of bits.\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8c_a13}{bset\-Reg} (volatile unsigned int $\ast$adr, unsigned int set\-Msk) \begin{CompactList}\small\item\em Sets the specified bits.\item\end{CompactList}\item void \hyperlink{UNIV_8c_a14}{write\-Reg} (volatile unsigned int $\ast$adr, unsigned int value) \begin{CompactList}\small\item\em Internal function to write a 32 PCI address, with eieio synch.\item\end{CompactList}\item void \hyperlink{UNIV_8c_a15}{mwrite\-Reg} (volatile unsigned int $\ast$adr, unsigned int value) \begin{CompactList}\small\item\em Internal function to write a 32 PCI address, no eieio synch.\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8c_a16}{read\-DGCS} (void) \begin{CompactList}\small\item\em Reads the DGCS register.\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8c_a17}{bclr\-DGCS} (unsigned int bits\-To\-Clr) \begin{CompactList}\small\item\em Clears the specified bits in the DGCS register.\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8c_a18}{bmod\-DGCS} (unsigned int bits\-To\-Mod, unsigned int value) \begin{CompactList}\small\item\em Modifies a selected set of bits in the DGCS register.\item\end{CompactList}\item unsigned int \hyperlink{UNIV_8c_a19}{bset\-DGCS} (unsigned int bits\-To\-Clr) \begin{CompactList}\small\item\em Sets the specified bits in the DGCS register.\item\end{CompactList}\item void \hyperlink{UNIV_8c_a20}{write\-DGCS} (unsigned int value) \begin{CompactList}\small\item\em Writes the DGCS register.\item\end{CompactList}\item \hypertarget{UNIV_8c_a21}{ \index{UNIV_DCPP_read@{UNIV\_\-DCPP\_\-read}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_DCPP_read@{UNIV\_\-DCPP\_\-read}} \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} $\ast$ {\bf UNIV\_\-DCPP\_\-read} (void)} \label{UNIV_8c_a21} \item \hypertarget{UNIV_8c_a22}{ \index{UNIV_DCPP_write@{UNIV\_\-DCPP\_\-write}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_DCPP_write@{UNIV\_\-DCPP\_\-write}} void {\bf UNIV\_\-DCPP\_\-write} (const struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} $\ast$dcpp)} \label{UNIV_8c_a22} \item \hypertarget{UNIV_8c_a23}{ \index{UNIV_DTBC_read@{UNIV\_\-DTBC\_\-read}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_DTBC_read@{UNIV\_\-DTBC\_\-read}} unsigned int {\bf UNIV\_\-DTBC\_\-read} (void)} \label{UNIV_8c_a23} \item \hypertarget{UNIV_8c_a24}{ \index{UNIV_DTBC_write@{UNIV\_\-DTBC\_\-write}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_DTBC_write@{UNIV\_\-DTBC\_\-write}} void {\bf UNIV\_\-DTBC\_\-write} (unsigned int byte\-Count)} \label{UNIV_8c_a24} \item \hypertarget{UNIV_8c_a25}{ \index{UNIV_DGCS_read@{UNIV\_\-DGCS\_\-read}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_DGCS_read@{UNIV\_\-DGCS\_\-read}} unsigned int {\bf UNIV\_\-DGCS\_\-read} (void)} \label{UNIV_8c_a25} \item \hypertarget{UNIV_8c_a26}{ \index{UNIV_DGCS_bclr@{UNIV\_\-DGCS\_\-bclr}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_DGCS_bclr@{UNIV\_\-DGCS\_\-bclr}} unsigned int {\bf UNIV\_\-DGCS\_\-bclr} (unsigned int bits\-To\-Clr)} \label{UNIV_8c_a26} \item \hypertarget{UNIV_8c_a27}{ \index{UNIV_DGCS_bmod@{UNIV\_\-DGCS\_\-bmod}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_DGCS_bmod@{UNIV\_\-DGCS\_\-bmod}} unsigned int {\bf UNIV\_\-DGCS\_\-bmod} (unsigned int bits\-To\-Mod, unsigned int value)} \label{UNIV_8c_a27} \item \hypertarget{UNIV_8c_a28}{ \index{UNIV_DGCS_bset@{UNIV\_\-DGCS\_\-bset}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_DGCS_bset@{UNIV\_\-DGCS\_\-bset}} unsigned int {\bf UNIV\_\-DGCS\_\-bset} (unsigned int bits\-To\-Set)} \label{UNIV_8c_a28} \item \hypertarget{UNIV_8c_a29}{ \index{UNIV_DGCS_write@{UNIV\_\-DGCS\_\-write}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_DGCS_write@{UNIV\_\-DGCS\_\-write}} void {\bf UNIV\_\-DGCS\_\-write} (unsigned int value)} \label{UNIV_8c_a29} \item \hypertarget{UNIV_8c_a30}{ \index{UNIV_go@{UNIV\_\-go}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_go@{UNIV\_\-go}} unsigned int {\bf UNIV\_\-go} (void)} \label{UNIV_8c_a30} \item \hypertarget{UNIV_8c_a31}{ \index{UNIV_request_halt@{UNIV\_\-request\_\-halt}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_request_halt@{UNIV\_\-request\_\-halt}} unsigned int {\bf UNIV\_\-request\_\-halt} (void)} \label{UNIV_8c_a31} \item \hypertarget{UNIV_8c_a32}{ \index{UNIV_request_stop@{UNIV\_\-request\_\-stop}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_request_stop@{UNIV\_\-request\_\-stop}} unsigned int {\bf UNIV\_\-request\_\-stop} (void)} \label{UNIV_8c_a32} \item \hypertarget{UNIV_8c_a33}{ \index{UNIV_go_at@{UNIV\_\-go\_\-at}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_go_at@{UNIV\_\-go\_\-at}} void {\bf UNIV\_\-go\_\-at} (struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} $\ast$head)} \label{UNIV_8c_a33} \item \hypertarget{UNIV_8c_a34}{ \index{UNIV_dcp_array_init@{UNIV\_\-dcp\_\-array\_\-init}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_dcp_array_init@{UNIV\_\-dcp\_\-array\_\-init}} void {\bf UNIV\_\-dcp\_\-array\_\-init} (struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} $\ast$dcpp, int cnt)} \label{UNIV_8c_a34} \item \hypertarget{UNIV_8c_a35}{ \index{UNIV_dcp_complete@{UNIV\_\-dcp\_\-complete}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_dcp_complete@{UNIV\_\-dcp\_\-complete}} void {\bf UNIV\_\-dcp\_\-complete} (struct \hyperlink{struct__UNIV__dcp}{\_\-UNIV\_\-dcp} $\ast$dcpp, unsigned int dctl, unsigned int vme\-Adr, unsigned char $\ast$lcl\-Adr, int nbytes)} \label{UNIV_8c_a35} \item \hypertarget{UNIV_8c_a36}{ \index{UNIV_int_connect@{UNIV\_\-int\_\-connect}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_int_connect@{UNIV\_\-int\_\-connect}} int {\bf UNIV\_\-int\_\-connect} (unsigned int which, \hyperlink{UNIV_8h_a23}{UNIV\_\-isr} routine, void $\ast$parameter)} \label{UNIV_8c_a36} \item \hypertarget{UNIV_8c_a37}{ \index{UNIV_int_disable@{UNIV\_\-int\_\-disable}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_int_disable@{UNIV\_\-int\_\-disable}} int {\bf UNIV\_\-int\_\-disable} (void)} \label{UNIV_8c_a37} \item \hypertarget{UNIV_8c_a38}{ \index{UNIV_int_enable@{UNIV\_\-int\_\-enable}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_int_enable@{UNIV\_\-int\_\-enable}} int {\bf UNIV\_\-int\_\-enable} ()} \label{UNIV_8c_a38} \item \hypertarget{UNIV_8c_a39}{ \index{UNIV_bus_master_set@{UNIV\_\-bus\_\-master\_\-set}!UNIV.c@{UNIV.c}}\index{UNIV.c@{UNIV.c}!UNIV_bus_master_set@{UNIV\_\-bus\_\-master\_\-set}} unsigned int {\bf UNIV\_\-bus\_\-master\_\-set} (void)} \label{UNIV_8c_a39} \end{CompactItemize} \subsection{Detailed Description} Universe II Utilities, Interface. \begin{Desc} \item[Author: ]\par JJRussell - \href{mailto:russell@slac.stanford.edu}{\tt russell@slac.stanford.edu}\end{Desc} \subsection{Function Documentation} \hypertarget{UNIV_8c_a17}{ \index{UNIV.c@{UNIV.c}!bclrDGCS@{bclrDGCS}} \index{bclrDGCS@{bclrDGCS}!UNIV.c@{UNIV.c}} \subsubsection[bclrDGCS]{\setlength{\rightskip}{0pt plus 5cm}unsigned int bclr\-DGCS (unsigned int {\em clr\-Msk})\hspace{0.3cm}{\tt \mbox{[}inline, static\mbox{]}}}} \label{UNIV_8c_a17} Clears the specified bits in the DGCS register. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em clr\-Msk}]A mask of bits to clear, bits set to 1 will be cleared. \end{description} \end{Desc} \begin{Desc} \item[Returns: ]\par The original value before clearing.\end{Desc} Clears the specified bits. This implements the following pseudocode \footnotesize\begin{verbatim} *adr &= ~clrMsk; \end{verbatim}\normalsize \begin{Desc} \item[Warning: ]\par This is not done in an indivisible manner. \end{Desc} \hypertarget{UNIV_8c_a11}{ \index{UNIV.c@{UNIV.c}!bclrReg@{bclrReg}} \index{bclrReg@{bclrReg}!UNIV.c@{UNIV.c}} \subsubsection[bclrReg]{\setlength{\rightskip}{0pt plus 5cm}unsigned int bclr\-Reg (volatile unsigned int $\ast$ {\em adr}, unsigned int {\em clr\-Msk})\hspace{0.3cm}{\tt \mbox{[}inline, static\mbox{]}}}} \label{UNIV_8c_a11} Clears the specified bits. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em adr}]The address to clear the bits in. \item[{\em clr\-Msk}]The clear mask. Bits set to 1 are cleared. \end{description} \end{Desc} \begin{Desc} \item[Returns: ]\par The original value before the bits are cleared.\end{Desc} Clears the specified bits. This implements the following pseudocode \footnotesize\begin{verbatim} *adr &= ~clrMsk; \end{verbatim}\normalsize \begin{Desc} \item[Warning: ]\par This is not done in an indivisible manner. \end{Desc} \hypertarget{UNIV_8c_a18}{ \index{UNIV.c@{UNIV.c}!bmodDGCS@{bmodDGCS}} \index{bmodDGCS@{bmodDGCS}!UNIV.c@{UNIV.c}} \subsubsection[bmodDGCS]{\setlength{\rightskip}{0pt plus 5cm}unsigned int bmod\-DGCS (unsigned int {\em mod}, unsigned int {\em val})\hspace{0.3cm}{\tt \mbox{[}inline, static\mbox{]}}}} \label{UNIV_8c_a18} Modifies a selected set of bits in the DGCS register. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em mod\-Msk}]Which bits to modify. \item[{\em value}]The new values. \end{description} \end{Desc} \begin{Desc} \item[Returns: ]\par The original value before modification.\end{Desc} \begin{Desc} \item[Warning: ]\par This is not done in an indivisible manner. \end{Desc} \hypertarget{UNIV_8c_a12}{ \index{UNIV.c@{UNIV.c}!bmodReg@{bmodReg}} \index{bmodReg@{bmodReg}!UNIV.c@{UNIV.c}} \subsubsection[bmodReg]{\setlength{\rightskip}{0pt plus 5cm}unsigned int bmod\-Reg (volatile unsigned int $\ast$ {\em adr}, unsigned int {\em mod\-Msk}, unsigned int {\em value})\hspace{0.3cm}{\tt \mbox{[}inline, static\mbox{]}}}} \label{UNIV_8c_a12} Modifies a selected set of bits. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em adr}]The PCI address to modify. \item[{\em mod\-Msk}]Which bits to modify. \item[{\em value}]The new values. \end{description} \end{Desc} \begin{Desc} \item[Returns: ]\par The original value before modification.\end{Desc} Function to consolidate the setting of individual fields of a PCI memory location. \begin{Desc} \item[Warning: ]\par This is not done in an indivisible manner. \end{Desc} \hypertarget{UNIV_8c_a19}{ \index{UNIV.c@{UNIV.c}!bsetDGCS@{bsetDGCS}} \index{bsetDGCS@{bsetDGCS}!UNIV.c@{UNIV.c}} \subsubsection[bsetDGCS]{\setlength{\rightskip}{0pt plus 5cm}unsigned int bset\-DGCS (unsigned int {\em set})\hspace{0.3cm}{\tt \mbox{[}inline, static\mbox{]}}}} \label{UNIV_8c_a19} Sets the specified bits in the DGCS register. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em set\-Msk}]The set mask. Bits set to 1 are set. \end{description} \end{Desc} \begin{Desc} \item[Returns: ]\par The original value before the bits are set.\end{Desc} Sets the specified bits. This implements the following pseudocode \footnotesize\begin{verbatim} *adr |= setMsk; \end{verbatim}\normalsize \begin{Desc} \item[Warning: ]\par This is not done in an indivisible manner. \end{Desc} \hypertarget{UNIV_8c_a13}{ \index{UNIV.c@{UNIV.c}!bsetReg@{bsetReg}} \index{bsetReg@{bsetReg}!UNIV.c@{UNIV.c}} \subsubsection[bsetReg]{\setlength{\rightskip}{0pt plus 5cm}unsigned int bset\-Reg (volatile unsigned int $\ast$ {\em adr}, unsigned int {\em set\-Msk})\hspace{0.3cm}{\tt \mbox{[}inline, static\mbox{]}}}} \label{UNIV_8c_a13} Sets the specified bits. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em adr}]The PCI address to set the bits in. \item[{\em set\-Msk}]The set mask. Bits set to 1 are set. \end{description} \end{Desc} \begin{Desc} \item[Returns: ]\par The original value before the bits are set.\end{Desc} Sets the specified bits. This implements the following pseudocode \footnotesize\begin{verbatim} *adr |= setMsk; \end{verbatim}\normalsize \begin{Desc} \item[Warning: ]\par This is not done in an indivisible manner. \end{Desc} \hypertarget{UNIV_8c_a10}{ \index{UNIV.c@{UNIV.c}!mreadReg@{mreadReg}} \index{mreadReg@{mreadReg}!UNIV.c@{UNIV.c}} \subsubsection[mreadReg]{\setlength{\rightskip}{0pt plus 5cm}unsigned int mread\-Reg (volatile unsigned int $\ast$ {\em adr})\hspace{0.3cm}{\tt \mbox{[}inline, static\mbox{]}}}} \label{UNIV_8c_a10} Internal function to read a 32 PCI address, no eieio synch. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em The}]local address to read. \end{description} \end{Desc} \begin{Desc} \item[Returns: ]\par The read value.\end{Desc} Function to consolidate the method of reading of a 32bit PCI address. This form is a minimal read, not using the EIEIO instruction. \hypertarget{UNIV_8c_a15}{ \index{UNIV.c@{UNIV.c}!mwriteReg@{mwriteReg}} \index{mwriteReg@{mwriteReg}!UNIV.c@{UNIV.c}} \subsubsection[mwriteReg]{\setlength{\rightskip}{0pt plus 5cm}void mwrite\-Reg (volatile unsigned int $\ast$ {\em adr}, unsigned int {\em value})\hspace{0.3cm}{\tt \mbox{[}inline, static\mbox{]}}}} \label{UNIV_8c_a15} Internal function to write a 32 PCI address, no eieio synch. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em adr}]The local address to write. \item[{\em value}]The value to write.\end{description} \end{Desc} Function to consolidate writing of a 32bit PCI address with a known value. This is done so that any common error checking code can be inserted here. This form is the minimal write, not using the EIEIO instruction to ensure in order reads and writes. \hypertarget{UNIV_8c_a16}{ \index{UNIV.c@{UNIV.c}!readDGCS@{readDGCS}} \index{readDGCS@{readDGCS}!UNIV.c@{UNIV.c}} \subsubsection[readDGCS]{\setlength{\rightskip}{0pt plus 5cm}unsigned int read\-DGCS (void)\hspace{0.3cm}{\tt \mbox{[}inline, static\mbox{]}}}} \label{UNIV_8c_a16} Reads the DGCS register. \begin{Desc} \item[Returns: ]\par The read value. \end{Desc} \hypertarget{UNIV_8c_a9}{ \index{UNIV.c@{UNIV.c}!readReg@{readReg}} \index{readReg@{readReg}!UNIV.c@{UNIV.c}} \subsubsection[readReg]{\setlength{\rightskip}{0pt plus 5cm}unsigned int read\-Reg (volatile unsigned int $\ast$ {\em adr})\hspace{0.3cm}{\tt \mbox{[}inline, static\mbox{]}}}} \label{UNIV_8c_a9} Internal function to read a 32 PCI address, with eieio synch. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em The}]local address to read. \end{description} \end{Desc} \begin{Desc} \item[Returns: ]\par The read value.\end{Desc} Function to consolidate the method of reading of a 32bit PCI address. This form uses the EIEIO to ensure in order reads and writes. \hypertarget{UNIV_8c_a20}{ \index{UNIV.c@{UNIV.c}!writeDGCS@{writeDGCS}} \index{writeDGCS@{writeDGCS}!UNIV.c@{UNIV.c}} \subsubsection[writeDGCS]{\setlength{\rightskip}{0pt plus 5cm}void write\-DGCS (unsigned int {\em value})\hspace{0.3cm}{\tt \mbox{[}inline, static\mbox{]}}}} \label{UNIV_8c_a20} Writes the DGCS register. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em value}]The value to write. \end{description} \end{Desc} \hypertarget{UNIV_8c_a14}{ \index{UNIV.c@{UNIV.c}!writeReg@{writeReg}} \index{writeReg@{writeReg}!UNIV.c@{UNIV.c}} \subsubsection[writeReg]{\setlength{\rightskip}{0pt plus 5cm}void write\-Reg (volatile unsigned int $\ast$ {\em adr}, unsigned int {\em value})\hspace{0.3cm}{\tt \mbox{[}inline, static\mbox{]}}}} \label{UNIV_8c_a14} Internal function to write a 32 PCI address, with eieio synch. \begin{Desc} \item[Parameters: ]\par \begin{description} \item[{\em adr}]The local address to write. \item[{\em value}]The value to write.\end{description} \end{Desc} Function to consolidate writing of a 32bit PCI address with a known value. This is done so that any common error checking code can be inserted here. This form uses the EIEIO to ensure in order reads and writes.